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|
---------- Begin Simulation Statistics ----------
host_inst_rate 139548 # Simulator instruction rate (inst/s)
host_mem_usage 244652 # Number of bytes of host memory used
host_seconds 10956.69 # Real time elapsed on the host
host_tick_rate 63750196 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1528988756 # Number of instructions simulated
sim_seconds 0.698491 # Number of seconds simulated
sim_ticks 698491025500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 172887264 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 187312240 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 17887438 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 187888188 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 187888188 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 149758588 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 10029766 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 1350871673 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.131853 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.433209 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 568349245 42.07% 42.07% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 413717350 30.63% 72.70% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 172321570 12.76% 85.46% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 110104358 8.15% 93.61% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 43035291 3.19% 96.79% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 18507275 1.37% 98.16% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 8248201 0.61% 98.77% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 6558617 0.49% 99.26% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 10029766 0.74% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1350871673 # Number of insts commited each cycle
system.cpu.commit.COM:count 1528988756 # Number of instructions committed
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 1528317614 # Number of committed integer instructions.
system.cpu.commit.COM:loads 384102160 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 533262345 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 17888761 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 257046446 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
system.cpu.cpi 0.913664 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.913664 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 334229227 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14263.584813 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8537.168964 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 332171764 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 29346798000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.006156 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 2057463 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 319131 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 14840434000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005201 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1738332 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 16290.992476 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12654.921756 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 148197195 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 15688323500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.006456 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 963006 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 176041 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 9958980500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005276 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 786965 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 190.400689 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 483389428 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14909.976398 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 9820.395185 # average overall mshr miss latency
system.cpu.dcache.demand_hits 480368959 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 45035121500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.006249 # miss rate for demand accesses
system.cpu.dcache.demand_misses 3020469 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 495172 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 24799414500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005224 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2525297 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.997741 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4086.747665 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 483389428 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 14909.976398 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9820.395185 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 480368959 # number of overall hits
system.cpu.dcache.overall_miss_latency 45035121500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.006249 # miss rate for overall accesses
system.cpu.dcache.overall_misses 3020469 # number of overall misses
system.cpu.dcache.overall_mshr_hits 495172 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 24799414500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005224 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2525297 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 2518885 # number of replacements
system.cpu.dcache.sampled_refs 2522981 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4086.747665 # Cycle average of tags in use
system.cpu.dcache.total_refs 480377321 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 3312879000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2225275 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 18280435 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 1869219380 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 343093281 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 984893533 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 39316255 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 4604424 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 187888188 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 144979108 # Number of cache lines fetched
system.cpu.fetch.Cycles 1039380252 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 2070461 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 999560833 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 1828 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 17988626 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.134496 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 144979108 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 172887264 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.715514 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1390187928 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.363495 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.275570 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 388271402 27.93% 27.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 493387093 35.49% 63.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 229970387 16.54% 79.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 224046516 16.12% 96.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 21915192 1.58% 97.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 25802023 1.86% 99.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 493192 0.04% 99.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 12 0.00% 99.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 6302111 0.45% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1390187928 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 9 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 144979108 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 22807.726664 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 19441.756997 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 144972391 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 153199500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 6717 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 536 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 120169500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000043 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 6181 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 43679.520036 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 144979108 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 22807.726664 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 19441.756997 # average overall mshr miss latency
system.cpu.icache.demand_hits 144972391 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 153199500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses
system.cpu.icache.demand_misses 6717 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 536 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 120169500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000043 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 6181 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.450710 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 923.054085 # Average occupied blocks per context
system.cpu.icache.overall_accesses 144979108 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 22807.726664 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 19441.756997 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 144972391 # number of overall hits
system.cpu.icache.overall_miss_latency 153199500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses
system.cpu.icache.overall_misses 6717 # number of overall misses
system.cpu.icache.overall_mshr_hits 536 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 120169500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000043 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 6181 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1737 # number of replacements
system.cpu.icache.sampled_refs 3319 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 923.054085 # Cycle average of tags in use
system.cpu.icache.total_refs 144972327 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 6794124 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 154306305 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.173655 # Inst execution rate
system.cpu.iew.EXEC:refs 571924541 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 156120222 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1557537154 # num instructions consuming a value
system.cpu.iew.WB:count 1628444279 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.759406 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1182802327 # num instructions producing a value
system.cpu.iew.WB:rate 1.165687 # insts written-back per cycle
system.cpu.iew.WB:sent 1630313962 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 18753816 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 4588629 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 454402470 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 570 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 11948307 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 170547501 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 1786034876 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 415804319 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 21119599 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1639574511 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 357621 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 9695 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 39316255 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 668139 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 80610216 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 294173 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 154646 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 837 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 70300310 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 21387316 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 154646 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 515713 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 18238103 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 2891828761 # number of integer regfile reads
system.cpu.int_regfile_writes 1524435086 # number of integer regfile writes
system.cpu.ipc 1.094494 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.094494 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1929805 0.12% 0.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1078730229 64.96% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 421270517 25.37% 90.44% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 158763559 9.56% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 1660694110 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 783660 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.000472 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 37602 4.80% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 575954 73.50% 78.29% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 170104 21.71% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 1390187928 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.194582 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.080366 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 424313305 30.52% 30.52% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 484307598 34.84% 65.36% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 321495427 23.13% 88.49% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 117467117 8.45% 96.94% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 33024815 2.38% 99.31% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 8635258 0.62% 99.93% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 892156 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 52195 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 57 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1390187928 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.188773 # Inst issue rate
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 9 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 1659547943 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 4712390399 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 1628444270 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 2036676469 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 1786034306 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1660694110 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 570 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 250539717 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 30635 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 443519402 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 789066 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34257.778038 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.587520 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 541510 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 8480718500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.313733 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 247556 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7674629000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313733 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 247556 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1737232 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34158.153227 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.616867 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1403818 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 11388806500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.191923 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 333414 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 10336706500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191923 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 333414 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 2858 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 24.740050 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.358551 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_hits 69 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_miss_latency 69000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 0.975857 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 2789 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 86460000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.975857 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 2789 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2225275 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 2225275 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 5.353417 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 2526298 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34200.604162 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31002.178254 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1945328 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 19869525000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.229969 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 580970 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 18011335500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.229969 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 580970 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.234251 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.418210 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 7675.941579 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13703.908999 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 2526298 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34200.604162 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31002.178254 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1945328 # number of overall hits
system.cpu.l2cache.overall_miss_latency 19869525000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.229969 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 580970 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 18011335500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.229969 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 580970 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 570217 # number of replacements
system.cpu.l2cache.sampled_refs 589293 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 21379.850577 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3154731 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 377230361000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 411577 # number of writebacks
system.cpu.memDep0.conflictingLoads 169465698 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 40622935 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 454402470 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 170547499 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 909615360 # number of misc regfile reads
system.cpu.numCycles 1396982052 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 7556367 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1427299027 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 5884693 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 361176398 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 2156935 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 61 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 4360508954 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 1840516856 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 1743217369 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 971079353 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 39316255 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 11053475 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 315918342 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 168 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 4360508786 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 6080 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 557 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 18505861 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 554 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 3126877109 # The number of ROB reads
system.cpu.rob.rob_writes 3611419620 # The number of ROB writes
system.cpu.timesIdled 237370 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
---------- End Simulation Statistics ----------
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