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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.584023 # Number of seconds simulated
sim_ticks 584023415000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 204231 # Simulator instruction rate (inst/s)
host_tick_rate 78009509 # Simulator tick rate (ticks/s)
host_mem_usage 293660 # Number of bytes of host memory used
host_seconds 7486.57 # Real time elapsed on the host
sim_insts 1528988756 # Number of instructions simulated
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 1168046831 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 253390632 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 253390632 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 16658352 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 238513057 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 219596279 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 188480819 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1362450524 # Number of instructions fetch has processed
system.cpu.fetch.Branches 253390632 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 219596279 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 442052723 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 19279680 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 77230 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 188480819 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 3788271 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1143904596 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.224031 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.207932 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 706004786 61.72% 61.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 32751719 2.86% 64.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 38229862 3.34% 67.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 34570255 3.02% 70.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 20874859 1.82% 72.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 39604957 3.46% 76.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 44518737 3.89% 80.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 36275151 3.17% 83.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 191074270 16.70% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1143904596 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.216935 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.166435 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 421330270 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 186446419 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 405934175 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 21628969 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 108564763 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2493904791 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 108564763 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 460258453 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 50662056 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 15556 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 387000173 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 137403595 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2428714828 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 8220 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 53929654 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 70829494 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2267135297 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 5702873531 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 5702857140 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16391 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 839836270 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2552 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2513 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 298757683 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 586893998 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 222778511 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 352697963 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 138822292 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2327078199 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 9768 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1903699453 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 749156 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 795322101 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1354689551 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 9215 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1143904596 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.664212 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.649949 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 364118171 31.83% 31.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 266012583 23.25% 55.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 191391841 16.73% 71.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 151042401 13.20% 85.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 94875410 8.29% 93.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 46737983 4.09% 97.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 20365340 1.78% 99.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 8494546 0.74% 99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 866321 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1143904596 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 1290623 11.43% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 7282650 64.51% 75.94% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2716745 24.06% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2276794 0.12% 0.12% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1273262556 66.88% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.00% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 457990895 24.06% 91.06% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 170169208 8.94% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1903699453 # Type of FU issued
system.cpu.iq.rate 1.629814 # Inst issue rate
system.cpu.iq.fu_busy_cnt 11290018 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005931 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4963342528 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3124994935 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1860002555 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 148 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6470 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 35 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1912712604 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 73 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 121974892 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 202791838 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 144755 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 2595349 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 73620402 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1258 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 108564763 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 9612649 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1584002 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2327087967 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2265532 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 586893998 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 222780587 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 9768 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1061349 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 44764 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 2595349 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 15395124 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 2700605 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 18095729 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1873365131 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 447946174 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 30334322 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 613940816 # number of memory reference insts executed
system.cpu.iew.exec_branches 173514694 # Number of branches executed
system.cpu.iew.exec_stores 165994642 # Number of stores executed
system.cpu.iew.exec_rate 1.603844 # Inst execution rate
system.cpu.iew.wb_sent 1866291041 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1860002590 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1434917653 # num instructions producing a value
system.cpu.iew.wb_consumers 2113204026 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.592404 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.679025 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 798102573 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 16689612 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1035339833 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.476799 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.996303 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 433023044 41.82% 41.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 272005097 26.27% 68.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 102852786 9.93% 78.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 102343925 9.89% 87.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 37875553 3.66% 91.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 24412247 2.36% 93.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 10662009 1.03% 94.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10610565 1.02% 95.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 41554607 4.01% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1035339833 # Number of insts commited each cycle
system.cpu.commit.count 1528988756 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 533262345 # Number of memory references committed
system.cpu.commit.loads 384102160 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 149758588 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 41554607 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3320876555 # The number of ROB reads
system.cpu.rob.rob_writes 4762809697 # The number of ROB writes
system.cpu.timesIdled 612261 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 24142235 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
system.cpu.cpi 0.763934 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.763934 # CPI: Total CPI of All Threads
system.cpu.ipc 1.309013 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.309013 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3113980511 # number of integer regfile reads
system.cpu.int_regfile_writes 1735312737 # number of integer regfile writes
system.cpu.fp_regfile_reads 35 # number of floating regfile reads
system.cpu.misc_regfile_reads 1026187894 # number of misc regfile reads
system.cpu.icache.replacements 9719 # number of replacements
system.cpu.icache.tagsinuse 962.212052 # Cycle average of tags in use
system.cpu.icache.total_refs 188218304 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 11170 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 16850.340555 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 962.212052 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.469830 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 188225426 # number of ReadReq hits
system.cpu.icache.demand_hits 188225426 # number of demand (read+write) hits
system.cpu.icache.overall_hits 188225426 # number of overall hits
system.cpu.icache.ReadReq_misses 255393 # number of ReadReq misses
system.cpu.icache.demand_misses 255393 # number of demand (read+write) misses
system.cpu.icache.overall_misses 255393 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 1672074500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 1672074500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 1672074500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 188480819 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 188480819 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 188480819 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.001355 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.001355 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.001355 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 6547.064720 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 6547.064720 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 6547.064720 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 6 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 1431 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1431 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1431 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 253962 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 253962 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 253962 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 874487000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 874487000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 874487000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.001347 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.001347 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.001347 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3443.377356 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 3443.377356 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 3443.377356 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2526689 # number of replacements
system.cpu.dcache.tagsinuse 4088.695138 # Cycle average of tags in use
system.cpu.dcache.total_refs 470723878 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2530785 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 185.999158 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 2167120000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4088.695138 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.998217 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 321863634 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 147543808 # number of WriteReq hits
system.cpu.dcache.demand_hits 469407442 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 469407442 # number of overall hits
system.cpu.dcache.ReadReq_misses 3006802 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1616393 # number of WriteReq misses
system.cpu.dcache.demand_misses 4623195 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 4623195 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 47968938500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 38293464500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 86262403000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 86262403000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 324870436 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 474030637 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 474030637 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.009255 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.010837 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.009753 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.009753 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 15953.474323 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 23690.689393 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 18658.612280 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 18658.612280 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 2229828 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 1247246 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 605486 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1852732 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1852732 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1759556 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1010907 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 2770463 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 2770463 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 14841103500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 18213023500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 33054127000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 33054127000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005416 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006777 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.005844 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.005844 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8434.572983 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18016.517345 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11930.903607 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11930.903607 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 574908 # number of replacements
system.cpu.l2cache.tagsinuse 21475.483997 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3187378 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 594034 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 5.365649 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 306954721000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 7759.424179 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13716.059817 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.236799 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.418581 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 1427745 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 2229834 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 1220 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 528395 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 1956140 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 1956140 # number of overall hits
system.cpu.l2cache.ReadReq_misses 338148 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 241457 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 247534 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 585682 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 585682 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 11551208500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 10591500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 8481401000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 20032609500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 20032609500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 1765893 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 2229834 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 242677 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 775929 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 2541822 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 2541822 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.191488 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.994973 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.319016 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.230418 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.230418 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34160.215349 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency 43.864953 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34263.579953 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34203.901605 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34203.901605 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 412029 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 338148 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 241457 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 247534 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 585682 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 585682 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 10484352000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7486160000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7674186000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 18158538000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 18158538000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191488 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994973 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.319016 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.230418 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.230418 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.216651 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31004.112533 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31002.553185 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.090957 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.090957 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|
