blob: 72ade1ee4c3eccdd0b6c3cf77e800133a228c4a8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
|
---------- Begin Simulation Statistics ----------
host_inst_rate 139716 # Simulator instruction rate (inst/s)
host_mem_usage 230084 # Number of bytes of host memory used
host_seconds 2498.39 # Real time elapsed on the host
host_tick_rate 60715238 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 349065980 # Number of instructions simulated
sim_seconds 0.151691 # Number of seconds simulated
sim_ticks 151690547000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 20064052 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 26320164 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 70860 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 3397653 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 19939350 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 36470167 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 7288898 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 30506634 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 7586748 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 297315049 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.174063 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.830157 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 153879250 51.76% 51.76% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 68550967 23.06% 74.81% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 27297315 9.18% 83.99% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 16153153 5.43% 89.43% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 11239863 3.78% 93.21% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 6593648 2.22% 95.43% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 3258875 1.10% 96.52% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 2755230 0.93% 97.45% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 7586748 2.55% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 297315049 # Number of insts commited each cycle
system.cpu.commit.COM:count 349066592 # Number of instructions committed
system.cpu.commit.COM:fp_insts 114216705 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 6225112 # Number of function calls committed.
system.cpu.commit.COM:int_insts 287529371 # Number of committed integer instructions.
system.cpu.commit.COM:loads 94648996 # Number of loads committed
system.cpu.commit.COM:membars 11033 # Number of memory barriers committed
system.cpu.commit.COM:refs 177024837 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 3383925 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 349066592 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 3555475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 29789757 # The number of squashed insts skipped by commit
system.cpu.committedInsts 349065980 # Number of Instructions Simulated
system.cpu.committedInsts_total 349065980 # Number of Instructions Simulated
system.cpu.cpi 0.869122 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.869122 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 11409 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_hits 11407 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate 0.000175 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.ReadReq_accesses 95593398 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 33910.477454 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30796.467863 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 95590382 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 102274000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000032 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 3016 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 1289 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 53185500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1727 # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses 11146 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits 11146 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses 82052672 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 32102.269728 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35439.570120 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 82033727 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 608177500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000231 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 18945 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 16107 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 100577500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 2838 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 26227.272727 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 38940.524331 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 288500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 177646070 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 32350.598789 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 33683.023001 # average overall mshr miss latency
system.cpu.dcache.demand_hits 177624109 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 710451500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000124 # miss rate for demand accesses
system.cpu.dcache.demand_misses 21961 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 17396 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 153763000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 4565 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.753135 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3084.839186 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 177646070 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 32350.598789 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 33683.023001 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 177624109 # number of overall hits
system.cpu.dcache.overall_miss_latency 710451500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000124 # miss rate for overall accesses
system.cpu.dcache.overall_misses 21961 # number of overall misses
system.cpu.dcache.overall_mshr_hits 17396 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 153763000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 4565 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1402 # number of replacements
system.cpu.dcache.sampled_refs 4562 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3084.839186 # Cycle average of tags in use
system.cpu.dcache.total_refs 177646672 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1023 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 139700611 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 71034 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 7228761 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 408720937 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 85085390 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 69907941 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 5944542 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 201754 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 2621106 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.fetch.Branches 36470167 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 38697287 # Number of cache lines fetched
system.cpu.fetch.Cycles 74568068 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 438780 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 318859916 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 20920 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 3516150 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.120212 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 38697287 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 27352950 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.051021 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 303259590 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.373282 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.757488 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 229247017 75.59% 75.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 9043835 2.98% 78.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 5596121 1.85% 80.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 6435084 2.12% 82.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 5316543 1.75% 84.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4702041 1.55% 85.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 3588760 1.18% 87.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 4030820 1.33% 88.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 35299369 11.64% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 303259590 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 185391890 # number of floating regfile reads
system.cpu.fp_regfile_writes 131539425 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 38697287 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 11752.678794 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8359.038302 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 38681235 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 188654000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000415 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 16052 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 413 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 130727000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000404 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 15639 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 2473.857316 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 38697287 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 11752.678794 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 8359.038302 # average overall mshr miss latency
system.cpu.icache.demand_hits 38681235 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 188654000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000415 # miss rate for demand accesses
system.cpu.icache.demand_misses 16052 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 413 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 130727000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000404 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 15639 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.893029 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1828.923459 # Average occupied blocks per context
system.cpu.icache.overall_accesses 38697287 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 11752.678794 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 8359.038302 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 38681235 # number of overall hits
system.cpu.icache.overall_miss_latency 188654000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000415 # miss rate for overall accesses
system.cpu.icache.overall_misses 16052 # number of overall misses
system.cpu.icache.overall_mshr_hits 413 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 130727000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000404 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 15639 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 13772 # number of replacements
system.cpu.icache.sampled_refs 15636 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1828.923459 # Cycle average of tags in use
system.cpu.icache.total_refs 38681233 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 121505 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 31578601 # Number of branches executed
system.cpu.iew.EXEC:nop 55958 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.199464 # Inst execution rate
system.cpu.iew.EXEC:refs 183601400 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 84386759 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 302383263 # num instructions consuming a value
system.cpu.iew.WB:count 361678841 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.513536 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 155284641 # num instructions producing a value
system.cpu.iew.WB:rate 1.192160 # insts written-back per cycle
system.cpu.iew.WB:sent 362172156 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 3565736 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 6223 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 104097603 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 3634765 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 5762936 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 89132401 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 378858680 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 99214641 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3439356 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 363894705 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 99 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 34 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 5944542 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 242 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 169 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 3534064 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 41128 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 165865 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 275 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 9448606 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 6756560 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 165865 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 371765 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3193971 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 845234199 # number of integer regfile reads
system.cpu.int_regfile_writes 184410543 # number of integer regfile writes
system.cpu.ipc 1.150586 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.150586 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 125195241 34.08% 34.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 2147341 0.58% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 3 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 1 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 34.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 6684288 1.82% 36.49% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 36.49% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 8300579 2.26% 38.75% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 3402180 0.93% 39.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1567163 0.43% 40.10% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 20208124 5.50% 45.60% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 7197502 1.96% 47.56% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 7077300 1.93% 49.49% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 175286 0.05% 49.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 100094621 27.25% 76.78% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 85284432 23.22% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 367334061 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 12197832 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.033206 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 5508 0.05% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 5040 0.04% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 66 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 1308 0.01% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 3 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 233645 1.92% 2.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 627 0.01% 2.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 321940 2.64% 4.66% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.66% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 7433926 60.94% 65.60% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 4195769 34.40% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 303259590 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.211286 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.642583 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 151189237 49.85% 49.85% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 63508236 20.94% 70.80% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 27984122 9.23% 80.02% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 21601335 7.12% 87.15% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 21428973 7.07% 94.21% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 10561255 3.48% 97.70% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 4840954 1.60% 99.29% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 1678139 0.55% 99.85% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 467339 0.15% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 303259590 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.210801 # Inst issue rate
system.cpu.iq.fp_alu_accesses 125152178 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 243612430 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 116468066 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 124271782 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 254379715 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 807715135 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 245210775 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 282420664 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 375156709 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 367334061 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 3646013 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 27828461 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1202021 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 90538 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 56356812 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 2835 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34417.287895 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31254.348598 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 18 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 96953500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.993651 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 2817 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 88043500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993651 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 2817 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 17363 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34335.562731 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31152.310924 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 13027 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 148879000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.249726 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 4336 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency 133456500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.246732 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 4284 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 3 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 93000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 3 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 1023 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 1023 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.520377 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 20198 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34367.747798 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31192.789748 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 13045 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 245832500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.354144 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7153 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 52 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 221500000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.351569 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7101 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.103835 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.011338 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3402.462231 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 371.534678 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 20198 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34367.747798 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31192.789748 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 13045 # number of overall hits
system.cpu.l2cache.overall_miss_latency 245832500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.354144 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7153 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 52 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 221500000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.351569 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7101 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 53 # number of replacements
system.cpu.l2cache.sampled_refs 5202 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 3773.996909 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13111 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 11713930 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 25106151 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 104097603 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 89132401 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 963036910 # number of misc regfile reads
system.cpu.misc_regfile_writes 43097542 # number of misc regfile writes
system.cpu.numCycles 303381095 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 825170 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 344460462 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 48323 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 92021425 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 4815329 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 1568557063 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 396913119 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 386168908 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 66099997 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 5944542 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 17924907 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 41708443 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 797945883 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 770611180 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 120443549 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 12410013 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 58864418 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 3692672 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 668582127 # The number of ROB reads
system.cpu.rob.rob_writes 763657860 # The number of ROB writes
system.cpu.timesIdled 2620 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 191 # Number of system calls
---------- End Simulation Statistics ----------
|
