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---------- Begin Simulation Statistics ----------
host_inst_rate 1114146 # Simulator instruction rate (inst/s)
host_mem_usage 205224 # Number of bytes of host memory used
host_seconds 309.12 # Real time elapsed on the host
host_tick_rate 1701065680 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 344399678 # Number of instructions simulated
sim_seconds 0.525826 # Number of seconds simulated
sim_ticks 525825884000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 94586725 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 49727.442439 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46727.442439 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 94585118 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 79912000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1607 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 75091000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000017 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1607 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 82063572 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55766.016713 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52766.016713 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 82060700 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 160160000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000035 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 2872 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 151544000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 2872 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 39438.673365 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 176650297 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 53599.464166 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 50599.464166 # average overall mshr miss latency
system.cpu.dcache.demand_hits 176645818 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 240072000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
system.cpu.dcache.demand_misses 4479 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 226635000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 4479 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.751814 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3079.431639 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 176650297 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 53599.464166 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 50599.464166 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 176645818 # number of overall hits
system.cpu.dcache.overall_miss_latency 240072000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_misses 4479 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 226635000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 4479 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1332 # number of replacements
system.cpu.dcache.sampled_refs 4479 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3079.431639 # Cycle average of tags in use
system.cpu.dcache.total_refs 176645818 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 998 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.icache.ReadReq_accesses 348627536 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 21025.572005 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 18025.572005 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 348611933 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 328062000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000045 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 15603 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 281253000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000045 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 15603 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 22342.622124 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 348627536 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 21025.572005 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency
system.cpu.icache.demand_hits 348611933 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 328062000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000045 # miss rate for demand accesses
system.cpu.icache.demand_misses 15603 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 281253000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000045 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 15603 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.862305 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1766.001397 # Average occupied blocks per context
system.cpu.icache.overall_accesses 348627536 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 21025.572005 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 348611933 # number of overall hits
system.cpu.icache.overall_miss_latency 328062000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000045 # miss rate for overall accesses
system.cpu.icache.overall_misses 15603 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 281253000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000045 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 15603 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 13796 # number of replacements
system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1766.001397 # Cycle average of tags in use
system.cpu.icache.total_refs 348611933 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 2872 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 16 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 148512000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.994429 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 2856 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 114240000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994429 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 2856 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 17210 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 13233 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 206804000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.231087 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3977 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 159080000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231087 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3977 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 998 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 998 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.725579 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 20082 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 13249 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 355316000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.340255 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 6833 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 273320000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.340255 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 6833 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.095645 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.010426 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3134.106018 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 341.623002 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 20082 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 13249 # number of overall hits
system.cpu.l2cache.overall_miss_latency 355316000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.340255 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 6833 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 273320000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.340255 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 6833 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 48 # number of replacements
system.cpu.l2cache.sampled_refs 4883 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 3475.729020 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13309 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1051651768 # number of cpu cycles simulated
system.cpu.num_insts 344399678 # Number of instructions executed
system.cpu.num_refs 177028576 # Number of memory references
system.cpu.workload.PROG:num_syscalls 191 # Number of system calls
---------- End Simulation Statistics ----------
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