blob: bce6cbb055adbd610540323835fbe621d40aa046 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.744106 # Number of seconds simulated
sim_ticks 744105966500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 75556 # Simulator instruction rate (inst/s)
host_tick_rate 29820362 # Simulator tick rate (ticks/s)
host_mem_usage 264164 # Number of bytes of host memory used
host_seconds 24952.95 # Real time elapsed on the host
sim_insts 1885342016 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
system.cpu.numCycles 1488211934 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 518896793 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 400040732 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 32908651 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 412694566 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 290043770 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 65454853 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2848873 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 431006584 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2627710278 # Number of instructions fetch has processed
system.cpu.fetch.Branches 518896793 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 355498623 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 704801435 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 227434994 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 113516280 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 5111 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 399257672 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 8382302 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1436630001 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.536830 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.149737 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 731865766 50.94% 50.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 52278672 3.64% 54.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 109951004 7.65% 62.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 64331025 4.48% 66.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 92104513 6.41% 73.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 55434190 3.86% 76.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 39408243 2.74% 79.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 32778762 2.28% 82.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 258477826 17.99% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1436630001 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.348671 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.765683 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 474703889 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 92089695 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 671736516 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 10812998 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 187286903 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 70416009 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 13639 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3539876246 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 23440 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 187286903 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 514963010 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 29220198 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 3511276 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 640788708 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 60859906 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 3412725631 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 46 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4123400 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 48521988 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 3397910620 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 16198267301 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 15450730698 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 747536603 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993166767 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 1404743848 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 278280 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 278424 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 178635722 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 1114561414 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 545702989 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 154567236 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 147667095 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 3238356442 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 281581 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2642482384 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 5796308 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 1352960304 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3645177300 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 70016 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1436630001 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.839362 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.852230 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 506457907 35.25% 35.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 223599177 15.56% 50.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 229642094 15.98% 66.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 172448421 12.00% 78.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 157180454 10.94% 89.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 90857048 6.32% 96.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 40453427 2.82% 98.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 11405646 0.79% 99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 4585827 0.32% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1436630001 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 1185558 1.85% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 23950 0.04% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 40505203 63.35% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 22224408 34.76% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1237165385 46.82% 46.82% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 11226668 0.42% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 8630 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 47.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.26% 47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 6142371 0.23% 47.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 24460385 0.93% 48.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 896605446 33.93% 82.64% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 458621735 17.36% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2642482384 # Type of FU issued
system.cpu.iq.rate 1.775609 # Inst issue rate
system.cpu.iq.fu_busy_cnt 63939119 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.024197 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6661297580 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 4469277070 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2420670942 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 130032616 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 124010144 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 59075392 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2641405327 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 65016176 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 73114963 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 483170898 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 99011 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 3650929 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 268704359 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 94 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 187286903 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 16548451 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1477546 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 3238703739 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 11872283 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 1114561414 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 545702989 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 268887 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1475433 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 305 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 3650929 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 36090139 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 8517669 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 44607808 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2538548253 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 842723322 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 103934131 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 65716 # number of nop insts executed
system.cpu.iew.exec_refs 1272992998 # number of memory reference insts executed
system.cpu.iew.exec_branches 351489842 # Number of branches executed
system.cpu.iew.exec_stores 430269676 # Number of stores executed
system.cpu.iew.exec_rate 1.705771 # Inst execution rate
system.cpu.iew.wb_sent 2508384244 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2479746334 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1467036313 # num instructions producing a value
system.cpu.iew.wb_consumers 2710651250 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.666259 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.541212 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1885353032 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 1353312364 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 211565 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 38431023 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1249343100 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.509075 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.191779 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 548617532 43.91% 43.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 340979538 27.29% 71.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 105479188 8.44% 79.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 77201400 6.18% 85.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 51871134 4.15% 89.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 18884009 1.51% 91.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 20943022 1.68% 93.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 8690011 0.70% 93.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 76677266 6.14% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1249343100 # Number of insts commited each cycle
system.cpu.commit.count 1885353032 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 908389145 # Number of memory references committed
system.cpu.commit.loads 631390515 # Number of loads committed
system.cpu.commit.membars 9986 # Number of memory barriers committed
system.cpu.commit.branches 291351878 # Number of branches committed
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1653712207 # Number of committed integer instructions.
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
system.cpu.commit.bw_lim_events 76677266 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 4411312885 # The number of ROB reads
system.cpu.rob.rob_writes 6664635759 # The number of ROB writes
system.cpu.timesIdled 1344981 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 51581933 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1885342016 # Number of Instructions Simulated
system.cpu.committedInsts_total 1885342016 # Number of Instructions Simulated
system.cpu.cpi 0.789359 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.789359 # CPI: Total CPI of All Threads
system.cpu.ipc 1.266850 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.266850 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 12578509945 # number of integer regfile reads
system.cpu.int_regfile_writes 2395231974 # number of integer regfile writes
system.cpu.fp_regfile_reads 70809202 # number of floating regfile reads
system.cpu.fp_regfile_writes 51453484 # number of floating regfile writes
system.cpu.misc_regfile_reads 4059454744 # number of misc regfile reads
system.cpu.misc_regfile_writes 13779568 # number of misc regfile writes
system.cpu.icache.replacements 25817 # number of replacements
system.cpu.icache.tagsinuse 1640.813432 # Cycle average of tags in use
system.cpu.icache.total_refs 399229379 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 27501 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 14516.904076 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1640.813432 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.801178 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 399229380 # number of ReadReq hits
system.cpu.icache.demand_hits 399229380 # number of demand (read+write) hits
system.cpu.icache.overall_hits 399229380 # number of overall hits
system.cpu.icache.ReadReq_misses 28292 # number of ReadReq misses
system.cpu.icache.demand_misses 28292 # number of demand (read+write) misses
system.cpu.icache.overall_misses 28292 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 269405500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 269405500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 269405500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 399257672 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 399257672 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 399257672 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000071 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000071 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000071 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 9522.320797 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 9522.320797 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 9522.320797 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 785 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 785 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 785 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 27507 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 27507 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 27507 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 166096000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 166096000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 166096000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000069 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000069 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000069 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6038.317519 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 6038.317519 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 6038.317519 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1531025 # number of replacements
system.cpu.dcache.tagsinuse 4094.846671 # Cycle average of tags in use
system.cpu.dcache.total_refs 1028461825 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1535121 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 669.954893 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 306448000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4094.846671 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999718 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 752304344 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 276127089 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 17060 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 13318 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 1028431433 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 1028431433 # number of overall hits
system.cpu.dcache.ReadReq_misses 1932486 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 808589 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 2741075 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2741075 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 69636872500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 28315241500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 97952114000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 97952114000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 754236830 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 17063 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 13318 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 1031172508 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 1031172508 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.002562 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.002920 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000176 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.002658 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.002658 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 36034.865194 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 35018.088918 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 35734.926626 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 35734.926626 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 59000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 14750 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 106614 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 470081 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 735866 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1205947 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1205947 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1462405 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 72723 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1535128 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1535128 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 50067282500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2361289000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 52428571500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 52428571500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001939 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.001489 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.001489 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34236.263210 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32469.631341 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34152.573271 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34152.573271 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1479866 # number of replacements
system.cpu.l2cache.tagsinuse 31973.633477 # Cycle average of tags in use
system.cpu.l2cache.total_refs 82869 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1512586 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.054786 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 29008.320334 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 2965.313143 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.885264 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.090494 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 74752 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 106614 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 6636 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 81388 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 81388 # number of overall hits
system.cpu.l2cache.ReadReq_misses 1415154 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 66081 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 1481235 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 1481235 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 48603615500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2279719000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 50883334500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 50883334500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 1489906 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 106614 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 6 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 72717 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 1562623 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 1562623 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.949828 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.666667 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.908742 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.947916 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.947916 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34345.106964 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.857463 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34351.966096 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34351.966096 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 66099 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 27 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 1415127 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 66081 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 1481208 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 1481208 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 44021028500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048574500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 46069603000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 46069603000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.949810 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.666667 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908742 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.947899 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.947899 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31107.475513 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.960942 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.723588 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.723588 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|
