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---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 7411086 # Number of BTB hits
global.BPredUnit.BTBLookups 13158968 # Number of BTB lookups
global.BPredUnit.RASInCorrect 32147 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 450892 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 9746581 # Number of conditional branches predicted
global.BPredUnit.lookups 14988034 # Number of BP lookups
global.BPredUnit.usedRAS 1776543 # Number of times the RAS was used to get a target.
host_inst_rate 99683 # Simulator instruction rate (inst/s)
host_mem_usage 159476 # Number of bytes of host memory used
host_seconds 798.45 # Real time elapsed on the host
host_tick_rate 35303213 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 9747985 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 9298064 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 21418262 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 15459606 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.028188 # Number of seconds simulated
sim_ticks 28187684500 # Number of ticks simulated
system.cpu.commit.COM:branches 13754477 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 3230574 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 55590975
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 26501535 4767.24%
1 10970497 1973.43%
2 5466463 983.34%
3 3506601 630.79%
4 2372940 426.86%
5 1558557 280.36%
6 1098347 197.58%
7 885461 159.28%
8 3230574 581.13%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:count 88340672 # Number of instructions committed
system.cpu.commit.COM:loads 20379399 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 355366 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 4551161 # The number of squashed insts skipped by commit
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
system.cpu.cpi 0.708309 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.708309 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 20049834 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 4729.134904 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3349.390829 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 19907503 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 673102500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.007099 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 142331 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 80854 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 205910500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003066 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61477 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 3029.723364 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4119.889460 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 14053363 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1696687500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.038322 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 560014 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 416536 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 591113500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 143478 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 165.699134 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34663211 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3374.111014 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3888.775585 # average overall mshr miss latency
system.cpu.dcache.demand_hits 33960866 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2369790000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.020262 # miss rate for demand accesses
system.cpu.dcache.demand_misses 702345 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 497390 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 797024000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005913 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 204955 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 34663211 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3374.111014 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3888.775585 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 33960866 # number of overall hits
system.cpu.dcache.overall_miss_latency 2369790000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.020262 # miss rate for overall accesses
system.cpu.dcache.overall_misses 702345 # number of overall misses
system.cpu.dcache.overall_mshr_hits 497390 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 797024000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005913 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 204955 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 200859 # number of replacements
system.cpu.dcache.sampled_refs 204955 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4080.110580 # Cycle average of tags in use
system.cpu.dcache.total_refs 33960866 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 144827000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147753 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 583473 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 97307 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3380270 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 95203508 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 37386702 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 17614461 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 784542 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 292514 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 6340 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 14988034 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 12416477 # Number of cache lines fetched
system.cpu.fetch.Cycles 30119953 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 260035 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 96279919 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 467393 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.265861 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 12416477 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 9187629 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.707832 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 56375518
system.cpu.fetch.rateDist.min_value 0
0 38672046 6859.72%
1 1321940 234.49%
2 1201428 213.11%
3 1338454 237.42%
4 3789980 672.27%
5 1624217 288.11%
6 592859 105.16%
7 975150 172.97%
8 6859444 1216.74%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 12416477 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3477.694454 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2488.876340 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 12330467 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 299116500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.006927 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 86010 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1011 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 211552000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.006846 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 84999 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 145.066024 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 12416477 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3477.694454 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2488.876340 # average overall mshr miss latency
system.cpu.icache.demand_hits 12330467 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 299116500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.006927 # miss rate for demand accesses
system.cpu.icache.demand_misses 86010 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1011 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 211552000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.006846 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 84999 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 12416477 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3477.694454 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2488.876340 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 12330467 # number of overall hits
system.cpu.icache.overall_miss_latency 299116500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.006927 # miss rate for overall accesses
system.cpu.icache.overall_misses 86010 # number of overall misses
system.cpu.icache.overall_mshr_hits 1011 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 211552000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.006846 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 84999 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 82951 # number of replacements
system.cpu.icache.sampled_refs 84999 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1918.432617 # Cycle average of tags in use
system.cpu.icache.total_refs 12330467 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 24669337000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 25301 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 14196900 # Number of branches executed
system.cpu.iew.EXEC:nop 9006488 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.455602 # Inst execution rate
system.cpu.iew.EXEC:refs 36045074 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 15052480 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 39431808 # num instructions consuming a value
system.cpu.iew.WB:count 81784655 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.769564 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 30345313 # num instructions producing a value
system.cpu.iew.WB:rate 1.450712 # insts written-back per cycle
system.cpu.iew.WB:sent 81828309 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 387091 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 10156 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 21418262 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 4652 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 597409 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 15459606 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 92891480 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 20992594 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 333391 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 82060341 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 141 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 37 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 784542 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 478 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 828061 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 554 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 19340 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1425 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 1038863 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 614987 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 19340 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 103732 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 283359 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.411814 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.411814 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 82393732 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 0 0.00% # Type of FU issued
IntAlu 45892607 55.70% # Type of FU issued
IntMult 44107 0.05% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 116900 0.14% # Type of FU issued
FloatCmp 87 0.00% # Type of FU issued
FloatCvt 120453 0.15% # Type of FU issued
FloatMult 50 0.00% # Type of FU issued
FloatDiv 37768 0.05% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 21065064 25.57% # Type of FU issued
MemWrite 15116696 18.35% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 898002 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.010899 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
IntAlu 168043 18.71% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available
FloatCvt 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 309725 34.49% # attempts to use FU when none available
MemWrite 420234 46.80% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 56375518
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 22612550 4011.06%
1 13769796 2442.51%
2 7834961 1389.78%
3 4029672 714.79%
4 3712649 658.56%
5 1993297 353.57%
6 1449259 257.07%
7 434309 77.04%
8 539025 95.61%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.461516 # Inst issue rate
system.cpu.iq.iqInstsAdded 83880340 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 82393732 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 4652 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 4104955 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 35761 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 69 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 2730801 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 289883 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4226.385671 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2218.670959 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 120272 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 716841500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.585102 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 169611 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 376311000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.585102 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 169611 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 147753 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 147292 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 0.003120 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 461 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 0.003120 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 461 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 1.577516 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 289883 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4226.385671 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2218.670959 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 120272 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 716841500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.585102 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 169611 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 376311000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.585102 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 169611 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 437636 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4214.929559 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2218.670959 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 267564 # number of overall hits
system.cpu.l2cache.overall_miss_latency 716841500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.388615 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 170072 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 376311000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.387562 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 169611 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 136843 # number of replacements
system.cpu.l2cache.sampled_refs 169611 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 32058.525051 # Cycle average of tags in use
system.cpu.l2cache.total_refs 267564 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 13792867000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 115936 # number of writebacks
system.cpu.numCycles 56375518 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 238131 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 31030 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 37626801 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 240022 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 113729051 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 94390828 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 56605918 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 17378620 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 784542 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 281505 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 4059037 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 65919 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 4656 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 641192 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 4654 # count of temporary serializing insts renamed
system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------
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