blob: 91b29d8d93484fea2de286ec972f7f13dd92fc31 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
|
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 7744324 # Number of BTB hits
global.BPredUnit.BTBLookups 13591046 # Number of BTB lookups
global.BPredUnit.RASInCorrect 32932 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 452723 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 10077718 # Number of conditional branches predicted
global.BPredUnit.lookups 15489897 # Number of BP lookups
global.BPredUnit.usedRAS 1844517 # Number of times the RAS was used to get a target.
host_inst_rate 108228 # Simulator instruction rate (inst/s)
host_mem_usage 159488 # Number of bytes of host memory used
host_seconds 735.41 # Real time elapsed on the host
host_tick_rate 23792996 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 12942665 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 11520420 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 21780362 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 15866784 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.017498 # Number of seconds simulated
sim_ticks 17497602000 # Number of ticks simulated
system.cpu.commit.COM:branches 13754477 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 4260073 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 33996100
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 8358440 2458.65%
1 8230566 2421.03%
2 4712162 1386.09%
3 3108634 914.41%
4 2121957 624.18%
5 1131901 332.95%
6 1374606 404.34%
7 697761 205.25%
8 4260073 1253.11%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:count 88340672 # Number of instructions committed
system.cpu.commit.COM:loads 20379399 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 356682 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 6565781 # The number of squashed insts skipped by commit
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
system.cpu.cpi 0.439684 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.439684 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 19603173 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 4020.633151 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2686.323277 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 19458721 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 580788500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.007369 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 144452 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 82734 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 165794500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003148 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61718 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 2642.114676 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3379.334983 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 13777457 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2208596500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.057202 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 835920 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 692465 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 484782500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009817 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 143455 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 161.990993 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34216550 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 2845.231198 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3170.870436 # average overall mshr miss latency
system.cpu.dcache.demand_hits 33236178 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2789385000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.028652 # miss rate for demand accesses
system.cpu.dcache.demand_misses 980372 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 775199 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 650577000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005996 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 205173 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 34216550 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 2845.231198 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3170.870436 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 33236178 # number of overall hits
system.cpu.dcache.overall_miss_latency 2789385000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.028652 # miss rate for overall accesses
system.cpu.dcache.overall_misses 980372 # number of overall misses
system.cpu.dcache.overall_mshr_hits 775199 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 650577000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005996 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 205173 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 201077 # number of replacements
system.cpu.dcache.sampled_refs 205173 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4079.993551 # Cycle average of tags in use
system.cpu.dcache.total_refs 33236178 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 90338000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147781 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 1516721 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 98391 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3463978 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 98144908 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 14320248 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 17547399 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 999107 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 287801 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 611733 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 15489897 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 12778073 # Number of cache lines fetched
system.cpu.fetch.Cycles 31147667 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 14471 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 99913909 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 465674 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.442629 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 12778073 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 9588841 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.855074 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 34995208
system.cpu.fetch.rateDist.min_value 0
0 16625619 4750.83%
1 1365816 390.29%
2 1258616 359.65%
3 1410956 403.19%
4 3900976 1114.72%
5 1678758 479.71%
6 612174 174.93%
7 1011089 288.92%
8 7131204 2037.77%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 12778073 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 2888.242687 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1894.538715 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 12690553 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 252779000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.006849 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 87520 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 654 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 164571000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.006798 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 86866 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 146.093443 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 12778073 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 2888.242687 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 1894.538715 # average overall mshr miss latency
system.cpu.icache.demand_hits 12690553 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 252779000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.006849 # miss rate for demand accesses
system.cpu.icache.demand_misses 87520 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 654 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 164571000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.006798 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 86866 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 12778073 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 2888.242687 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 1894.538715 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 12690553 # number of overall hits
system.cpu.icache.overall_miss_latency 252779000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.006849 # miss rate for overall accesses
system.cpu.icache.overall_misses 87520 # number of overall misses
system.cpu.icache.overall_mshr_hits 654 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 164571000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.006798 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 86866 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 84818 # number of replacements
system.cpu.icache.sampled_refs 86866 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1921.828467 # Cycle average of tags in use
system.cpu.icache.total_refs 12690553 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 15230287000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 6484 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 14304724 # Number of branches executed
system.cpu.iew.EXEC:nop 9152219 # number of nop insts executed
system.cpu.iew.EXEC:rate 2.363053 # Inst execution rate
system.cpu.iew.EXEC:refs 36160680 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 15116998 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 43283574 # num instructions consuming a value
system.cpu.iew.WB:count 82548148 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.757836 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 32801872 # num instructions producing a value
system.cpu.iew.WB:rate 2.358841 # insts written-back per cycle
system.cpu.iew.WB:sent 82621578 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 398195 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 20355 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 21780362 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 4681 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 352010 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 15866784 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 94903979 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 21043682 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 752566 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 82695525 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 5889 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 132 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 999107 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 7135 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 1325562 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 2239 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 16849 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1491 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 1400963 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 1022165 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 16849 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 105190 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 293005 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 2.274362 # IPC: Instructions Per Cycle
system.cpu.ipc_total 2.274362 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 83448091 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 0 0.00% # Type of FU issued
IntAlu 46687810 55.95% # Type of FU issued
IntMult 45238 0.05% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 120004 0.14% # Type of FU issued
FloatCmp 87 0.00% # Type of FU issued
FloatCvt 122290 0.15% # Type of FU issued
FloatMult 50 0.00% # Type of FU issued
FloatDiv 37770 0.05% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 21206489 25.41% # Type of FU issued
MemWrite 15228353 18.25% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 1422206 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.017043 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
IntAlu 169452 11.91% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available
FloatCvt 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 649726 45.68% # attempts to use FU when none available
MemWrite 603028 42.40% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 34995208
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 5876071 1679.11%
1 8518834 2434.29%
2 6419045 1834.26%
3 4436708 1267.80%
4 4423684 1264.08%
5 2554091 729.84%
6 1512126 432.10%
7 794096 226.92%
8 460553 131.60%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 2.384558 # Inst issue rate
system.cpu.iq.iqInstsAdded 85747079 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 83448091 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 4681 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 5951026 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 23998 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 98 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 4012087 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 291992 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 3325.548649 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1922.235296 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 122257 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 564462000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.581300 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 169735 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 326270608 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.581300 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 169735 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 147781 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 147317 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 1.588205 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 291992 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 3325.548649 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1922.235296 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 122257 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 564462000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.581300 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 169735 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 326270608 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.581300 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 169735 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 439773 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 3316.482471 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1922.235296 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 269574 # number of overall hits
system.cpu.l2cache.overall_miss_latency 564462000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.387016 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 170199 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 326270608 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.385960 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 169735 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 136967 # number of replacements
system.cpu.l2cache.sampled_refs 169735 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 32064.700481 # Cycle average of tags in use
system.cpu.l2cache.total_refs 269574 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 8508988000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 115938 # number of writebacks
system.cpu.numCycles 34995208 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 201241 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 31178 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 14721876 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1110145 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 117085470 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 96973574 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 58152082 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 17754494 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 999107 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 1242602 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 5605201 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 75888 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 4701 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 2792735 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 4699 # count of temporary serializing insts renamed
system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------
|