blob: 8d53ad02b9843f3d8397dfc7e59b033f0eff8bcf (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
|
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 8038204 # Number of BTB hits
global.BPredUnit.BTBLookups 14256935 # Number of BTB lookups
global.BPredUnit.RASInCorrect 35926 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 456185 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 10553314 # Number of conditional branches predicted
global.BPredUnit.lookups 16248074 # Number of BP lookups
global.BPredUnit.usedRAS 1941559 # Number of times the RAS was used to get a target.
host_inst_rate 107979 # Simulator instruction rate (inst/s)
host_mem_usage 171824 # Number of bytes of host memory used
host_seconds 737.10 # Real time elapsed on the host
host_tick_rate 33795098 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 12328057 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 11324911 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 22967030 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 16293172 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.024910 # Number of seconds simulated
sim_ticks 24910446000 # Number of ticks simulated
system.cpu.commit.COM:branches 13754477 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 3431451 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 48556236
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 19632028 4043.15%
1 11130407 2292.27%
2 5090838 1048.44%
3 3451952 710.92%
4 2493473 513.52%
5 1522245 313.50%
6 990886 204.07%
7 812956 167.43%
8 3431451 706.70%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:count 88340672 # Number of instructions committed
system.cpu.commit.COM:loads 20379399 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 360457 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 8047613 # The number of squashed insts skipped by commit
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
system.cpu.cpi 0.625955 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.625955 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 20358815 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14848.430668 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3932.171708 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20297292 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 913520000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.003022 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 61523 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 82415 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 241919000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61523 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 13806620 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 30619.646254 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5319.309194 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 13656795 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 4587588500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010852 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 149825 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 806757 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 796965500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010852 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 149825 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 165.649492 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34165435 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 26028.675455 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 4915.516116 # average overall mshr miss latency
system.cpu.dcache.demand_hits 33954087 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 5501108500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.006186 # miss rate for demand accesses
system.cpu.dcache.demand_misses 211348 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 889172 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1038884500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.006186 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 211348 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 34165435 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 26028.675455 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 4915.516116 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 33954087 # number of overall hits
system.cpu.dcache.overall_miss_latency 5501108500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.006186 # miss rate for overall accesses
system.cpu.dcache.overall_misses 211348 # number of overall misses
system.cpu.dcache.overall_mshr_hits 889172 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1038884500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.006186 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 211348 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 200918 # number of replacements
system.cpu.dcache.sampled_refs 205014 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4080.935098 # Cycle average of tags in use
system.cpu.dcache.total_refs 33960465 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 120644000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147759 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 965138 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 96643 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3649464 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 101643368 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 27939518 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 19626008 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 1262570 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 284543 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 25573 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 36605590 # DTB accesses
system.cpu.dtb.acv 38 # DTB access violations
system.cpu.dtb.hits 36432080 # DTB hits
system.cpu.dtb.misses 173510 # DTB misses
system.cpu.dtb.read_accesses 21546917 # DTB read accesses
system.cpu.dtb.read_acv 36 # DTB read access violations
system.cpu.dtb.read_hits 21390081 # DTB read hits
system.cpu.dtb.read_misses 156836 # DTB read misses
system.cpu.dtb.write_accesses 15058673 # DTB write accesses
system.cpu.dtb.write_acv 2 # DTB write access violations
system.cpu.dtb.write_hits 15041999 # DTB write hits
system.cpu.dtb.write_misses 16674 # DTB write misses
system.cpu.fetch.Branches 16248074 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 13374991 # Number of cache lines fetched
system.cpu.fetch.Cycles 33229665 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 154532 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 103238390 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 573003 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.326130 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 13374991 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 9979763 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.072191 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 49818807
system.cpu.fetch.rateDist.min_value 0
0 29989736 6019.76%
1 1895135 380.41%
2 1526458 306.40%
3 1823774 366.08%
4 3936760 790.22%
5 1866062 374.57%
6 698148 140.14%
7 1109093 222.63%
8 6973641 1399.80%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 13374115 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 4650.026870 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2608.921937 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 13288517 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 398033000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.006400 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 85598 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 876 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 223318500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.006400 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 85598 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 155.243312 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 13374115 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 4650.026870 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2608.921937 # average overall mshr miss latency
system.cpu.icache.demand_hits 13288517 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 398033000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.006400 # miss rate for demand accesses
system.cpu.icache.demand_misses 85598 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 876 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 223318500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.006400 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 85598 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 13374115 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 4650.026870 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2608.921937 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 13288517 # number of overall hits
system.cpu.icache.overall_miss_latency 398033000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.006400 # miss rate for overall accesses
system.cpu.icache.overall_misses 85598 # number of overall misses
system.cpu.icache.overall_mshr_hits 876 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 223318500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.006400 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 85598 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 83550 # number of replacements
system.cpu.icache.sampled_refs 85598 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1922.621732 # Cycle average of tags in use
system.cpu.icache.total_refs 13288517 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 21667252000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 2086 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 14743916 # Number of branches executed
system.cpu.iew.EXEC:nop 9378551 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.702006 # Inst execution rate
system.cpu.iew.EXEC:refs 36947583 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 15291466 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 42399540 # num instructions consuming a value
system.cpu.iew.WB:count 84317145 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.765160 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 32442413 # num instructions producing a value
system.cpu.iew.WB:rate 1.692405 # insts written-back per cycle
system.cpu.iew.WB:sent 84551587 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 401023 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 18086 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 22967030 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 4976 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 358113 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 16293172 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 98809667 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 21656117 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 536500 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 84795443 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 1943 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 166 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 1262570 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 2513 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 947497 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 960 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 18554 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1310 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 2587631 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 1448553 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 18554 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 108095 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 292928 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.597558 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.597558 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 85331943 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 0 0.00% # Type of FU issued
IntAlu 47873863 56.10% # Type of FU issued
IntMult 42967 0.05% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 121266 0.14% # Type of FU issued
FloatCmp 86 0.00% # Type of FU issued
FloatCvt 121911 0.14% # Type of FU issued
FloatMult 50 0.00% # Type of FU issued
FloatDiv 38525 0.05% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 21762707 25.50% # Type of FU issued
MemWrite 15370568 18.01% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 973739 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011411 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 95466 9.80% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available
FloatCvt 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 447999 46.01% # attempts to use FU when none available
MemWrite 430274 44.19% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 49818807
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 14814928 2973.76%
1 13524369 2714.71%
2 8025078 1610.85%
3 4803693 964.23%
4 4680291 939.46%
5 2123644 426.27%
6 1156346 232.11%
7 454785 91.29%
8 235673 47.31%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.712774 # Inst issue rate
system.cpu.iq.iqInstsAdded 89426140 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 85331943 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 4976 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 9626821 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 45871 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 393 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 6618385 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 13400594 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 13374991 # ITB hits
system.cpu.itb.misses 25603 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 143491 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4105.274895 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2105.274895 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 589070000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 143491 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 302088000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 143491 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 147121 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4130.611741 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2130.611741 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 102527 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 184200500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.303111 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 44594 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 95012500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.303111 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 44594 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 6346 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4217.538607 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2242.593760 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 26764500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 6346 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14231500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 6346 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 147759 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 147759 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.676534 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 290612 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4111.282133 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2111.282133 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 102527 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 773270500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.647203 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 188085 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 397100500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.647203 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 188085 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 290612 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4111.282133 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2111.282133 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 102527 # number of overall hits
system.cpu.l2cache.overall_miss_latency 773270500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.647203 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 188085 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 397100500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.647203 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 188085 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 148798 # number of replacements
system.cpu.l2cache.sampled_refs 174015 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 18438.001925 # Cycle average of tags in use
system.cpu.l2cache.total_refs 117727 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 120645 # number of writebacks
system.cpu.numCycles 49820893 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 263970 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 36282 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 28255906 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 551452 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 121470810 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 100830627 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 60670426 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 19329077 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 1262570 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 631100 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 8123545 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 76184 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 5248 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 1415098 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 5246 # count of temporary serializing insts renamed
system.cpu.timesIdled 786 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------
|
