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---------- Begin Simulation Statistics ----------
host_inst_rate 111480 # Simulator instruction rate (inst/s)
host_mem_usage 216720 # Number of bytes of host memory used
host_seconds 713.95 # Real time elapsed on the host
host_tick_rate 37970836 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.027109 # Number of seconds simulated
sim_ticks 27109454000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 8023938 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 14145639 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 34256 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 455419 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 10571328 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 16274912 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1940184 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 13754477 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 3318027 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 51708884 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.708423 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.329205 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 22519798 43.55% 43.55% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 11308699 21.87% 65.42% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 5100268 9.86% 75.28% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 3555628 6.88% 82.16% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 2564108 4.96% 87.12% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 1506181 2.91% 90.03% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 1020225 1.97% 92.01% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 815950 1.58% 93.58% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 3318027 6.42% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 51708884 # Number of insts commited each cycle
system.cpu.commit.COM:count 88340672 # Number of instructions committed
system.cpu.commit.COM:loads 20379399 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 360224 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 8384811 # The number of squashed insts skipped by commit
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
system.cpu.cpi 0.681213 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.681213 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 20456575 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 30286.204567 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20855.715214 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20307098 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4527091000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.007307 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 149477 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 87887 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1284503500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003011 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61590 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 32227.418613 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35731.214318 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 13566176 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 33748584999 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.071660 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1047201 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 900041 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 5258205499 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010070 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 147160 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 165.209324 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 35069952 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 31984.941646 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 31342.318558 # average overall mshr miss latency
system.cpu.dcache.demand_hits 33873274 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 38275675999 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.034123 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1196678 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 987928 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 6542708999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005952 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 208750 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.995492 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4077.536069 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 35069952 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 31984.941646 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 31342.318558 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 33873274 # number of overall hits
system.cpu.dcache.overall_miss_latency 38275675999 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.034123 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1196678 # number of overall misses
system.cpu.dcache.overall_mshr_hits 987928 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 6542708999 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005952 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 208750 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 200988 # number of replacements
system.cpu.dcache.sampled_refs 205084 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4077.536069 # Cycle average of tags in use
system.cpu.dcache.total_refs 33881789 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 181403000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 149251 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 3489554 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 96109 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3659886 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 101890177 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 28536030 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 19538571 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 1305079 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 281240 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 144729 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 36643462 # DTB accesses
system.cpu.dtb.data_acv 34 # DTB access violations
system.cpu.dtb.data_hits 36467174 # DTB hits
system.cpu.dtb.data_misses 176288 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 21569273 # DTB read accesses
system.cpu.dtb.read_acv 32 # DTB read access violations
system.cpu.dtb.read_hits 21411172 # DTB read hits
system.cpu.dtb.read_misses 158101 # DTB read misses
system.cpu.dtb.write_accesses 15074189 # DTB write accesses
system.cpu.dtb.write_acv 2 # DTB write access violations
system.cpu.dtb.write_hits 15056002 # DTB write hits
system.cpu.dtb.write_misses 18187 # DTB write misses
system.cpu.fetch.Branches 16274912 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 13386326 # Number of cache lines fetched
system.cpu.fetch.Cycles 33268098 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 152194 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 103463438 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 573170 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.300170 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 13386326 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 9964122 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.908254 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 53013963 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.951626 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.945013 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 33159204 62.55% 62.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1896528 3.58% 66.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1503537 2.84% 68.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1853022 3.50% 72.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 3942692 7.44% 79.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1853723 3.50% 83.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 688430 1.30% 84.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1103809 2.08% 86.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 7013018 13.23% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 53013963 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 13386326 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 9552.485505 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6054.988859 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 13297330 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 850133000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.006648 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 88996 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 2824 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 521770500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.006437 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 86172 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 154.313284 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 13386326 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 9552.485505 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 6054.988859 # average overall mshr miss latency
system.cpu.icache.demand_hits 13297330 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 850133000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.006648 # miss rate for demand accesses
system.cpu.icache.demand_misses 88996 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 2824 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 521770500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.006437 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 86172 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.936859 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1918.688120 # Average occupied blocks per context
system.cpu.icache.overall_accesses 13386326 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 9552.485505 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 6054.988859 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 13297330 # number of overall hits
system.cpu.icache.overall_miss_latency 850133000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.006648 # miss rate for overall accesses
system.cpu.icache.overall_misses 88996 # number of overall misses
system.cpu.icache.overall_mshr_hits 2824 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 521770500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.006437 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 86172 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 84124 # number of replacements
system.cpu.icache.sampled_refs 86171 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1918.688120 # Cycle average of tags in use
system.cpu.icache.total_refs 13297330 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 1204946 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 14764091 # Number of branches executed
system.cpu.iew.EXEC:nop 9400465 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.566510 # Inst execution rate
system.cpu.iew.EXEC:refs 36986360 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 15307304 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 42224308 # num instructions consuming a value
system.cpu.iew.WB:count 84456261 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.765793 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 32335073 # num instructions producing a value
system.cpu.iew.WB:rate 1.557690 # insts written-back per cycle
system.cpu.iew.WB:sent 84693859 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 401805 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 605778 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 23014883 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 5009 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 349401 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 16347988 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 99082046 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 21679056 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 539226 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 84934458 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 11054 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 8978 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 1305079 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 42917 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 953186 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 20710 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1355 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 2635484 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 1503369 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 20710 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 131758 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 270047 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.467970 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.467970 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 47968991 56.12% 56.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 42906 0.05% 56.17% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.17% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122147 0.14% 56.31% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 86 0.00% 56.31% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122353 0.14% 56.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 51 0.00% 56.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38520 0.05% 56.50% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.50% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 21790369 25.49% 82.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 15388261 18.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 85473684 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 995540 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011647 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 102737 10.32% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 453943 45.60% 55.92% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 438860 44.08% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 53013963 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.612286 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.719350 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 17564950 33.13% 33.13% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 14012876 26.43% 59.57% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 8103290 15.29% 74.85% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 4796735 9.05% 83.90% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 4597424 8.67% 92.57% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 2085134 3.93% 96.50% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 1155738 2.18% 98.68% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 468299 0.88% 99.57% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 229517 0.43% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 53013963 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.576455 # Inst issue rate
system.cpu.iq.iqInstsAdded 89676572 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 85473684 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 5009 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 9869392 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 46778 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 426 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 6797277 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 13413339 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 13386326 # ITB hits
system.cpu.itb.fetch_misses 27013 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 143495 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34335.046084 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31231.824393 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 61 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 4924813000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.999575 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 143434 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4479705500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999575 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 143434 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 147761 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34138.356934 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.221173 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 103271 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1518815500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.301094 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 44490 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1380712500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.301094 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 44490 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 3671 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 33969.081994 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31027.649142 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 124700500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 3671 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 113902500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 3671 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 149251 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 149251 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.688286 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 291256 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34288.480982 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.042890 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 103332 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 6443628500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.645219 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 187924 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 5860418000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.645219 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 187924 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.096999 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.471977 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3178.468873 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15465.728229 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 291256 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34288.480982 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.042890 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 103332 # number of overall hits
system.cpu.l2cache.overall_miss_latency 6443628500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.645219 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 187924 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 5860418000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.645219 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 187924 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 148884 # number of replacements
system.cpu.l2cache.sampled_refs 174227 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 18644.197102 # Cycle average of tags in use
system.cpu.l2cache.total_refs 119918 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 120621 # number of writebacks
system.cpu.memDep0.conflictingLoads 12607383 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 11255649 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 23014883 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 16347988 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 54218909 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 2001211 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 58273 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 28932787 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1273359 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 32 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 121782078 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 101070010 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 60804975 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 19289152 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 1305079 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 1405067 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 8258094 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 80667 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 5283 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 2766751 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 5281 # count of temporary serializing insts renamed
system.cpu.timesIdled 41950 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------
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