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---------- Begin Simulation Statistics ----------
host_inst_rate 1745846 # Simulator instruction rate (inst/s)
host_mem_usage 217668 # Number of bytes of host memory used
host_seconds 56.13 # Real time elapsed on the host
host_tick_rate 2379327214 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 97997303 # Number of instructions simulated
sim_seconds 0.133556 # Number of seconds simulated
sim_ticks 133556162000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 27164439 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 35927.990796 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32927.990796 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 27111418 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 1904938000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001952 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 53021 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1745875000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001952 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 53021 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 19865820 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55999.910387 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.910387 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 19754229 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 6249086000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.005617 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 111591 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 5914313000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005617 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 111591 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 292.838112 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 47030259 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 49534.809127 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 46534.809127 # average overall mshr miss latency
system.cpu.dcache.demand_hits 46865647 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 8154024000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.003500 # miss rate for demand accesses
system.cpu.dcache.demand_misses 164612 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 7660188000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003500 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 164612 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.995356 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4076.978068 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 47030259 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 49534.809127 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 46534.809127 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 46865647 # number of overall hits
system.cpu.dcache.overall_miss_latency 8154024000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.003500 # miss rate for overall accesses
system.cpu.dcache.overall_misses 164612 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 7660188000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003500 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 164612 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 155959 # number of replacements
system.cpu.dcache.sampled_refs 160055 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4076.978068 # Cycle average of tags in use
system.cpu.dcache.total_refs 46870204 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 1080546000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 109433 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.icache.ReadReq_accesses 78097320 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 24226.782314 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21226.782314 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 78078412 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 458080000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000242 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 18908 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 401356000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000242 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 18908 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 4129.385022 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 78097320 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 24226.782314 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 21226.782314 # average overall mshr miss latency
system.cpu.icache.demand_hits 78078412 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 458080000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000242 # miss rate for demand accesses
system.cpu.icache.demand_misses 18908 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 401356000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000242 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 18908 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.847875 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1736.448416 # Average occupied blocks per context
system.cpu.icache.overall_accesses 78097320 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 24226.782314 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 21226.782314 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 78078412 # number of overall hits
system.cpu.icache.overall_miss_latency 458080000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000242 # miss rate for overall accesses
system.cpu.icache.overall_misses 18908 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 401356000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000242 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 18908 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 16890 # number of replacements
system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1736.448416 # Cycle average of tags in use
system.cpu.icache.total_refs 78078412 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 107034 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 5565768000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 107034 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4281360000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 107034 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 71929 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 39643 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1678872000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.448859 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 32286 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1291440000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.448859 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 32286 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 4557 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51885.889840 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 236444000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 4557 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 182280000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 4557 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 109433 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 109433 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.358187 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 178963 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 39643 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 7244640000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.778485 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 139320 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 5572800000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.778485 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 139320 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.064995 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.477989 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2129.749713 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15662.741873 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 178963 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 39643 # number of overall hits
system.cpu.l2cache.overall_miss_latency 7244640000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.778485 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 139320 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 5572800000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.778485 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 139320 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 114093 # number of replacements
system.cpu.l2cache.sampled_refs 132791 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 17792.491585 # Cycle average of tags in use
system.cpu.l2cache.total_refs 47564 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 88579 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 267112324 # number of cpu cycles simulated
system.cpu.num_insts 97997303 # Number of instructions executed
system.cpu.num_refs 47871034 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
---------- End Simulation Statistics ----------
|
