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|
---------- Begin Simulation Statistics ----------
host_inst_rate 172436 # Simulator instruction rate (inst/s)
host_mem_usage 208600 # Number of bytes of host memory used
host_seconds 10067.76 # Real time elapsed on the host
host_tick_rate 69724149 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1736043781 # Number of instructions simulated
sim_seconds 0.701966 # Number of seconds simulated
sim_ticks 701966325500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 292400183 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 299029010 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 138 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 19849428 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 261227143 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 338874509 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 23706003 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 214632552 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 64109829 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 1311318680 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.387748 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.144873 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 679377178 51.81% 51.81% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 251802247 19.20% 71.01% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 122784402 9.36% 80.37% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 79744679 6.08% 86.46% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 49330681 3.76% 90.22% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 25797964 1.97% 92.18% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 24618038 1.88% 94.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 13753662 1.05% 95.11% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 64109829 4.89% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1311318680 # Number of insts commited each cycle
system.cpu.commit.COM:count 1819780126 # Number of instructions committed
system.cpu.commit.COM:fp_insts 805525 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 16767440 # Number of function calls committed.
system.cpu.commit.COM:int_insts 1718967519 # Number of committed integer instructions.
system.cpu.commit.COM:loads 444595663 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 605324165 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 19848912 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 560481052 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
system.cpu.cpi 0.808697 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.808697 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses 524164871 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 16357.820717 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10976.941721 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 514173767 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 163432688000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.019061 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 9991104 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 2714607 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 79873683500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013882 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7276497 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 27513.387050 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20471.203773 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 155977688 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 130710984385 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.029558 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 4750814 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 2866037 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 38583654034 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011726 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1884777 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.415452 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 32995.492313 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 73.150457 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 37718 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 65111 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 118978242 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2148369500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 684893373 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 19952.876714 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency
system.cpu.dcache.demand_hits 670151455 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 294143672385 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.021524 # miss rate for demand accesses
system.cpu.dcache.demand_misses 14741918 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 5580644 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 118457337534 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.013376 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9161274 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.997370 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4085.228479 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 684893373 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 19952.876714 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 670151455 # number of overall hits
system.cpu.dcache.overall_miss_latency 294143672385 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.021524 # miss rate for overall accesses
system.cpu.dcache.overall_misses 14741918 # number of overall misses
system.cpu.dcache.overall_mshr_hits 5580644 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 118457337534 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.013376 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9161274 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 9157179 # number of replacements
system.cpu.dcache.sampled_refs 9161275 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4085.228479 # Cycle average of tags in use
system.cpu.dcache.total_refs 670151457 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 7052593000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 3077964 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 69300100 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 734 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 53326576 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 2753583044 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 704925020 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 533426665 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 83930076 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 1732 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 3666895 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 776927298 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 761318004 # DTB hits
system.cpu.dtb.data_misses 15609294 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 573302197 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 563960671 # DTB read hits
system.cpu.dtb.read_misses 9341526 # DTB read misses
system.cpu.dtb.write_accesses 203625101 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 197357333 # DTB write hits
system.cpu.dtb.write_misses 6267768 # DTB write misses
system.cpu.fetch.Branches 338874509 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 346935606 # Number of cache lines fetched
system.cpu.fetch.Cycles 547160939 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 8134553 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 2804810127 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 26702024 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.241375 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 346935606 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 316106186 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.997824 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1395248756 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.010258 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.885668 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 848087817 60.78% 60.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 47124000 3.38% 64.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 30216424 2.17% 66.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 49573099 3.55% 69.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 121201096 8.69% 78.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 67474425 4.84% 83.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 44590738 3.20% 86.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 37036211 2.65% 89.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 149944946 10.75% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1395248756 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 788 # number of floating regfile reads
system.cpu.fp_regfile_writes 457 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 346935606 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35242.436306 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35438.663746 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 346934350 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 44264500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1256 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 343 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 32355500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 913 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 379993.811610 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 346935606 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35242.436306 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency
system.cpu.icache.demand_hits 346934350 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 44264500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_misses 1256 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 343 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 32355500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 913 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.349808 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 716.407669 # Average occupied blocks per context
system.cpu.icache.overall_accesses 346935606 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35242.436306 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 346934350 # number of overall hits
system.cpu.icache.overall_miss_latency 44264500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_misses 1256 # number of overall misses
system.cpu.icache.overall_mshr_hits 343 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 32355500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 913 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 913 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 716.407669 # Cycle average of tags in use
system.cpu.icache.total_refs 346934350 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 8683896 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 278210520 # Number of branches executed
system.cpu.iew.EXEC:nop 128264130 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.613458 # Inst execution rate
system.cpu.iew.EXEC:refs 776927311 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 203625107 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1505740839 # num instructions consuming a value
system.cpu.iew.WB:count 2224607717 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.814091 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1225810379 # num instructions producing a value
system.cpu.iew.WB:rate 1.584554 # insts written-back per cycle
system.cpu.iew.WB:sent 2246216503 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 21671278 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 12833645 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 610412990 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 23291799 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 227416042 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2568259823 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 573302204 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 37676740 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2265186271 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 698616 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 16282 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 83930076 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 949861 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 162061 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 39718780 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 292481 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 198174 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 20 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 165817327 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 66687540 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 198174 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 3374280 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 18296998 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 3052265091 # number of integer regfile reads
system.cpu.int_regfile_writes 1775418368 # number of integer regfile writes
system.cpu.ipc 1.236558 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.236558 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1511867682 65.65% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 94 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 234 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 19 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 136 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 16 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 584171534 25.37% 91.02% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 206823272 8.98% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 2302863011 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 12654324 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.005495 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 2979112 23.54% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 7017383 55.45% 79.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 2657829 21.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 1395248756 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.650504 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.793673 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 526952247 37.77% 37.77% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 258740979 18.54% 56.31% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 229473715 16.45% 72.76% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 137779252 9.87% 82.63% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 109981774 7.88% 90.52% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 76286512 5.47% 95.98% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 43503715 3.12% 99.10% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 10789596 0.77% 99.88% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 1740966 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1395248756 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.640295 # Inst issue rate
system.cpu.iq.fp_alu_accesses 821696 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 1643378 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 816998 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 858249 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 2314695639 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 6012429707 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 2223790719 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 3126227824 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 2439995648 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2302863011 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 686898644 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 443983 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 276282436 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 346935639 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 346935606 # ITB hits
system.cpu.itb.fetch_misses 33 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1884779 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34458.146481 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31271.142152 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 1001508 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 30435881500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.468634 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 883271 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 27620893000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468634 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 883271 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 7277409 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34326.005759 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31136.294702 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5456843 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 62492759000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.250167 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1820566 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 56685679500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250167 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1820566 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 3077964 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 3077964 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10347.377725 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.807961 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 1697 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 17559500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 9162188 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34369.172587 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 6458351 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 92928640500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.295108 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 2703837 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 84306572500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.295108 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 2703837 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.482747 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.327799 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 15818.650272 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10741.307183 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 9162188 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34369.172587 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 6458351 # number of overall hits
system.cpu.l2cache.overall_miss_latency 92928640500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.295108 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 2703837 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 84306572500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.295108 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 2703837 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 2693244 # number of replacements
system.cpu.l2cache.sampled_refs 2717889 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 26559.957454 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7631725 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 146645124500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1171773 # number of writebacks
system.cpu.memDep0.conflictingLoads 58011440 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 46695485 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 610412990 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 227416042 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.numCycles 1403932652 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 45015493 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 2058465 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 721970868 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 19605286 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 493414 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 3482054752 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2693944594 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2019690549 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 519735088 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 83930076 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 24596395 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 643487586 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 875387 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 3481179365 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 836 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 50 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 51588618 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 48 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 3541690829 # The number of ROB reads
system.cpu.rob.rob_writes 4844528665 # The number of ROB writes
system.cpu.timesIdled 283673 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------
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