blob: 93a32f882f411c5bd77b134917d548eadbf1645f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
|
---------- Begin Simulation Statistics ----------
host_inst_rate 192033 # Simulator instruction rate (inst/s)
host_mem_usage 206980 # Number of bytes of host memory used
host_seconds 9040.35 # Real time elapsed on the host
host_tick_rate 81902195 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1736043781 # Number of instructions simulated
sim_seconds 0.740425 # Number of seconds simulated
sim_ticks 740424887500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 300304269 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 307023866 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 161 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 19915568 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 268271856 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 347819261 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 23893430 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 214632552 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 63188477 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 1374695730 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.323769 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.099460 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 733755921 53.38% 53.38% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 260590847 18.96% 72.33% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 127148586 9.25% 81.58% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 73808717 5.37% 86.95% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 48837558 3.55% 90.50% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 32392808 2.36% 92.86% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 24165844 1.76% 94.62% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 10806972 0.79% 95.40% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 63188477 4.60% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1374695730 # Number of insts commited each cycle
system.cpu.commit.COM:count 1819780126 # Number of instructions committed
system.cpu.commit.COM:loads 445666361 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 606571343 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 19915049 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 631770816 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
system.cpu.cpi 0.853003 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.853003 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses 523747084 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 16905.655994 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11269.981612 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 513424902 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 174503258000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.019708 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 10322182 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 3045892 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 82003654500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013893 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7276290 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 33742.228480 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.275529 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 155297365 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 183258665559 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.033791 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 5431137 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 3182597 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 83540626157 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 2248540 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6330.872599 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 30366.853399 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 73.096818 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 156412 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 65334 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 990224445 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1983988000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 684475586 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 22710.257030 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 17380.287171 # average overall mshr miss latency
system.cpu.dcache.demand_hits 668722267 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 357761923559 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.023015 # miss rate for demand accesses
system.cpu.dcache.demand_misses 15753319 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 6228489 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 165544280657 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.013916 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9524830 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.997494 # Average percentage of cache occupancy
system.cpu.dcache.occ_%::1 -0.003143 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4085.737319 # Average occupied blocks per context
system.cpu.dcache.occ_blocks::1 -12.874688 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 684475586 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 22710.257030 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 17380.287171 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 668722267 # number of overall hits
system.cpu.dcache.overall_miss_latency 357761923559 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.023015 # miss rate for overall accesses
system.cpu.dcache.overall_misses 15753319 # number of overall misses
system.cpu.dcache.overall_mshr_hits 6228489 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 165544280657 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.013916 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9524830 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 9156903 # number of replacements
system.cpu.dcache.sampled_refs 9160999 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4079.299976 # Cycle average of tags in use
system.cpu.dcache.total_refs 669639874 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 7084220000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2245460 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 97965081 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 741 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 54990106 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 2817972216 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 726420898 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 545630418 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 93906879 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 1735 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 4679333 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 771953785 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 755880744 # DTB hits
system.cpu.dtb.data_misses 16073041 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 569575118 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 560292416 # DTB read hits
system.cpu.dtb.read_misses 9282702 # DTB read misses
system.cpu.dtb.write_accesses 202378667 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 195588328 # DTB write hits
system.cpu.dtb.write_misses 6790339 # DTB write misses
system.cpu.fetch.Branches 347819261 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 356032734 # Number of cache lines fetched
system.cpu.fetch.Cycles 917156426 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 8668632 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 2872343822 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 28362919 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.234878 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 356032734 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 324197699 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.939659 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1468602609 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.955835 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.862588 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 907478951 61.79% 61.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 48285594 3.29% 65.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 31293098 2.13% 67.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 51463172 3.50% 70.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 124103039 8.45% 79.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 68291233 4.65% 83.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 47448055 3.23% 87.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 37389871 2.55% 89.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 152849596 10.41% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1468602609 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 356032734 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35280.127694 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35449.450549 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 356031481 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 44206000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1253 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 343 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 32259000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 391243.385714 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 356032734 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35280.127694 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35449.450549 # average overall mshr miss latency
system.cpu.icache.demand_hits 356031481 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 44206000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_misses 1253 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 343 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 32259000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.349473 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 715.720591 # Average occupied blocks per context
system.cpu.icache.overall_accesses 356032734 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35280.127694 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35449.450549 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 356031481 # number of overall hits
system.cpu.icache.overall_miss_latency 44206000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_misses 1253 # number of overall misses
system.cpu.icache.overall_mshr_hits 343 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 32259000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 715.720591 # Cycle average of tags in use
system.cpu.icache.total_refs 356031481 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 12247167 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 283205490 # Number of branches executed
system.cpu.iew.EXEC:nop 130221162 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.544186 # Inst execution rate
system.cpu.iew.EXEC:refs 773252228 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 202589844 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1537746587 # num instructions consuming a value
system.cpu.iew.WB:count 2247853705 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.811174 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1247380184 # num instructions producing a value
system.cpu.iew.WB:rate 1.517949 # insts written-back per cycle
system.cpu.iew.WB:sent 2269524166 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 21734619 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 17681894 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 621844790 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 21649497 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 234635839 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2626124753 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 570662384 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 37709808 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2286707552 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 438059 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 36964 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 93906879 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 800629 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 361620 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 36313428 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 213767 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 2870017 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 18 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 176178429 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 73730857 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 2870017 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 3392458 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 18342161 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.172329 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.172329 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1537413633 66.14% 66.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 96 0.00% 66.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 239 0.00% 66.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 20 0.00% 66.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 141 0.00% 66.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 17 0.00% 66.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 66.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 581325773 25.01% 91.15% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 205677417 8.85% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 2324417360 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 13099894 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.005636 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 2747666 20.97% 20.97% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 20.97% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 20.97% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 20.97% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 20.97% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 20.97% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 20.97% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 20.97% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 20.97% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 8624380 65.84% 86.81% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 1727848 13.19% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 1468602609 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.582741 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.758662 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 577211692 39.30% 39.30% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 268561729 18.29% 57.59% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 245516096 16.72% 74.31% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 137351239 9.35% 83.66% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 112900190 7.69% 91.35% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 73000831 4.97% 96.32% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 43951863 2.99% 99.31% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 8418123 0.57% 99.88% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 1690846 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1468602609 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.569651 # Inst issue rate
system.cpu.iq.iqInstsAdded 2495903546 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2324417360 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 740504039 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1264443 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 323242086 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 356032768 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 356032734 # ITB hits
system.cpu.itb.fetch_misses 34 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1884709 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34610.194422 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31460.521684 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 65230144918 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1884709 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 59293928362 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1884709 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 7277200 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34313.246356 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31139.092194 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5388273 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 64815217500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.259568 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1888927 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 58819472000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259568 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1888927 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 363845 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34326.565768 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31260.856148 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 12489549322 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 363845 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11374106205 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 363845 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2245460 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 2245460 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 11887.575431 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.418021 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 39831 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 473494017 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 9161909 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34461.554431 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31299.627299 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 5388273 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 130045362418 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.411883 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 3773636 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 118113400362 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.411883 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 3773636 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.452605 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.337458 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 14830.970465 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 11057.808672 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 9161909 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34461.554431 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.627299 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 5388273 # number of overall hits
system.cpu.l2cache.overall_miss_latency 130045362418 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.411883 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 3773636 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 118113400362 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.411883 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 3773636 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 2759709 # number of replacements
system.cpu.l2cache.sampled_refs 2784305 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 25888.779137 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6732509 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 154525864500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1195751 # number of writebacks
system.cpu.memDep0.conflictingLoads 123998073 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 64478030 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 621844790 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 234635839 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 1480849776 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 67789415 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 5483545 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 745501679 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 20525033 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 1073372 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 3564600090 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2755431831 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2063008571 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 531263306 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 93906879 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 30140307 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 686805608 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 1023 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 61497352 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 46 # count of temporary serializing insts renamed
system.cpu.timesIdled 461191 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------
|