blob: 612ce5ecb903662947c34e4fbdea961d98b0071b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.630794 # Number of seconds simulated
sim_ticks 630794322500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 76362 # Simulator instruction rate (inst/s)
host_tick_rate 27746395 # Simulator tick rate (ticks/s)
host_mem_usage 246464 # Number of bytes of host memory used
host_seconds 22734.28 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 603175408 # DTB read hits
system.cpu.dtb.read_misses 10382155 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 613557563 # DTB read accesses
system.cpu.dtb.write_hits 207486280 # DTB write hits
system.cpu.dtb.write_misses 6703729 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 214190009 # DTB write accesses
system.cpu.dtb.data_hits 810661688 # DTB hits
system.cpu.dtb.data_misses 17085884 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 827747572 # DTB accesses
system.cpu.itb.fetch_hits 389142997 # ITB hits
system.cpu.itb.fetch_misses 38 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 389143035 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 1261588646 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 372091723 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 287344410 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 19482025 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 339026759 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 332564866 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 24521483 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 1913 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 401603290 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 3128927097 # Number of instructions fetch has processed
system.cpu.fetch.Branches 372091723 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 357086349 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 613258490 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 135586269 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 127041969 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 951 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 389142997 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 9519109 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1250962446 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.501216 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.011577 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 637703956 50.98% 50.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 53070188 4.24% 55.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 35635977 2.85% 58.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 54551976 4.36% 62.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 136343152 10.90% 73.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 75070366 6.00% 79.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 52403227 4.19% 83.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 43683605 3.49% 87.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 162499999 12.99% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1250962446 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.294939 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.480148 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 431101199 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 113892603 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 582711633 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 14200214 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 109056797 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 57497676 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 1028 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3047130030 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2024 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 109056797 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 453766318 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 66152638 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 4489 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 572459547 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 49522657 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2962251585 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 509472 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 8488964 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 37728922 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2215831278 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3828352305 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3827339752 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1012553 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 839628315 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 266 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 263 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 102105357 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 670128900 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 250448120 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 97927277 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 62674140 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2669873432 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 219 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2466087969 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1699054 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 923450677 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 397988094 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 190 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1250962446 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.971353 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.922762 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 403537577 32.26% 32.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 206908557 16.54% 48.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 196272095 15.69% 64.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 156883452 12.54% 77.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 140843033 11.26% 88.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 74249795 5.94% 94.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 49611438 3.97% 98.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 17556861 1.40% 99.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 5099638 0.41% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1250962446 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 3929936 26.79% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.79% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 9164613 62.47% 89.26% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 1575877 10.74% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1614368204 65.46% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 93 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 252 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 20 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 149 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 19 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.46% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 631861651 25.62% 91.08% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 219857557 8.92% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2466087969 # Type of FU issued
system.cpu.iq.rate 1.954748 # Inst issue rate
system.cpu.iq.fu_busy_cnt 14670426 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005949 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6197744460 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3592745886 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2365749940 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 1763404 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1020600 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 828073 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2479878842 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 879553 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 54119833 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 225533237 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 274653 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 443666 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 89719618 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 53 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 162300 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 109056797 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 23925138 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1338311 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2811874535 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 12833381 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 670128900 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 250448120 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 219 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 545828 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 18223 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 443666 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 20334836 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 2010249 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 22345085 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2412233933 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 613557757 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 53854036 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 142000884 # number of nop insts executed
system.cpu.iew.exec_refs 827747782 # number of memory reference insts executed
system.cpu.iew.exec_branches 295599123 # Number of branches executed
system.cpu.iew.exec_stores 214190025 # Number of stores executed
system.cpu.iew.exec_rate 1.912061 # Inst execution rate
system.cpu.iew.wb_sent 2392748648 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2366578013 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1358866108 # num instructions producing a value
system.cpu.iew.wb_consumers 1719778019 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.875871 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.790140 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 759617769 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 19481102 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1141905649 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.593634 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.464996 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 604531379 52.94% 52.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 194846854 17.06% 70.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 88590760 7.76% 77.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 56412510 4.94% 82.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 37294667 3.27% 85.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 28799723 2.52% 88.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 22448338 1.97% 90.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 21204433 1.86% 92.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 87776985 7.69% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1141905649 # Number of insts commited each cycle
system.cpu.commit.count 1819780126 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 605324165 # Number of memory references committed
system.cpu.commit.loads 444595663 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 214632552 # Number of branches committed
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
system.cpu.commit.bw_lim_events 87776985 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3547747359 # The number of ROB reads
system.cpu.rob.rob_writes 5268048666 # The number of ROB writes
system.cpu.timesIdled 494946 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 10626200 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
system.cpu.cpi 0.726703 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.726703 # CPI: Total CPI of All Threads
system.cpu.ipc 1.376078 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.376078 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3245673408 # number of integer regfile reads
system.cpu.int_regfile_writes 1894558271 # number of integer regfile writes
system.cpu.fp_regfile_reads 13236 # number of floating regfile reads
system.cpu.fp_regfile_writes 507 # number of floating regfile writes
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.tagsinuse 755.752117 # Cycle average of tags in use
system.cpu.icache.total_refs 389141650 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 944 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 412226.324153 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 755.752117 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.369020 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 389141650 # number of ReadReq hits
system.cpu.icache.demand_hits 389141650 # number of demand (read+write) hits
system.cpu.icache.overall_hits 389141650 # number of overall hits
system.cpu.icache.ReadReq_misses 1347 # number of ReadReq misses
system.cpu.icache.demand_misses 1347 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1347 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 47225000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 47225000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 47225000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 389142997 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 389142997 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 389142997 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35059.391240 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35059.391240 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35059.391240 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 403 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 403 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 403 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 944 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 944 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 944 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 33492000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 33492000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 33492000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35478.813559 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35478.813559 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35478.813559 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9159626 # number of replacements
system.cpu.dcache.tagsinuse 4087.185824 # Cycle average of tags in use
system.cpu.dcache.total_refs 694644975 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9163722 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 75.803803 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 5155515000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4087.185824 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.997848 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 538784960 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 155860012 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits 694644972 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 694644972 # number of overall hits
system.cpu.dcache.ReadReq_misses 10193496 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 4868490 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 15061986 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 15061986 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 169402977500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 135886448359 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 305289425859 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 305289425859 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 548978456 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 709706958 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 709706958 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.018568 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.030290 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.250000 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.021223 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.021223 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 16618.731935 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 27911.415728 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 20268.869315 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 20268.869315 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 119358733 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2148382000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 37827 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 65115 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3155.384593 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 32993.657375 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 3077546 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 2914965 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 2983300 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 5898265 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 5898265 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 7278531 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1885190 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses 9163721 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 9163721 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 80729480000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 38630501513 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 119359981513 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 119359981513 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013258 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011729 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.250000 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.012912 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.012912 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11091.452382 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20491.569292 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 13025.274505 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 13025.274505 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2693791 # number of replacements
system.cpu.l2cache.tagsinuse 26705.078667 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7632821 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2718423 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.807812 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 127919553500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 15965.123035 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10739.955632 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.487217 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.327757 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 5458638 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 3077546 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 1001691 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 6460329 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 6460329 # number of overall hits
system.cpu.l2cache.ReadReq_misses 1820833 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 883504 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 2704337 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 2704337 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 62507649000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 30451140500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 92958789500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 92958789500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 7279471 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 3077546 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1885195 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 9164666 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 9164666 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.250133 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.468654 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.295083 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.295083 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34329.149900 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34466.330090 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34373.966521 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34373.966521 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 17593500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 1703 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10330.886671 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 1171811 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 1820833 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 883504 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 2704337 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 2704337 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 56722118000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 27628606500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 84350724500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 84350724500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250133 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468654 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.295083 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.295083 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31151.740989 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31271.625822 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31190.907235 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31190.907235 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|