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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.096611 # Number of seconds simulated
sim_ticks 96610526000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 102112 # Simulator instruction rate (inst/s)
host_tick_rate 44565176 # Simulator tick rate (ticks/s)
host_mem_usage 220868 # Number of bytes of host memory used
host_seconds 2167.85 # Real time elapsed on the host
sim_insts 221363017 # Number of instructions simulated
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 193221053 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 25817967 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 25817967 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 2894858 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 23614164 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 20981330 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 30977399 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 261503264 # Number of instructions fetch has processed
system.cpu.fetch.Branches 25817967 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 20981330 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 70791188 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 26915794 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 67651206 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 160 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1398 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 28846864 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 549492 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 193133856 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.260391 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.334586 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 124189193 64.30% 64.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4110604 2.13% 66.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3242349 1.68% 68.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4337138 2.25% 70.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4293938 2.22% 72.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4598067 2.38% 74.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5546943 2.87% 77.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3021455 1.56% 79.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 39794169 20.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 193133856 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.133619 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.353389 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 44744191 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 57710964 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 57165261 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 9800935 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 23712505 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 424257825 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 23712505 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 53368695 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 14594998 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 21883 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 57606354 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 43829421 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 411666463 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 18981117 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 22454802 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 438110122 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1066455351 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1055559190 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10896161 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 203746713 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1780 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1774 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 94916865 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 104240418 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 37277466 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 67123936 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 21592423 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 396698453 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1768 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 287681057 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 248197 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 174766428 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 350779105 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 522 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 193133856 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.489542 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.479240 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 60593209 31.37% 31.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 53908728 27.91% 59.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 35738338 18.50% 77.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 21062429 10.91% 88.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 13747169 7.12% 95.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 5239198 2.71% 98.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2106456 1.09% 99.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 621668 0.32% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 116661 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 193133856 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 106266 3.87% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2319161 84.53% 88.40% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 318223 11.60% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 1204809 0.42% 0.42% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 187032245 65.01% 65.43% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.43% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1651608 0.57% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 73242981 25.46% 91.47% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 24549414 8.53% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 287681057 # Type of FU issued
system.cpu.iq.rate 1.488870 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2743650 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.009537 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 765972748 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 566387994 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 278383951 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 5515069 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 5414925 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2649060 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 286446350 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2773548 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 18375293 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 47590828 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 32389 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 343467 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 16761750 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 46017 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 23712505 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 356267 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 212332 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 396700221 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 134682 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 104240418 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 37277466 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1768 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 118966 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 14039 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 343467 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 2505670 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 594786 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 3100456 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 283858854 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 71711617 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3822203 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 95762495 # number of memory reference insts executed
system.cpu.iew.exec_branches 15668383 # Number of branches executed
system.cpu.iew.exec_stores 24050878 # Number of stores executed
system.cpu.iew.exec_rate 1.469089 # Inst execution rate
system.cpu.iew.wb_sent 282330192 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 281033011 # cumulative count of insts written-back
system.cpu.iew.wb_producers 227942764 # num instructions producing a value
system.cpu.iew.wb_consumers 378918606 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.454464 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.601561 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 175344362 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 2895014 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 169421351 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.306583 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.742468 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 63568929 37.52% 37.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 62259787 36.75% 74.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 15643694 9.23% 83.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 11988406 7.08% 90.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 5417709 3.20% 93.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2980917 1.76% 95.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 2013932 1.19% 96.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1192205 0.70% 97.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 4355772 2.57% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 169421351 # Number of insts commited each cycle
system.cpu.commit.count 221363017 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 77165306 # Number of memory references committed
system.cpu.commit.loads 56649590 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 12326943 # Number of branches committed
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
system.cpu.commit.int_insts 220339606 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 4355772 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 561772958 # The number of ROB reads
system.cpu.rob.rob_writes 817171098 # The number of ROB writes
system.cpu.timesIdled 1889 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 87197 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 221363017 # Number of Instructions Simulated
system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated
system.cpu.cpi 0.872870 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.872870 # CPI: Total CPI of All Threads
system.cpu.ipc 1.145646 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.145646 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 530742767 # number of integer regfile reads
system.cpu.int_regfile_writes 288972647 # number of integer regfile writes
system.cpu.fp_regfile_reads 3616458 # number of floating regfile reads
system.cpu.fp_regfile_writes 2303580 # number of floating regfile writes
system.cpu.misc_regfile_reads 149927786 # number of misc regfile reads
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
system.cpu.icache.replacements 4235 # number of replacements
system.cpu.icache.tagsinuse 1597.100373 # Cycle average of tags in use
system.cpu.icache.total_refs 28839309 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 6200 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4651.501452 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1597.100373 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.779834 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 28839309 # number of ReadReq hits
system.cpu.icache.demand_hits 28839309 # number of demand (read+write) hits
system.cpu.icache.overall_hits 28839309 # number of overall hits
system.cpu.icache.ReadReq_misses 7555 # number of ReadReq misses
system.cpu.icache.demand_misses 7555 # number of demand (read+write) misses
system.cpu.icache.overall_misses 7555 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 173857500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 173857500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 173857500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 28846864 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 28846864 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 28846864 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000262 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000262 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000262 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 23012.243547 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 23012.243547 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 23012.243547 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 1113 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1113 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1113 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 6442 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 6442 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 6442 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 125492000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 125492000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 125492000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000223 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000223 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000223 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 19480.285626 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 19480.285626 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 19480.285626 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 59 # number of replacements
system.cpu.dcache.tagsinuse 1420.172872 # Cycle average of tags in use
system.cpu.dcache.total_refs 73596568 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1986 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 37057.687815 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 1420.172872 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.346722 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 53088625 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 20507488 # number of WriteReq hits
system.cpu.dcache.demand_hits 73596113 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 73596113 # number of overall hits
system.cpu.dcache.ReadReq_misses 844 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 8242 # number of WriteReq misses
system.cpu.dcache.demand_misses 9086 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 9086 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 26292500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 227102000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 253394500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 253394500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 53089469 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 73605199 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 73605199 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.000402 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.000123 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000123 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 31152.251185 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 27554.234409 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 27888.454766 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 27888.454766 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 14 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 420 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 6436 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 6856 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 6856 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1806 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 2230 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 2230 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 14047000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 63209500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 77256500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 77256500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000030 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000030 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 33129.716981 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34999.723145 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34644.170404 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34644.170404 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2499.008056 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2867 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3761 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.762297 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 2497.026903 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 1.981153 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.076203 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.000060 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 2866 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 14 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 2874 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 2874 # number of overall hits
system.cpu.l2cache.ReadReq_misses 3757 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 242 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 1557 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 5314 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 5314 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 128666000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 53239000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 181905000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 181905000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 6623 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 14 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 242 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1565 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 8188 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 8188 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.567266 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.994888 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.648999 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.648999 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34247.005590 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34193.320488 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34231.275875 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34231.275875 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 3757 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 242 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 1557 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 5314 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 5314 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 116539500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7502000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48375000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 164914500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 164914500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567266 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994888 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.648999 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.648999 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.297312 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.364162 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.966880 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.966880 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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