blob: 6577540a080b765e90e5a7aa6d252d75b188d07d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
|
---------- Begin Simulation Statistics ----------
host_inst_rate 187440 # Simulator instruction rate (inst/s)
host_mem_usage 240848 # Number of bytes of host memory used
host_seconds 1180.98 # Real time elapsed on the host
host_tick_rate 96568147 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 221363017 # Number of instructions simulated
sim_seconds 0.114045 # Number of seconds simulated
sim_ticks 114045138500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 15975516 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 17934192 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 3581786 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 18022710 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 18022710 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 12326943 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 723634 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 220177428 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.005385 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.254706 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 88641889 40.26% 40.26% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 86561337 39.31% 79.57% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 21386723 9.71% 89.29% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 12188145 5.54% 94.82% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 6588488 2.99% 97.82% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 2070275 0.94% 98.76% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 1149159 0.52% 99.28% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 867778 0.39% 99.67% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 723634 0.33% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 220177428 # Number of insts commited each cycle
system.cpu.commit.COM:count 221363017 # Number of instructions committed
system.cpu.commit.COM:fp_insts 2162459 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 220339606 # Number of committed integer instructions.
system.cpu.commit.COM:loads 56649590 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 77165306 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 3581794 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 48027716 # The number of squashed insts skipped by commit
system.cpu.committedInsts 221363017 # Number of Instructions Simulated
system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated
system.cpu.cpi 1.030390 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.030390 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 50422643 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 32842.809365 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34433.615819 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 50422045 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 19640000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000012 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 598 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 244 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 12189500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 354 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 26406.061747 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35285.532995 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 20510418 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 140269000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000259 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 5312 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 3736 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 55610000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1576 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 36752.571503 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 70938373 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 27057.360406 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35129.274611 # average overall mshr miss latency
system.cpu.dcache.demand_hits 70932463 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 159909000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000083 # miss rate for demand accesses
system.cpu.dcache.demand_misses 5910 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 3980 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 67799500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1930 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.336507 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 1378.331851 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 70938373 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 27057.360406 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35129.274611 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 70932463 # number of overall hits
system.cpu.dcache.overall_miss_latency 159909000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000083 # miss rate for overall accesses
system.cpu.dcache.overall_misses 5910 # number of overall misses
system.cpu.dcache.overall_mshr_hits 3980 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 67799500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1930 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 47 # number of replacements
system.cpu.dcache.sampled_refs 1930 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1378.331851 # Cycle average of tags in use
system.cpu.dcache.total_refs 70932463 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 10 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 1914286 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 286005423 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 48312658 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 169297181 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 7787199 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 653303 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 18022710 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 18867666 # Number of cache lines fetched
system.cpu.fetch.Cycles 179995924 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 191272 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 169328996 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 3686154 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.079016 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 18867666 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 15975516 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.742377 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 227964627 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.282286 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.366402 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 54957212 24.11% 24.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 110607036 48.52% 72.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 34696842 15.22% 87.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 19348316 8.49% 96.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1875902 0.82% 97.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1062317 0.47% 97.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 939798 0.41% 98.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1341 0.00% 98.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 4475863 1.96% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 227964627 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 3211744 # number of floating regfile reads
system.cpu.fp_regfile_writes 2048533 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 18867666 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 25730.265551 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22379.751901 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 18862168 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 141465000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000291 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 5498 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 111854000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000265 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 4998 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 3774.698419 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 18867666 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 25730.265551 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22379.751901 # average overall mshr miss latency
system.cpu.icache.demand_hits 18862168 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 141465000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000291 # miss rate for demand accesses
system.cpu.icache.demand_misses 5498 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 500 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 111854000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000265 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 4998 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.745890 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1527.583314 # Average occupied blocks per context
system.cpu.icache.overall_accesses 18867666 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 25730.265551 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22379.751901 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 18862168 # number of overall hits
system.cpu.icache.overall_miss_latency 141465000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000291 # miss rate for overall accesses
system.cpu.icache.overall_misses 5498 # number of overall misses
system.cpu.icache.overall_mshr_hits 500 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 111854000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000265 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 4998 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 3094 # number of replacements
system.cpu.icache.sampled_refs 4997 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1527.583314 # Cycle average of tags in use
system.cpu.icache.total_refs 18862168 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 125651 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 13177188 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.062789 # Inst execution rate
system.cpu.iew.EXEC:refs 86183722 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 21962366 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 296340219 # num instructions consuming a value
system.cpu.iew.WB:count 239588905 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.644617 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 191026075 # num instructions producing a value
system.cpu.iew.WB:rate 1.050413 # insts written-back per cycle
system.cpu.iew.WB:sent 240106417 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 3659082 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 1291 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 69776556 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 1273 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 2389686 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 24137923 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 269390730 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 64221356 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3582148 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 242411882 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 7787199 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 324 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 13515418 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 128079 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 128891 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 44661 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 13126966 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 3622207 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 128891 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 152659 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3506423 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 488710459 # number of integer regfile reads
system.cpu.int_regfile_writes 250225793 # number of integer regfile writes
system.cpu.ipc 0.970506 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.970506 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1179793 0.48% 0.48% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 155739742 63.31% 63.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 1520188 0.62% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 64.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 65456200 26.61% 91.02% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 22098107 8.98% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 245994030 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 166267 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.000676 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 4 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 131346 79.00% 79.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 34917 21.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 227964627 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.079089 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.987640 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 72171112 31.66% 31.66% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 90119003 39.53% 71.19% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 46322685 20.32% 91.51% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 15038489 6.60% 98.11% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 3583873 1.57% 99.68% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 613391 0.27% 99.95% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 102303 0.04% 99.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 12243 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 1528 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 227964627 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.078494 # Inst issue rate
system.cpu.iq.fp_alu_accesses 2547074 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 5090153 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 2386799 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 3193028 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 242433430 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 715029059 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 237202106 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 313965679 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 269389457 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 245994030 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 1273 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 47650161 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 258 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 27 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 91534276 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 1576 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34382.484076 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31064.649682 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 53980500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.996193 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1570 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48771500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996193 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1570 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 5352 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34258.559622 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.566706 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1964 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 116068000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.633034 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3388 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 105148500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.633034 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3388 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.579180 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 6928 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34297.801533 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31044.776119 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1970 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 170048500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.715647 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4958 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 153920000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.715647 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 4958 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.067776 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000031 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2220.891460 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 1.016755 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 6928 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34297.801533 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31044.776119 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1970 # number of overall hits
system.cpu.l2cache.overall_miss_latency 170048500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.715647 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4958 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 153920000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.715647 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 4958 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3391 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 2221.908214 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1964 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 28553702 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 6206376 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 69776556 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 24137923 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 125230087 # number of misc regfile reads
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
system.cpu.numCycles 228090278 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 31917 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 234363409 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 638720 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 52054674 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 682190 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 732163494 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 280433210 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 305502440 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 166205742 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 7787199 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 1869216 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 71139031 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 7184355 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 724979139 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 15879 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 1273 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 3670415 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 1276 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 488844527 # The number of ROB reads
system.cpu.rob.rob_writes 546568715 # The number of ROB writes
system.cpu.timesIdled 2341 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
---------- End Simulation Statistics ----------
|
