path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.906052                       # Number of seconds simulated
sim_ticks                                1906052165500                       # Number of ticks simulated
final_tick                               1906052165500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 263346                       # Simulator instruction rate (inst/s)
host_op_rate                                   263346                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             8940174363                       # Simulator tick rate (ticks/s)
host_mem_usage                                 335264                       # Number of bytes of host memory used
host_seconds                                   213.20                       # Real time elapsed on the host
sim_insts                                    56145499                       # Number of instructions simulated
sim_ops                                      56145499                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst           1044672                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24858688                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             25904320                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1044672                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1044672                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7563072                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7563072                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              16323                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388417                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                404755                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          118173                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               118173                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               548082                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13041977                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               504                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13590562                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          548082                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             548082                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3967925                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3967925                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3967925                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              548082                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13041977                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide              504                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               17558487                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        404755                       # Number of read requests accepted
system.physmem.writeReqs                       118173                       # Number of write requests accepted
system.physmem.readBursts                      404755                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     118173                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 25897216                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7104                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7561728                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  25904320                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7563072                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      111                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               25477                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25704                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25816                       # Per bank write bursts
system.physmem.perBankRdBursts::3               25781                       # Per bank write bursts
system.physmem.perBankRdBursts::4               25083                       # Per bank write bursts
system.physmem.perBankRdBursts::5               25010                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24709                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24576                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25196                       # Per bank write bursts
system.physmem.perBankRdBursts::9               25297                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25389                       # Per bank write bursts
system.physmem.perBankRdBursts::11              25021                       # Per bank write bursts
system.physmem.perBankRdBursts::12              24534                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25530                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25795                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25726                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7822                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7672                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8075                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7745                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7196                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7016                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6702                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6427                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7309                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6908                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7271                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7002                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7086                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7981                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7993                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7947                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
system.physmem.totGap                    1906043365500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  404755                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 118173                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    402408                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      2161                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        63                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1528                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2966                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     7248                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5892                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6862                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6013                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5964                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6987                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6497                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8431                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8614                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7309                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7697                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6993                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6015                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5600                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      258                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      212                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      186                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      286                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      259                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       39                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       24                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        64457                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      519.089377                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     317.985274                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     407.069012                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          14849     23.04%     23.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        11122     17.25%     40.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4951      7.68%     47.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3330      5.17%     53.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2494      3.87%     57.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1955      3.03%     60.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         4176      6.48%     66.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1342      2.08%     68.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        20238     31.40%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          64457                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5292                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        76.462207                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2902.463532                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           5289     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5292                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5292                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.326531                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.072850                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       20.540172                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23            4687     88.57%     88.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31              34      0.64%     89.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39              32      0.60%     89.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47              42      0.79%     90.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55             211      3.99%     94.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63               8      0.15%     94.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71              13      0.25%     94.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79              25      0.47%     95.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87             188      3.55%     99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95               3      0.06%     99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103              3      0.06%     99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111             3      0.06%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135             5      0.09%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143             1      0.02%     99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151             1      0.02%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159             1      0.02%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167             1      0.02%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175            11      0.21%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             9      0.17%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             3      0.06%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199             1      0.02%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207             3      0.06%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             5      0.09%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             2      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5292                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2635925000                       # Total ticks spent queuing
system.physmem.totMemAccLat               10223000000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2023220000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        6514.18                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  25264.18                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.59                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.97                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.59                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.97                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.36                       # Average write queue length when enqueuing
system.physmem.readRowHits                     362809                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     95530                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.66                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.84                       # Row buffer hit rate for writes
system.physmem.avgGap                      3644944.17                       # Average gap between requests
system.physmem.pageHitRate                      87.67                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  238124880                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  129929250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1576816800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                380084400                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           124493962320                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            67910384250                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1084060020000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1278789321900                       # Total energy per rank (pJ)
system.physmem_0.averagePower              670.910378                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   1803172860750                       # Time in different power states
system.physmem_0.memoryStateTime::REF     63647220000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     39230820500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  249170040                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  135955875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1579406400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                385540560                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           124493962320                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            68468592375                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1083570372000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1278882999570                       # Total energy per rank (pJ)
system.physmem_1.averagePower              670.959521                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   1802360809750                       # Time in different power states
system.physmem_1.memoryStateTime::REF     63647220000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     40042885250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                15006509                       # Number of BP lookups
system.cpu.branchPred.condPredicted          13016597                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            371031                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9764467                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 5201318                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             53.267813                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                  807808                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              31462                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9242631                       # DTB read hits
system.cpu.dtb.read_misses                      17134                       # DTB read misses
system.cpu.dtb.read_acv                           211                       # DTB read access violations
system.cpu.dtb.read_accesses                   765515                       # DTB read accesses
system.cpu.dtb.write_hits                     6388389                       # DTB write hits
system.cpu.dtb.write_misses                      2336                       # DTB write misses
system.cpu.dtb.write_acv                          160                       # DTB write access violations
system.cpu.dtb.write_accesses                  298460                       # DTB write accesses
system.cpu.dtb.data_hits                     15631020                       # DTB hits
system.cpu.dtb.data_misses                      19470                       # DTB misses
system.cpu.dtb.data_acv                           371                       # DTB access violations
system.cpu.dtb.data_accesses                  1063975                       # DTB accesses
system.cpu.itb.fetch_hits                     4014011                       # ITB hits
system.cpu.itb.fetch_misses                      6826                       # ITB misses
system.cpu.itb.fetch_acv                          642                       # ITB acv
system.cpu.itb.fetch_accesses                 4020837                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                        221712638                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    56145499                       # Number of instructions committed
system.cpu.committedOps                      56145499                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       2504937                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      5531                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   3590391693                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               3.948894                       # CPI: cycles per instruction
system.cpu.ipc                               0.253235                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6375                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     211539                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74805     40.93%     40.93% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     133      0.07%     41.01% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1904      1.04%     42.05% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  105907     57.95%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               182749                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73438     49.32%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      133      0.09%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1904      1.28%     50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73439     49.32%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                148914                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1837274169000     96.39%     96.39% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                83596500      0.00%     96.40% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               707455500      0.04%     96.43% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             67985922500      3.57%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1906051143500                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981726                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.693429                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.814855                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4174      2.17%      2.17% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl                175582     91.22%     93.43% # number of callpals executed
system.cpu.kern.callpal::rdps                    6807      3.54%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rti                     5130      2.67%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 192473                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5876                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2094                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1907                      
system.cpu.kern.mode_good::user                  1738                      
system.cpu.kern.mode_good::idle                   169                      
system.cpu.kern.mode_switch_good::kernel     0.324541                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.080707                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.392872                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        38725166000      2.03%      2.03% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           4529345500      0.24%      2.27% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1862796622000     97.73%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4175                       # number of times the context was actually changed
system.cpu.tickCycles                        84517271                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       137195367                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements           1395430                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.976766                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            13774435                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1395942                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs              9.867484                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         123981500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.976766                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999955                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999955                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          229                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          215                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          63669791                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         63669791                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data      7815717                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7815717                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      5576828                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        5576828                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       182828                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       182828                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       199029                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       199029                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      13392545                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         13392545                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     13392545                       # number of overall hits
system.cpu.dcache.overall_hits::total        13392545                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1201618                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1201618                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       575220                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       575220                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        17222                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        17222                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1776838                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1776838                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1776838                       # number of overall misses
system.cpu.dcache.overall_misses::total       1776838                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  46968047500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  46968047500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  33964546500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  33964546500                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    234897500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    234897500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  80932594000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  80932594000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  80932594000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  80932594000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      9017335                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9017335                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6152048                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6152048                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200050                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       200050                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       199029                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       199029                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15169383                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15169383                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15169383                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15169383                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.133256                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.133256                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093501                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.093501                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086088                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086088                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.117133                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.117133                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.117133                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.117133                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39087.336824                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 39087.336824                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59046.184938                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 59046.184938                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13639.385669                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13639.385669                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45548.662287                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 45548.662287                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45548.662287                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 45548.662287                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       838230                       # number of writebacks
system.cpu.dcache.writebacks::total            838230                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       127262                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       127262                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       270814                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       270814                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       398076                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       398076                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       398076                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       398076                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074356                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1074356                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304406                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       304406                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17219                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17219                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1378762                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1378762                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1378762                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1378762                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6934                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total         6934                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9624                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total         9624                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16558                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        16558                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43812536500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  43812536500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17276327500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  17276327500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    217413000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    217413000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  61088864000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  61088864000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  61088864000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  61088864000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1529368000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1529368000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2162483000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2162483000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3691851000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3691851000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119143                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119143                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049480                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049480                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086073                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086073                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090891                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.090891                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090891                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.090891                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40780.278139                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40780.278139                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56754.227906                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56754.227906                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12626.342993                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12626.342993                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.040664                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.040664                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.040664                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.040664                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220560.715316                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220560.715316                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224696.903574                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224696.903574                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222964.790434                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222964.790434                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           1460482                       # number of replacements
system.cpu.icache.tags.tagsinuse           508.105568                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            18950550                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1460993                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             12.971007                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       50119711500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   508.105568                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.992394                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.992394                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          406                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          21872887                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         21872887                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     18950553                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        18950553                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      18950553                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         18950553                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     18950553                       # number of overall hits
system.cpu.icache.overall_hits::total        18950553                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1461167                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1461167                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1461167                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1461167                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1461167                       # number of overall misses
system.cpu.icache.overall_misses::total       1461167                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  21009920000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  21009920000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  21009920000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  21009920000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  21009920000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  21009920000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     20411720                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     20411720                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     20411720                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     20411720                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     20411720                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     20411720                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071585                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.071585                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.071585                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.071585                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.071585                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.071585                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14378.862923                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14378.862923                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14378.862923                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14378.862923                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14378.862923                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14378.862923                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks      1460482                       # number of writebacks
system.cpu.icache.writebacks::total           1460482                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1461167                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1461167                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1461167                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1461167                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1461167                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1461167                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  19548753000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  19548753000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  19548753000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  19548753000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  19548753000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  19548753000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071585                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071585                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071585                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.071585                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071585                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.071585                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13378.862923                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13378.862923                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13378.862923                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13378.862923                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13378.862923                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13378.862923                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           339567                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65260.796606                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4999675                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           404729                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            12.353142                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       9687465000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 54046.207258                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  5724.432786                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  5490.156561                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.824680                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.087348                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.083773                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.995801                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          228                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          883                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5613                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2925                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55513                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         46397707                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        46397707                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks       838230                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       838230                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks      1459876                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total      1459876                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       187761                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       187761                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1444783                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      1444783                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       819335                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       819335                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst      1444783                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1007096                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2451879                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst      1444783                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1007096                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2451879                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data           17                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           17                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       116656                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       116656                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16324                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        16324                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       272208                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       272208                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst        16324                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       388864                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        405188                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        16324                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       388864                       # number of overall misses
system.cpu.l2cache.overall_misses::total       405188                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       397000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       397000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14841518500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  14841518500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2141533000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2141533000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  33675448500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  33675448500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2141533000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  48516967000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  50658500000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2141533000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  48516967000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  50658500000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks       838230                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       838230                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks      1459876                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total      1459876                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           21                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           21                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       304417                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       304417                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1461107                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      1461107                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1091543                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1091543                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      1461107                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1395960                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2857067                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1461107                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1395960                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2857067                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.809524                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.809524                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383211                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.383211                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.011172                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.011172                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.249379                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.249379                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.011172                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.278564                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.141820                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.011172                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.278564                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.141820                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23352.941176                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23352.941176                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127224.647682                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127224.647682                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131189.230581                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131189.230581                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123712.192515                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123712.192515                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131189.230581                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124765.900160                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 125024.679902                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131189.230581                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124765.900160                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 125024.679902                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        76661                       # number of writebacks
system.cpu.l2cache.writebacks::total            76661                       # number of writebacks
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           17                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           17                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116656                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       116656                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16324                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16324                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       272208                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       272208                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16324                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       388864                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       405188                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16324                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       388864                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       405188                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6934                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6934                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9624                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9624                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16558                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16558                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1175000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1175000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13674958500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13674958500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1978293000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1978293000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  30955575000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  30955575000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1978293000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  44630533500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  46608826500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1978293000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  44630533500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  46608826500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1442672500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1442672500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2051806000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2051806000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3494478500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3494478500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.809524                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.809524                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383211                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383211                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.011172                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.011172                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.249379                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249379                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.011172                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.278564                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.141820                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.011172                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.278564                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.141820                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69117.647059                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69117.647059                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117224.647682                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117224.647682                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121189.230581                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121189.230581                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113720.298448                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113720.298448                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121189.230581                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114771.574381                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115030.125522                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121189.230581                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114771.574381                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115030.125522                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208057.758869                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208057.758869                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213196.799667                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213196.799667                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211044.721585                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211044.721585                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      5713060                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2856101                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1990                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1247                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1247                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq           6934                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2559783                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq          9624                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp         9624                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       956411                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean      1460482                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       820279                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           21                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           21                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       304417                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       304417                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      1461167                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1091716                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4382756                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4220664                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8603420                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    186981696                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143041437                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          330023133                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      423201                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      3296691                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.001034                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.032145                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            3293281     99.90%     99.90% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               3410      0.10%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        3296691                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     5168333000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       291883                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    2192017465                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2105681496                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq                 7107                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7107                       # Transaction distribution
system.iobus.trans_dist::WriteReq               51176                       # Transaction distribution
system.iobus.trans_dist::WriteResp              51176                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5110                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6674                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        33116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  116566                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20440                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4194                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total        44381                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2705989                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              5419000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               786000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              186000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            14810500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             2308500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5936500                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy               98500                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           215720167                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            23492000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41685                       # number of replacements
system.iocache.tags.tagsinuse                1.290842                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1748612862000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.290842                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.080678                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.080678                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
system.iocache.tags.data_accesses              375525                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
system.iocache.overall_misses::total              173                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21917383                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21917383                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide   5244742784                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   5244742784                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide     21917383                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     21917383                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide     21917383                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     21917383                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 126690.075145                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126221.187524                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126221.187524                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 126690.075145                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 126690.075145                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 126690.075145                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 126690.075145                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs            10                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs            5                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13267383                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     13267383                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3165341974                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3165341974                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide     13267383                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     13267383                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide     13267383                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     13267383                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.848816                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.848816                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76690.075145                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76690.075145                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76690.075145                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76690.075145                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq                6934                       # Transaction distribution
system.membus.trans_dist::ReadResp             295622                       # Transaction distribution
system.membus.trans_dist::WriteReq               9624                       # Transaction distribution
system.membus.trans_dist::WriteResp              9624                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       118173                       # Transaction distribution
system.membus.trans_dist::CleanEvict           262241                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              175                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            116498                       # Transaction distribution
system.membus.trans_dist::ReadExResp           116498                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        288705                       # Transaction distribution
system.membus.trans_dist::BadAddressError           17                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33116                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1148657                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1181807                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83425                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        83425                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1265232                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44381                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30809664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30854045                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                33511773                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              433                       # Total snoops (count)
system.membus.snoop_fanout::samples            843910                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  843910    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              843910                       # Request fanout histogram
system.membus.reqLayer0.occupancy            29565500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1319337462                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer2.occupancy               22000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2159897250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy             943117                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped

---------- End Simulation Statistics   ----------