path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.887168                       # Number of seconds simulated
sim_ticks                                1887168480000                       # Number of ticks simulated
final_tick                               1887168480000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 181674                       # Simulator instruction rate (inst/s)
host_op_rate                                   181674                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6108559174                       # Simulator tick rate (ticks/s)
host_mem_usage                                 367844                       # Number of bytes of host memory used
host_seconds                                   308.94                       # Real time elapsed on the host
sim_insts                                    56125948                       # Number of instructions simulated
sim_ops                                      56125948                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst           1049920                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24850048                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             25900928                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1049920                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1049920                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7553472                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7553472                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              16405                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388282                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                404702                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          118023                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               118023                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               556347                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13167901                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               509                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13724757                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          556347                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             556347                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4002542                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4002542                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4002542                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              556347                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13167901                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide              509                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               17727299                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        404702                       # Number of read requests accepted
system.physmem.writeReqs                       118023                       # Number of write requests accepted
system.physmem.readBursts                      404702                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     118023                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 25893824                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7104                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7551936                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  25900928                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7553472                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      111                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          41707                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               25482                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25721                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25818                       # Per bank write bursts
system.physmem.perBankRdBursts::3               25768                       # Per bank write bursts
system.physmem.perBankRdBursts::4               25084                       # Per bank write bursts
system.physmem.perBankRdBursts::5               25019                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24651                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24525                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25293                       # Per bank write bursts
system.physmem.perBankRdBursts::9               25189                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25397                       # Per bank write bursts
system.physmem.perBankRdBursts::11              24988                       # Per bank write bursts
system.physmem.perBankRdBursts::12              24521                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25565                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25830                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25740                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7815                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7682                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8062                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7737                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7196                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7012                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6647                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6398                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7404                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6806                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7277                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6969                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7052                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8011                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7982                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7949                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          29                       # Number of times write queue was full causing retry
system.physmem.totGap                    1887159671500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  404702                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 118023                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    402323                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      2193                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        63                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1508                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1846                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6025                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6279                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6254                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7072                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7254                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     9744                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8775                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7502                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6817                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6604                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7036                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5787                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5493                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5524                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      184                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       94                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        63563                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      526.182842                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     320.768050                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     414.563237                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          14483     22.79%     22.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        10991     17.29%     40.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4893      7.70%     47.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3583      5.64%     53.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2419      3.81%     57.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1815      2.86%     60.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1455      2.29%     62.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1407      2.21%     64.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        22517     35.42%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          63563                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5279                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        76.639515                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2907.321691                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           5276     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5279                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5279                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.352529                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.833418                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       22.552708                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23            4665     88.37%     88.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31             223      4.22%     92.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39              69      1.31%     93.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47              13      0.25%     94.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55               7      0.13%     94.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63               8      0.15%     94.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71              10      0.19%     94.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79              11      0.21%     94.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87               9      0.17%     95.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95              33      0.63%     95.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103            187      3.54%     99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111             5      0.09%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119             2      0.04%     99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127             2      0.04%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135             7      0.13%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151             1      0.02%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159             1      0.02%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167             3      0.06%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175             3      0.06%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             6      0.11%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199             2      0.04%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223             1      0.02%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             9      0.17%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-295             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5279                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2194493000                       # Total ticks spent queuing
system.physmem.totMemAccLat                9780574250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2022955000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        5423.98                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  24173.98                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.72                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           4.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.72                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        4.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.87                       # Average write queue length when enqueuing
system.physmem.readRowHits                     363582                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     95445                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.86                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.87                       # Row buffer hit rate for writes
system.physmem.avgGap                      3610234.20                       # Average gap between requests
system.physmem.pageHitRate                      87.83                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  233596440                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  127458375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1576130400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                379397520                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           123260195760                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            60352481790                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1079356093500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1265285353785                       # Total energy per rank (pJ)
system.physmem_0.averagePower              670.470116                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   1795392967750                       # Time in different power states
system.physmem_0.memoryStateTime::REF     63016460000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     28752031000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  246939840                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  134739000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1579679400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                385236000                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           123260195760                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            61300664820                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1078524362250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1265431817070                       # Total energy per rank (pJ)
system.physmem_1.averagePower              670.547722                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   1794008459000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     63016460000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     30136553500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                14997890                       # Number of BP lookups
system.cpu.branchPred.condPredicted          13009268                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            370594                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9393435                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 5198350                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             55.340246                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                  807960                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              32049                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9241004                       # DTB read hits
system.cpu.dtb.read_misses                      17472                       # DTB read misses
system.cpu.dtb.read_acv                           211                       # DTB read access violations
system.cpu.dtb.read_accesses                   766036                       # DTB read accesses
system.cpu.dtb.write_hits                     6386411                       # DTB write hits
system.cpu.dtb.write_misses                      2301                       # DTB write misses
system.cpu.dtb.write_acv                          160                       # DTB write access violations
system.cpu.dtb.write_accesses                  298419                       # DTB write accesses
system.cpu.dtb.data_hits                     15627415                       # DTB hits
system.cpu.dtb.data_misses                      19773                       # DTB misses
system.cpu.dtb.data_acv                           371                       # DTB access violations
system.cpu.dtb.data_accesses                  1064455                       # DTB accesses
system.cpu.itb.fetch_hits                     4013195                       # ITB hits
system.cpu.itb.fetch_misses                      6857                       # ITB misses
system.cpu.itb.fetch_acv                          677                       # ITB acv
system.cpu.itb.fetch_accesses                 4020052                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                        182043546                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    56125948                       # Number of instructions committed
system.cpu.committedOps                      56125948                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       2502558                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      5565                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   3594204473                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               3.243483                       # CPI: cycles per instruction
system.cpu.ipc                               0.308311                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6375                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     211461                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74782     40.94%     40.94% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     41.01% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1902      1.04%     42.05% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  105860     57.95%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               182675                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73415     49.32%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1902      1.28%     50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73415     49.32%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                148863                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1834747397000     97.22%     97.22% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                80828500      0.00%     97.23% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               680298500      0.04%     97.26% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             51658959000      2.74%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1887167483000                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981720                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.693510                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.814906                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4172      2.17%      2.17% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl                175514     91.22%     93.43% # number of callpals executed
system.cpu.kern.callpal::rdps                    6805      3.54%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rti                     5127      2.66%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 192398                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5868                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1739                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1907                      
system.cpu.kern.mode_good::user                  1739                      
system.cpu.kern.mode_good::idle                   168                      
system.cpu.kern.mode_switch_good::kernel     0.324983                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.080114                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.393034                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        36501486500      1.93%      1.93% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           4115911000      0.22%      2.15% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1846550075500     97.85%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4173                       # number of times the context was actually changed
system.cpu.tickCycles                        86269078                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        95774468                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements           1395484                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.981722                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            13771544                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1395996                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs              9.865031                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          90850500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.981722                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999964                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999964                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          214                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          63656757                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         63656757                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data      7813939                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7813939                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      5575873                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        5575873                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       182717                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       182717                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       198981                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       198981                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      13389812                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         13389812                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     13389812                       # number of overall hits
system.cpu.dcache.overall_hits::total        13389812                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1201834                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1201834                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       574561                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       574561                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        17285                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        17285                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1776395                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1776395                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1776395                       # number of overall misses
system.cpu.dcache.overall_misses::total       1776395                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  32870602000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  32870602000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  22298477500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  22298477500                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    232185000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    232185000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  55169079500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  55169079500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  55169079500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  55169079500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      9015773                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9015773                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6150434                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6150434                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200002                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       200002                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       198981                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       198981                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15166207                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15166207                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15166207                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15166207                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.133303                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.133303                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093418                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.093418                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086424                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086424                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.117128                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.117128                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.117128                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.117128                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27350.367854                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 27350.367854                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38809.591149                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38809.591149                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13432.745155                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13432.745155                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31056.763558                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31056.763558                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31056.763558                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31056.763558                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       838310                       # number of writebacks
system.cpu.dcache.writebacks::total            838310                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       127379                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       127379                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       270264                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       270264                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       397643                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       397643                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       397643                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       397643                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074455                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1074455                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304297                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       304297                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17282                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17282                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1378752                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1378752                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1378752                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1378752                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9620                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total         9620                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16550                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        16550                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29867395000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  29867395000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11355989000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11355989000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    214737500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    214737500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  41223384000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  41223384000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  41223384000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  41223384000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1450621500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1450621500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2041589000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2041589000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3492210500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3492210500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119175                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119175                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049476                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049476                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086409                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086409                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090909                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.090909                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090909                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.090909                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27797.716051                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27797.716051                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37318.767520                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37318.767520                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12425.500521                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12425.500521                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29899.056538                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29899.056538                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29899.056538                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29899.056538                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209324.891775                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209324.891775                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212223.388773                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212223.388773                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211009.697885                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211009.697885                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           1459068                       # number of replacements
system.cpu.icache.tags.tagsinuse           509.460685                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            18942908                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1459579                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             12.978337                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       33609235500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   509.460685                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.995040                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.995040                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          400                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          21862421                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         21862421                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     18942911                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        18942911                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      18942911                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         18942911                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     18942911                       # number of overall hits
system.cpu.icache.overall_hits::total        18942911                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1459755                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1459755                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1459755                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1459755                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1459755                       # number of overall misses
system.cpu.icache.overall_misses::total       1459755                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  20136698000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  20136698000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  20136698000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  20136698000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  20136698000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  20136698000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     20402666                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     20402666                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     20402666                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     20402666                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     20402666                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     20402666                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071547                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.071547                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.071547                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.071547                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.071547                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.071547                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13794.573747                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13794.573747                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13794.573747                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13794.573747                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13794.573747                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13794.573747                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1459755                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1459755                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1459755                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1459755                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1459755                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1459755                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  18676943000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  18676943000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  18676943000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  18676943000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  18676943000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  18676943000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071547                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071547                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071547                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.071547                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071547                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.071547                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12794.573747                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12794.573747                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12794.573747                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12794.573747                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12794.573747                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12794.573747                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           339197                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65316.861882                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4997134                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           404357                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            12.358223                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       6286116000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 54372.711085                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  5866.673832                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  5077.476965                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.829662                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.089518                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.077476                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.996656                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65160                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          228                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1416                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5171                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2816                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55529                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994263                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         46375417                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        46375417                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks       838310                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       838310                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       187763                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       187763                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1443287                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      1443287                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       819540                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       819540                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst      1443287                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1007303                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2450590                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst      1443287                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1007303                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2450590                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data           17                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           17                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       116544                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       116544                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16406                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        16406                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       272166                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       272166                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst        16406                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       388710                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        405116                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        16406                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       388710                       # number of overall misses
system.cpu.l2cache.overall_misses::total       405116                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       253000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       253000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8923529500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8923529500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1314713000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   1314713000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  19729862500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  19729862500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1314713000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  28653392000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  29968105000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1314713000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  28653392000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  29968105000                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks       838310                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       838310                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           21                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           21                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       304307                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       304307                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1459693                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      1459693                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1091706                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1091706                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      1459693                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1396013                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2855706                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1459693                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1396013                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2855706                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.809524                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.809524                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.382982                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.382982                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.011239                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.011239                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.249303                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.249303                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.011239                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.278443                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.141862                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.011239                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.278443                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.141862                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14882.352941                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14882.352941                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76567.901393                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76567.901393                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80136.108741                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80136.108741                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72492.017739                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72492.017739                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80136.108741                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73714.059324                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73974.133335                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80136.108741                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73714.059324                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73974.133335                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        76511                       # number of writebacks
system.cpu.l2cache.writebacks::total            76511                       # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          317                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total          317                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           17                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           17                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116544                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       116544                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16406                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16406                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       272166                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       272166                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16406                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       388710                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       405116                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16406                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       388710                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       405116                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9620                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9620                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16550                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16550                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       453499                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       453499                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7758089500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7758089500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1150653000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1150653000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  17010167000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  17010167000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1150653000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  24768256500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  25918909500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1150653000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  24768256500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  25918909500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1363977000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1363977000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1930958000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1930958000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3294935000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3294935000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.809524                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.809524                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.382982                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.382982                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.011239                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.011239                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.249303                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249303                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.011239                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.278443                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.141862                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.011239                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.278443                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.141862                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26676.411765                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26676.411765                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66567.901393                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66567.901393                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70136.108741                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70136.108741                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62499.235761                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62499.235761                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70136.108741                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63719.113221                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63978.982563                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70136.108741                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63719.113221                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63978.982563                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196822.077922                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196822.077922                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200723.284823                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200723.284823                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199089.728097                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199089.728097                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2558531                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq          9620                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp         9620                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       956362                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      2277135                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           21                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           21                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       304307                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       304307                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      1459755                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1091879                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError           16                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4377903                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4219455                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8597358                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     93420352                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143049956                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          236470308                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      422854                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      6149527                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.068727                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.252989                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1            5726891     93.13%     93.13% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2             422636      6.87%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        6149527                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     3706565999                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    2189850563                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2105755497                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
system.iobus.trans_dist::WriteReq               51172                       # Transaction distribution
system.iobus.trans_dist::WriteResp              51172                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5096                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        33100                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  116550                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20384                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total        44324                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2705932                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              4707000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13484000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           216043265                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            23480000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41685                       # number of replacements
system.iocache.tags.tagsinuse                1.302220                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1729987199000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.302220                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.081389                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.081389                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
system.iocache.tags.data_accesses              375525                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
system.iocache.overall_misses::total              173                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21637883                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21637883                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide   4908791382                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4908791382                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide     21637883                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     21637883                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide     21637883                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     21637883                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125074.468208                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118136.103725                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118136.103725                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125074.468208                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125074.468208                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             6                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs            3                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12987883                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12987883                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2831191382                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2831191382                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide     12987883                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     12987883                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide     12987883                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     12987883                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68136.103725                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68136.103725                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75074.468208                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75074.468208                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
system.membus.trans_dist::ReadResp             295659                       # Transaction distribution
system.membus.trans_dist::WriteReq               9620                       # Transaction distribution
system.membus.trans_dist::WriteResp              9620                       # Transaction distribution
system.membus.trans_dist::Writeback            118023                       # Transaction distribution
system.membus.trans_dist::CleanEvict           262178                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              157                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             157                       # Transaction distribution
system.membus.trans_dist::ReadExReq            116404                       # Transaction distribution
system.membus.trans_dist::ReadExResp           116404                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        288745                       # Transaction distribution
system.membus.trans_dist::BadAddressError           16                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33100                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1148635                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           32                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1181767                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124817                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       124817                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1306584                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44324                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30796672                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30840996                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                33498724                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              433                       # Total snoops (count)
system.membus.snoop_fanout::samples            843798                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  843798    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              843798                       # Request fanout histogram
system.membus.reqLayer0.occupancy            29290000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1318757186                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer2.occupancy               20500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2160035845                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy           72019946                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped

---------- End Simulation Statistics   ----------