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|
---------- Begin Simulation Statistics ----------
sim_seconds 1.887184 # Number of seconds simulated
sim_ticks 1887184463000 # Number of ticks simulated
final_tick 1887184463000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 272052 # Simulator instruction rate (inst/s)
host_op_rate 272052 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 9147074399 # Simulator tick rate (ticks/s)
host_mem_usage 373996 # Number of bytes of host memory used
host_seconds 206.32 # Real time elapsed on the host
sim_insts 56128524 # Number of instructions simulated
sim_ops 56128524 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 1052352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 25913536 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1052352 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1052352 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7558400 # Number of bytes written to this memory
system.physmem.bytes_written::total 7558400 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 16443 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 388441 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 404899 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 118100 # Number of write requests responded to by this memory
system.physmem.num_writes::total 118100 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 557631 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 13173182 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13731321 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 557631 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 557631 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4005120 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4005120 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4005120 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 557631 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 13173182 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 17736441 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 404899 # Number of read requests accepted
system.physmem.writeReqs 159652 # Number of write requests accepted
system.physmem.readBursts 404899 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 159652 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 25907328 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue
system.physmem.bytesWritten 8555840 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 25913536 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 10217728 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 25937 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 159 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 25492 # Per bank write bursts
system.physmem.perBankRdBursts::1 25732 # Per bank write bursts
system.physmem.perBankRdBursts::2 25844 # Per bank write bursts
system.physmem.perBankRdBursts::3 25788 # Per bank write bursts
system.physmem.perBankRdBursts::4 25096 # Per bank write bursts
system.physmem.perBankRdBursts::5 25019 # Per bank write bursts
system.physmem.perBankRdBursts::6 24724 # Per bank write bursts
system.physmem.perBankRdBursts::7 24556 # Per bank write bursts
system.physmem.perBankRdBursts::8 25196 # Per bank write bursts
system.physmem.perBankRdBursts::9 25300 # Per bank write bursts
system.physmem.perBankRdBursts::10 25394 # Per bank write bursts
system.physmem.perBankRdBursts::11 24993 # Per bank write bursts
system.physmem.perBankRdBursts::12 24525 # Per bank write bursts
system.physmem.perBankRdBursts::13 25570 # Per bank write bursts
system.physmem.perBankRdBursts::14 25834 # Per bank write bursts
system.physmem.perBankRdBursts::15 25739 # Per bank write bursts
system.physmem.perBankWrBursts::0 8904 # Per bank write bursts
system.physmem.perBankWrBursts::1 8550 # Per bank write bursts
system.physmem.perBankWrBursts::2 9134 # Per bank write bursts
system.physmem.perBankWrBursts::3 8817 # Per bank write bursts
system.physmem.perBankWrBursts::4 8179 # Per bank write bursts
system.physmem.perBankWrBursts::5 8016 # Per bank write bursts
system.physmem.perBankWrBursts::6 7555 # Per bank write bursts
system.physmem.perBankWrBursts::7 7380 # Per bank write bursts
system.physmem.perBankWrBursts::8 8271 # Per bank write bursts
system.physmem.perBankWrBursts::9 7751 # Per bank write bursts
system.physmem.perBankWrBursts::10 8147 # Per bank write bursts
system.physmem.perBankWrBursts::11 7871 # Per bank write bursts
system.physmem.perBankWrBursts::12 8181 # Per bank write bursts
system.physmem.perBankWrBursts::13 9046 # Per bank write bursts
system.physmem.perBankWrBursts::14 9003 # Per bank write bursts
system.physmem.perBankWrBursts::15 8880 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 48 # Number of times write queue was full causing retry
system.physmem.totGap 1887175688500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 404899 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 159652 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 402512 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 2208 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1116 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1878 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5779 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5566 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5580 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5702 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5645 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5477 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5437 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5641 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 5825 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 6756 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 6161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 6363 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7635 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6502 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6461 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5991 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1224 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 780 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1179 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 1384 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1265 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 883 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1555 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1873 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1560 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1827 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1983 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1921 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 2157 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 2541 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 2774 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 2169 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 1666 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 1329 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 1241 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 764 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 448 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 299 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 232 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 261 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 149 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 147 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 64790 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 531.921099 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 325.032687 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 415.479352 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 14695 22.68% 22.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 10956 16.91% 39.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5460 8.43% 48.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3096 4.78% 52.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2482 3.83% 56.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1882 2.90% 59.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1491 2.30% 61.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1429 2.21% 64.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 23299 35.96% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 64790 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4900 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 82.608776 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 3017.174786 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191 4897 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 4900 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4900 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 27.282653 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.334547 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 63.863816 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-31 4662 95.14% 95.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-63 56 1.14% 96.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-95 12 0.24% 96.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-127 6 0.12% 96.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-159 26 0.53% 97.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-191 25 0.51% 97.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-223 16 0.33% 98.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-255 3 0.06% 98.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-287 4 0.08% 98.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-319 8 0.16% 98.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-351 21 0.43% 98.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-383 20 0.41% 99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-415 2 0.04% 99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::448-479 6 0.12% 99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-511 7 0.14% 99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-543 9 0.18% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-575 6 0.12% 99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::672-703 3 0.06% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::704-735 7 0.14% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1088-1119 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4900 # Writes before turning the bus around for reads
system.physmem.totQLat 2145936500 # Total ticks spent queuing
system.physmem.totMemAccLat 9735974000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2024010000 # Total ticks spent in databus transfers
system.physmem.avgQLat 5301.20 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 24051.20 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 4.53 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 5.41 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.14 # Data bus utilization in percentage
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 25.13 # Average write queue length when enqueuing
system.physmem.readRowHits 363622 # Number of row buffer hits during reads
system.physmem.writeRowHits 110075 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 82.32 # Row buffer hit rate for writes
system.physmem.avgGap 3342790.44 # Average gap between requests
system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 238979160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 130395375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1577557800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 431146800 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 60577818750 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1079167773000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1265384883765 # Total energy per rank (pJ)
system.physmem_0.averagePower 670.517324 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 1795079851716 # Time in different power states
system.physmem_0.memoryStateTime::REF 63016980000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 29080199534 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 250833240 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 136863375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1579897800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 435132000 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 61600331205 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1078270840500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1265535111000 # Total energy per rank (pJ)
system.physmem_1.averagePower 670.596923 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1793587329216 # Time in different power states
system.physmem_1.memoryStateTime::REF 63016980000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 30572735784 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 15007833 # Number of BP lookups
system.cpu.branchPred.condPredicted 13016266 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 375462 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9968116 # Number of BTB lookups
system.cpu.branchPred.BTBHits 5203851 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 52.204960 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 809053 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 32834 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 9242504 # DTB read hits
system.cpu.dtb.read_misses 17824 # DTB read misses
system.cpu.dtb.read_acv 211 # DTB read access violations
system.cpu.dtb.read_accesses 766347 # DTB read accesses
system.cpu.dtb.write_hits 6386002 # DTB write hits
system.cpu.dtb.write_misses 2322 # DTB write misses
system.cpu.dtb.write_acv 159 # DTB write access violations
system.cpu.dtb.write_accesses 298454 # DTB write accesses
system.cpu.dtb.data_hits 15628506 # DTB hits
system.cpu.dtb.data_misses 20146 # DTB misses
system.cpu.dtb.data_acv 370 # DTB access violations
system.cpu.dtb.data_accesses 1064801 # DTB accesses
system.cpu.itb.fetch_hits 4019475 # ITB hits
system.cpu.itb.fetch_misses 6849 # ITB misses
system.cpu.itb.fetch_acv 693 # ITB acv
system.cpu.itb.fetch_accesses 4026324 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.numCycles 180833533 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 56128524 # Number of instructions committed
system.cpu.committedOps 56128524 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2493054 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 5493 # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles 3593535393 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi 3.221776 # CPI: cycles per instruction
system.cpu.ipc 0.310388 # IPC: instructions per cycle
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
system.cpu.kern.inst.hwrei 211489 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74799 40.94% 40.94% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 105874 57.95% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 182705 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73432 49.32% 49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73432 49.32% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 148896 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1834551053500 97.21% 97.21% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 80458000 0.00% 97.22% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 676198500 0.04% 97.25% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 51875765500 2.75% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1887183475500 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.814953 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx 4170 2.17% 2.17% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl 175546 91.23% 93.43% # number of callpals executed
system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.callpal::total 192427 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5873 # number of protection mode switches
system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2089 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1906
system.cpu.kern.mode_good::user 1739
system.cpu.kern.mode_good::idle 167
system.cpu.kern.mode_switch_good::kernel 0.324536 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.392949 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 36591863000 1.94% 1.94% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 4134622500 0.22% 2.16% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1846456980000 97.84% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4171 # number of times the context was actually changed
system.cpu.tickCycles 84552243 # Number of cycles that the object actually ticked
system.cpu.idleCycles 96281290 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 1395323 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.981737 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 13774277 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1395835 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 9.868127 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 90985250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.981737 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 63660728 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 63660728 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 7815432 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7815432 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 5576995 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 5576995 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 182818 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 182818 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 198995 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 198995 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 13392427 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 13392427 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 13392427 # number of overall hits
system.cpu.dcache.overall_hits::total 13392427 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1201537 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1201537 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 573249 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 573249 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17197 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 17197 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1774786 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1774786 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1774786 # number of overall misses
system.cpu.dcache.overall_misses::total 1774786 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 32999736250 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 32999736250 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 22461890056 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 22461890056 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230671750 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 230671750 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 55461626306 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 55461626306 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 55461626306 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 55461626306 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 9016969 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9016969 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6150244 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6150244 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200015 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 200015 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 198995 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 198995 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::total 15167213 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::total 15167213 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.133253 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093208 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.093208 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085979 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085979 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.demand_miss_rate::total 0.117015 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::total 0.117015 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.602630 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.602630 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39183.478830 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39183.478830 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.487818 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.487818 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31249.754227 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31249.754227 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31249.754227 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31249.754227 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.writebacks::total 838171 # number of writebacks
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system.cpu.dcache.WriteReq_mshr_hits::total 268996 # number of WriteReq MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 396104 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::total 1074429 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 304253 # number of WriteReq MSHR misses
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system.cpu.dcache.LoadLockedReq_mshr_misses::total 17194 # number of LoadLockedReq MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 1378682 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9619 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 9619 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16549 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 16549 # number of overall MSHR uncacheable misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 29341393000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11237642841 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11237642841 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204691750 # number of LoadLockedReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 40579035841 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 40579035841 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433304500 # number of ReadReq MSHR uncacheable cycles
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2018260000 # number of WriteReq MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency::total 3451564500 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049470 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27308.824501 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27308.824501 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36935.191571 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36935.191571 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11904.835989 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.835989 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29433.209283 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29433.209283 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29433.209283 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29433.209283 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206826.046176 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206826.046176 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209820.147624 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209820.147624 # average WriteReq mshr uncacheable latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208566.348420 # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1459080 # number of replacements
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system.cpu.icache.tags.sampled_refs 1459591 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 12.995623 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 33851094250 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.age_task_id_blocks_1024::2 399 # Occupied blocks per task id
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system.cpu.icache.tags.tag_accesses 21887836 # Number of tag accesses
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system.cpu.icache.overall_hits::total 18968298 # number of overall hits
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system.cpu.icache.overall_misses::total 1459769 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 20155075408 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 20155075408 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::total 20155075408 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::total 20428067 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.overall_mshr_miss_latency::total 17958174092 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12302.065664 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12302.065664 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12302.065664 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12302.065664 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12302.065664 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12302.065664 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 339394 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65314.689332 # Cycle average of tags in use
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system.cpu.l2cache.tags.sampled_refs 404554 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.warmup_cycle 6335415750 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5172 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2816 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55531 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994263 # Percentage of cache occupancy per task id
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system.cpu.l2cache.UpgradeReq_miss_latency::total 253997 # number of UpgradeReq miss cycles
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system.cpu.l2cache.ReadReq_accesses::total 2551299 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 838171 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 838171 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 24 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 24 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304257 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 304257 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1459704 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1395852 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2855556 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1459704 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1395852 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2855556 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.011265 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.249369 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.113140 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.833333 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.833333 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383426 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383426 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011265 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.278590 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.141939 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011265 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.278590 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.141939 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80449.069569 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72533.430991 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72984.367963 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12699.850000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12699.850000 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76800.150943 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76800.150943 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80449.069569 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73813.436004 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74082.650387 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80449.069569 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73813.436004 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74082.650387 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 76588 # number of writebacks
system.cpu.l2cache.writebacks::total 76588 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16444 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272210 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 288654 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 20 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116660 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 116660 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 16444 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 388870 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 405314 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16444 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 388870 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 405314 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9619 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9619 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16549 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16549 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1116950000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16343076250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17460026250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 455517 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 455517 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7501019891 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7501019891 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1116950000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23844096141 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 24961046141 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1116950000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23844096141 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 24961046141 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336266500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336266500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893212500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893212500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229479000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229479000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249369 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113140 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.833333 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.833333 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383426 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383426 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278590 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.141939 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278590 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.141939 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67924.470932 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60038.485912 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60487.733584 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22775.850000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22775.850000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64298.130387 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64298.130387 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67924.470932 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61316.368300 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61584.465725 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67924.470932 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61316.368300 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61584.465725 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192823.448773 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192823.448773 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196820.095644 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196820.095644 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195146.474107 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195146.474107 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 2558467 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2558434 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 838171 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41592 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 304257 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 304257 # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2919473 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663177 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 6582650 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93421056 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143030748 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 236451804 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 41986 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 3752130 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.011131 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.104915 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 3710365 98.89% 98.89% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 41765 1.11% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 3752130 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2698163499 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 2193277408 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2194687409 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
system.iobus.trans_dist::WriteReq 51171 # Transaction distribution
system.iobus.trans_dist::WriteResp 9619 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5094 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 33098 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 116548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20376 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 44316 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2705924 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 4705000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 242092694 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41685 # number of replacements
system.iocache.tags.tagsinuse 1.302259 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 1729989085000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 1.302259 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.081391 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.081391 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
system.iocache.tags.data_accesses 375525 # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
system.iocache.overall_misses::total 173 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775999311 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 8775999311 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles
system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211205.220230 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 211205.220230 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 73059 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 10002 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 7.304439 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6615295311 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6615295311 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159205.220230 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159205.220230 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 295757 # Transaction distribution
system.membus.trans_dist::ReadResp 295741 # Transaction distribution
system.membus.trans_dist::WriteReq 9619 # Transaction distribution
system.membus.trans_dist::WriteResp 9619 # Transaction distribution
system.membus.trans_dist::Writeback 118100 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
system.membus.trans_dist::UpgradeReq 161 # Transaction distribution
system.membus.trans_dist::UpgradeResp 161 # Transaction distribution
system.membus.trans_dist::ReadExReq 116519 # Transaction distribution
system.membus.trans_dist::ReadExResp 116519 # Transaction distribution
system.membus.trans_dist::BadAddressError 16 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886949 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920079 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1044883 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30814208 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30858524 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 36175580 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 433 # Total snoops (count)
system.membus.snoop_fanout::samples 581756 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 581756 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 581756 # Request fanout histogram
system.membus.reqLayer0.occupancy 30242500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1230317312 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer2.occupancy 21000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 2160772841 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
---------- End Simulation Statistics ----------
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