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|
---------- Begin Simulation Statistics ----------
sim_seconds 1.884236 # Number of seconds simulated
sim_ticks 1884235597000 # Number of ticks simulated
final_tick 1884235597000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 167027 # Simulator instruction rate (inst/s)
host_op_rate 167027 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5607682389 # Simulator tick rate (ticks/s)
host_mem_usage 359752 # Number of bytes of host memory used
host_seconds 336.01 # Real time elapsed on the host
sim_insts 56122640 # Number of instructions simulated
sim_ops 56122640 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 1053184 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24861632 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 25915776 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1053184 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1053184 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7561856 # Number of bytes written to this memory
system.physmem.bytes_written::total 7561856 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 16456 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 388463 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 404934 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 118154 # Number of write requests responded to by this memory
system.physmem.num_writes::total 118154 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 558945 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 13194545 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13754000 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 558945 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 558945 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4013222 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4013222 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4013222 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 558945 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 13194545 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 17767222 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 404934 # Number of read requests accepted
system.physmem.writeReqs 159706 # Number of write requests accepted
system.physmem.readBursts 404934 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 159706 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 25910208 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 5568 # Total number of bytes read from write queue
system.physmem.bytesWritten 10081344 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 25915776 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 10221184 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 87 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2165 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 25481 # Per bank write bursts
system.physmem.perBankRdBursts::1 25742 # Per bank write bursts
system.physmem.perBankRdBursts::2 25839 # Per bank write bursts
system.physmem.perBankRdBursts::3 25784 # Per bank write bursts
system.physmem.perBankRdBursts::4 25228 # Per bank write bursts
system.physmem.perBankRdBursts::5 24953 # Per bank write bursts
system.physmem.perBankRdBursts::6 24817 # Per bank write bursts
system.physmem.perBankRdBursts::7 24560 # Per bank write bursts
system.physmem.perBankRdBursts::8 25102 # Per bank write bursts
system.physmem.perBankRdBursts::9 25274 # Per bank write bursts
system.physmem.perBankRdBursts::10 25530 # Per bank write bursts
system.physmem.perBankRdBursts::11 24856 # Per bank write bursts
system.physmem.perBankRdBursts::12 24523 # Per bank write bursts
system.physmem.perBankRdBursts::13 25574 # Per bank write bursts
system.physmem.perBankRdBursts::14 25845 # Per bank write bursts
system.physmem.perBankRdBursts::15 25739 # Per bank write bursts
system.physmem.perBankWrBursts::0 10323 # Per bank write bursts
system.physmem.perBankWrBursts::1 10094 # Per bank write bursts
system.physmem.perBankWrBursts::2 10597 # Per bank write bursts
system.physmem.perBankWrBursts::3 9998 # Per bank write bursts
system.physmem.perBankWrBursts::4 9794 # Per bank write bursts
system.physmem.perBankWrBursts::5 9430 # Per bank write bursts
system.physmem.perBankWrBursts::6 9122 # Per bank write bursts
system.physmem.perBankWrBursts::7 8746 # Per bank write bursts
system.physmem.perBankWrBursts::8 9866 # Per bank write bursts
system.physmem.perBankWrBursts::9 8965 # Per bank write bursts
system.physmem.perBankWrBursts::10 9841 # Per bank write bursts
system.physmem.perBankWrBursts::11 9391 # Per bank write bursts
system.physmem.perBankWrBursts::12 9895 # Per bank write bursts
system.physmem.perBankWrBursts::13 10602 # Per bank write bursts
system.physmem.perBankWrBursts::14 10396 # Per bank write bursts
system.physmem.perBankWrBursts::15 10461 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 1884226862500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 404934 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 159706 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 402541 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 2225 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1926 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 4012 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 8122 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 9238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 10015 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 10844 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 11276 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 12213 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 11798 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 11832 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 10697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9984 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8432 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6754 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6326 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6180 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6119 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 327 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 291 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 258 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 243 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 182 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 190 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 205 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 192 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 152 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 90 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 65747 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 547.425008 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 336.336786 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 417.790126 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 14590 22.19% 22.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 10813 16.45% 38.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4856 7.39% 46.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3188 4.85% 50.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2531 3.85% 54.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1959 2.98% 57.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1455 2.21% 59.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1675 2.55% 62.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 24680 37.54% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 65747 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5741 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 70.518028 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2788.038880 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191 5738 99.95% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5741 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5741 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 27.437903 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 20.774518 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 33.753883 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 4686 81.62% 81.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 175 3.05% 84.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 305 5.31% 89.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 60 1.05% 91.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 91 1.59% 92.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 55 0.96% 93.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71 13 0.23% 93.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 10 0.17% 93.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 19 0.33% 94.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95 5 0.09% 94.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 16 0.28% 94.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111 10 0.17% 94.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 11 0.19% 95.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127 3 0.05% 95.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 17 0.30% 95.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 40 0.70% 96.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151 20 0.35% 96.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159 16 0.28% 96.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167 94 1.64% 98.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175 33 0.57% 98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 16 0.28% 99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191 17 0.30% 99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199 9 0.16% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207 5 0.09% 99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215 3 0.05% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223 3 0.05% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231 2 0.03% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239 2 0.03% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247 2 0.03% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255 1 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263 2 0.03% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5741 # Writes before turning the bus around for reads
system.physmem.totQLat 2143675250 # Total ticks spent queuing
system.physmem.totMemAccLat 9734556500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2024235000 # Total ticks spent in databus transfers
system.physmem.avgQLat 5295.03 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 24045.03 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.75 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 5.35 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.75 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 5.42 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 25.52 # Average write queue length when enqueuing
system.physmem.readRowHits 364210 # Number of row buffer hits during reads
system.physmem.writeRowHits 132411 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.96 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 84.05 # Row buffer hit rate for writes
system.physmem.avgGap 3337041.06 # Average gap between requests
system.physmem.pageHitRate 88.31 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 243152280 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 132672375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1578751200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 506113920 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 123068977200 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 59789504475 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1078093355250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1263412526700 # Total energy per rank (pJ)
system.physmem_0.averagePower 670.517914 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 1793297401750 # Time in different power states
system.physmem_0.memoryStateTime::REF 62918700000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 28017727000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 253895040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 138534000 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1579055400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 514622160 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 123068977200 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 60612218820 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1077371684250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1263538986870 # Total energy per rank (pJ)
system.physmem_1.averagePower 670.585024 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1792097761500 # Time in different power states
system.physmem_1.memoryStateTime::REF 62918700000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 29217381000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 15006303 # Number of BP lookups
system.cpu.branchPred.condPredicted 13014667 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 375459 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9787101 # Number of BTB lookups
system.cpu.branchPred.BTBHits 5202858 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 53.160359 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 808926 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 32598 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 9241313 # DTB read hits
system.cpu.dtb.read_misses 17796 # DTB read misses
system.cpu.dtb.read_acv 211 # DTB read access violations
system.cpu.dtb.read_accesses 766310 # DTB read accesses
system.cpu.dtb.write_hits 6385986 # DTB write hits
system.cpu.dtb.write_misses 2327 # DTB write misses
system.cpu.dtb.write_acv 160 # DTB write access violations
system.cpu.dtb.write_accesses 298447 # DTB write accesses
system.cpu.dtb.data_hits 15627299 # DTB hits
system.cpu.dtb.data_misses 20123 # DTB misses
system.cpu.dtb.data_acv 371 # DTB access violations
system.cpu.dtb.data_accesses 1064757 # DTB accesses
system.cpu.itb.fetch_hits 4016976 # ITB hits
system.cpu.itb.fetch_misses 6883 # ITB misses
system.cpu.itb.fetch_acv 674 # ITB acv
system.cpu.itb.fetch_accesses 4023859 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.numCycles 175257245 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 56122640 # Number of instructions committed
system.cpu.committedOps 56122640 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2496382 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 5595 # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles 3593213949 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi 3.122755 # CPI: cycles per instruction
system.cpu.ipc 0.320230 # IPC: instructions per cycle
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed
system.cpu.kern.inst.hwrei 211475 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74790 40.94% 40.94% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 105864 57.95% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 182686 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73423 49.32% 49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73423 49.32% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 148878 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1833807390500 97.32% 97.32% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 80545000 0.00% 97.33% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 673176000 0.04% 97.36% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 49673506000 2.64% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1884234617500 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31 0.693560 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.814939 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl 175527 91.22% 93.43% # number of callpals executed
system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.callpal::total 192413 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5870 # number of protection mode switches
system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1910
system.cpu.kern.mode_good::user 1740
system.cpu.kern.mode_good::idle 170
system.cpu.kern.mode_switch_good::kernel 0.325383 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.393490 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 36258202500 1.92% 1.92% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 4079939000 0.22% 2.14% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1843896466000 97.86% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
system.cpu.tickCycles 84474734 # Number of cycles that the object actually ticked
system.cpu.idleCycles 90782511 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 1395383 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.982334 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 13772439 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1395895 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 9.866386 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 86820250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.982334 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 63656284 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 63656284 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 7814297 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7814297 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 5576378 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 5576378 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 182732 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 182732 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 198999 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 198999 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 13390675 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 13390675 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 13390675 # number of overall hits
system.cpu.dcache.overall_hits::total 13390675 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1201640 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1201640 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 573763 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 573763 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17288 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 17288 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1775403 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1775403 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1775403 # number of overall misses
system.cpu.dcache.overall_misses::total 1775403 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31034654250 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 31034654250 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20679395543 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 20679395543 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 231275750 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 231275750 # number of LoadLockedReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 51714049793 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::total 51714049793 # number of overall miss cycles
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system.cpu.dcache.LoadLockedReq_accesses::total 200020 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 198999 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25826.915091 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 25826.915091 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 36041.702834 # average WriteReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13377.819875 # average LoadLockedReq miss latency
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system.cpu.dcache.overall_avg_miss_latency::total 29128.062639 # average overall miss latency
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system.cpu.dcache.overall_mshr_misses::total 1378648 # number of overall MSHR misses
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system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196537750 # number of LoadLockedReq MSHR miss cycles
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25054.298697 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33683.251706 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33683.251706 # average WriteReq mshr miss latency
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system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11370.422332 # average LoadLockedReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26958.761117 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11718.691332 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11718.691332 # average overall mshr miss latency
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system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5137 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 # Occupied blocks per task id
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system.cpu.l2cache.UpgradeReq_miss_latency::total 214497 # number of UpgradeReq miss cycles
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system.cpu.l2cache.overall_miss_latency::total 26985130611 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1460096 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1091627 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2551723 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 838265 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 838265 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304285 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 304285 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1460096 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1395912 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2856008 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1460096 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1395912 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2856008 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.011271 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.249365 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.113128 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.809524 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383443 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383443 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011271 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.278592 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.141928 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011271 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.278592 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.141928 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72775.931215 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65106.454848 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 65543.688143 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12617.470588 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12617.470588 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69119.344261 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69119.344261 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72775.931215 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66310.414541 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 66572.913111 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72775.931215 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66310.414541 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 66572.913111 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 76642 # number of writebacks
system.cpu.l2cache.writebacks::total 76642 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16457 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272214 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 288671 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116676 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 116676 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 16457 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 388890 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 405347 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16457 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 388890 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 405347 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 990967000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14320677500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15311644500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271014 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271014 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6596786889 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6596786889 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 990967000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20917464389 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 21908431389 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 990967000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20917464389 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 21908431389 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333789500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333789500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1887480500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887480500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3221270000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221270000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011271 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249365 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113128 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383443 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383443 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011271 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278592 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.141928 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011271 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278592 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.141928 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60215.531385 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52608.159389 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53041.852143 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15942 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56539.364471 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56539.364471 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60215.531385 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53787.611893 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54048.584026 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60215.531385 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53787.611893 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54048.584026 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 2558889 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2558856 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 838265 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 304285 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 304285 # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2920255 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663385 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 6583640 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93446144 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143040604 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 236486748 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 41944 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 3736082 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.011168 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.105088 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 3694357 98.88% 98.88% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 41725 1.12% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 3736082 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2698528498 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 2193867384 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2194759654 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
system.iobus.trans_dist::WriteReq 51171 # Transaction distribution
system.iobus.trans_dist::WriteResp 9619 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5094 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 33098 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 116548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20376 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 44316 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2705924 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 4705000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 406197789 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41685 # number of replacements
system.iocache.tags.tagsinuse 1.296028 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 1728025570000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 1.296028 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.081002 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.081002 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
system.iocache.tags.data_accesses 375525 # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
system.iocache.overall_misses::total 173 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635920906 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 13635920906 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles
system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328165.212409 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 328165.212409 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 206267 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 23556 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 8.756453 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11475216906 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11475216906 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276165.212409 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276165.212409 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 295774 # Transaction distribution
system.membus.trans_dist::ReadResp 295758 # Transaction distribution
system.membus.trans_dist::WriteReq 9619 # Transaction distribution
system.membus.trans_dist::WriteResp 9619 # Transaction distribution
system.membus.trans_dist::Writeback 118154 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
system.membus.trans_dist::UpgradeReq 156 # Transaction distribution
system.membus.trans_dist::UpgradeResp 156 # Transaction distribution
system.membus.trans_dist::ReadExReq 116537 # Transaction distribution
system.membus.trans_dist::ReadExResp 116537 # Transaction distribution
system.membus.trans_dist::BadAddressError 16 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887063 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920193 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1044997 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30819904 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30864220 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 36181276 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 433 # Total snoops (count)
system.membus.snoop_fanout::samples 565243 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 565243 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 565243 # Request fanout histogram
system.membus.reqLayer0.occupancy 30308000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1878196000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 3792332596 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
---------- End Simulation Statistics ----------
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