path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.906037                       # Number of seconds simulated
sim_ticks                                1906037467000                       # Number of ticks simulated
final_tick                               1906037467000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 252781                       # Simulator instruction rate (inst/s)
host_op_rate                                   252781                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             8583432112                       # Simulator tick rate (ticks/s)
host_mem_usage                                 376892                       # Number of bytes of host memory used
host_seconds                                   222.06                       # Real time elapsed on the host
sim_insts                                    56132533                       # Number of instructions simulated
sim_ops                                      56132533                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst           1050496                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24857984                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             25909440                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1050496                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1050496                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7561088                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7561088                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              16414                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388406                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                404835                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          118142                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               118142                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               551141                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13041708                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               504                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13593353                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          551141                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             551141                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3966915                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3966915                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3966915                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              551141                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13041708                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide              504                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               17560268                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        404835                       # Number of read requests accepted
system.physmem.writeReqs                       118142                       # Number of write requests accepted
system.physmem.readBursts                      404835                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     118142                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 25902720                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6720                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7559680                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  25909440                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7561088                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      105                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          41709                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               25494                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25705                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25829                       # Per bank write bursts
system.physmem.perBankRdBursts::3               25773                       # Per bank write bursts
system.physmem.perBankRdBursts::4               25090                       # Per bank write bursts
system.physmem.perBankRdBursts::5               25012                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24715                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24579                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25194                       # Per bank write bursts
system.physmem.perBankRdBursts::9               25292                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25390                       # Per bank write bursts
system.physmem.perBankRdBursts::11              24989                       # Per bank write bursts
system.physmem.perBankRdBursts::12              24533                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25560                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25835                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25740                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7824                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7665                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8071                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7733                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7203                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7017                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6707                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6431                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7312                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6902                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7273                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6973                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7066                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8009                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7985                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7949                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          13                       # Number of times write queue was full causing retry
system.physmem.totGap                    1906028705500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  404835                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 118142                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    402462                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      2192                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        64                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1810                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5625                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5632                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6322                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6596                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6037                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6430                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7912                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8339                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9439                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8363                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8669                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7496                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6853                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5785                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5489                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      186                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       71                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       35                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        64437                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      519.304127                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     318.318074                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     406.802576                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          14872     23.08%     23.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        11053     17.15%     40.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5024      7.80%     48.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3269      5.07%     53.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2580      4.00%     57.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1937      3.01%     60.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         4194      6.51%     66.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1317      2.04%     68.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        20191     31.33%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          64437                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5312                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        76.190700                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2898.366893                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           5309     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5312                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5312                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.236446                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.912972                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       20.909399                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            4665     87.82%     87.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              19      0.36%     88.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              18      0.34%     88.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             199      3.75%     92.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35               5      0.09%     92.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              25      0.47%     92.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              40      0.75%     93.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               5      0.09%     93.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51               6      0.11%     93.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              23      0.43%     94.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               6      0.11%     94.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               4      0.08%     94.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67               9      0.17%     94.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               1      0.02%     94.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              20      0.38%     94.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              24      0.45%     95.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               2      0.04%     95.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87              32      0.60%     96.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               3      0.06%     96.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103           171      3.22%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.02%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             4      0.08%     99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             2      0.04%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.02%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             3      0.06%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.02%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.04%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             4      0.08%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.04%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             8      0.15%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             3      0.06%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211             1      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227             1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231             2      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5312                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2653633250                       # Total ticks spent queuing
system.physmem.totMemAccLat               10242320750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2023650000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        6556.55                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  25306.55                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.59                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.97                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.59                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.97                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.01                       # Average write queue length when enqueuing
system.physmem.readRowHits                     362859                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     95554                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.65                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.88                       # Row buffer hit rate for writes
system.physmem.avgGap                      3644574.63                       # Average gap between requests
system.physmem.pageHitRate                      87.67                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  238049280                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  129888000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1577136600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                380058480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           124492945200                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            67941192465                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1084023651750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1278782921775                       # Total energy per rank (pJ)
system.physmem_0.averagePower              670.912502                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   1803110214250                       # Time in different power states
system.physmem_0.memoryStateTime::REF     63646700000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     39278414500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  249094440                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  135914625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1579757400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                385359120                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           124492945200                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            68603580630                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1083442617750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1278889269165                       # Total energy per rank (pJ)
system.physmem_1.averagePower              670.968292                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   1802146960250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     63646700000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     40241682250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                15005157                       # Number of BP lookups
system.cpu.branchPred.condPredicted          13016352                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            370563                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9544476                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 5200630                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             54.488376                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                  807259                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              30802                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9242284                       # DTB read hits
system.cpu.dtb.read_misses                      17197                       # DTB read misses
system.cpu.dtb.read_acv                           211                       # DTB read access violations
system.cpu.dtb.read_accesses                   765766                       # DTB read accesses
system.cpu.dtb.write_hits                     6387071                       # DTB write hits
system.cpu.dtb.write_misses                      2294                       # DTB write misses
system.cpu.dtb.write_acv                          160                       # DTB write access violations
system.cpu.dtb.write_accesses                  298411                       # DTB write accesses
system.cpu.dtb.data_hits                     15629355                       # DTB hits
system.cpu.dtb.data_misses                      19491                       # DTB misses
system.cpu.dtb.data_acv                           371                       # DTB access violations
system.cpu.dtb.data_accesses                  1064177                       # DTB accesses
system.cpu.itb.fetch_hits                     4015320                       # ITB hits
system.cpu.itb.fetch_misses                      6841                       # ITB misses
system.cpu.itb.fetch_acv                          659                       # ITB acv
system.cpu.itb.fetch_accesses                 4022161                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                        223168437                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    56132533                       # Number of instructions committed
system.cpu.committedOps                      56132533                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       2504504                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      5489                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   3590815720                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               3.975741                       # CPI: cycles per instruction
system.cpu.ipc                               0.251525                       # IPC: instructions per cycle
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6378                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     211546                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74811     40.93%     40.93% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     41.01% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1904      1.04%     42.05% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  105910     57.95%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               182756                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73444     49.32%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1904      1.28%     50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73444     49.32%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                148923                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1837436986000     96.40%     96.40% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                81017000      0.00%     96.41% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               682412000      0.04%     96.44% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             67836062500      3.56%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1906036477500                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981727                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.693457                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.814873                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4174      2.17%      2.17% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl                175591     91.23%     93.43% # number of callpals executed
system.cpu.kern.callpal::rdps                    6807      3.54%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rti                     5129      2.66%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 192481                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5873                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2096                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1909                      
system.cpu.kern.mode_good::user                  1740                      
system.cpu.kern.mode_good::idle                   169                      
system.cpu.kern.mode_switch_good::kernel     0.325047                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.080630                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.393243                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        38636753000      2.03%      2.03% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           4528404000      0.24%      2.26% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1862871310500     97.74%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4175                       # number of times the context was actually changed
system.cpu.tickCycles                        86394668                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       136773769                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements           1395457                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.977331                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            13772866                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1395969                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs              9.866169                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         121717500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.977331                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999956                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999956                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          224                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          219                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          63663599                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         63663599                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data      7815159                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7815159                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      5575814                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        5575814                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       182834                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       182834                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       199026                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       199026                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      13390973                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         13390973                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     13390973                       # number of overall hits
system.cpu.dcache.overall_hits::total        13390973                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1201770                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1201770                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       575091                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       575091                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        17213                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        17213                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1776861                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1776861                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1776861                       # number of overall misses
system.cpu.dcache.overall_misses::total       1776861                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  46961675000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  46961675000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  33993891500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  33993891500                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    235176000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    235176000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  80955566500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  80955566500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  80955566500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  80955566500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      9016929                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9016929                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6150905                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6150905                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200047                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       200047                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       199026                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       199026                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15167834                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15167834                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15167834                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15167834                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.133279                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.133279                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093497                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.093497                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086045                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086045                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.117147                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.117147                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.117147                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.117147                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39077.090458                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 39077.090458                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59110.456432                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 59110.456432                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13662.696799                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13662.696799                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45561.001395                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 45561.001395                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45561.001395                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 45561.001395                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       838295                       # number of writebacks
system.cpu.dcache.writebacks::total            838295                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       127341                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       127341                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       270722                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       270722                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       398063                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       398063                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       398063                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       398063                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074429                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1074429                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304369                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       304369                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17210                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17210                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1378798                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1378798                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1378798                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1378798                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9622                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total         9622                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16552                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        16552                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43805969000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  43805969000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17294633000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  17294633000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    217700500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    217700500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  61100602000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  61100602000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  61100602000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  61100602000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1450655500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1450655500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2042490500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2042490500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3493146000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3493146000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119157                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119157                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049484                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049484                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086030                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086030                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090903                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.090903                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090903                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.090903                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40771.394853                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40771.394853                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56821.269577                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56821.269577                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12649.651365                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12649.651365                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44314.397033                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 44314.397033                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44314.397033                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44314.397033                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209329.797980                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209329.797980                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212272.968198                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212272.968198                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211040.720155                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211040.720155                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           1459812                       # number of replacements
system.cpu.icache.tags.tagsinuse           508.108213                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            18945545                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1460323                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             12.973531                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       50089035500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   508.108213                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.992399                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.992399                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          405                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          21866544                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         21866544                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     18945548                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        18945548                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      18945548                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         18945548                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     18945548                       # number of overall hits
system.cpu.icache.overall_hits::total        18945548                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1460498                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1460498                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1460498                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1460498                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1460498                       # number of overall misses
system.cpu.icache.overall_misses::total       1460498                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  20983654500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  20983654500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  20983654500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  20983654500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  20983654500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  20983654500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     20406046                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     20406046                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     20406046                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     20406046                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     20406046                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     20406046                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071572                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.071572                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.071572                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.071572                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.071572                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.071572                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14367.465412                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14367.465412                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14367.465412                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14367.465412                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14367.465412                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14367.465412                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1460498                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1460498                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1460498                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1460498                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1460498                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1460498                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  19523156500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  19523156500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  19523156500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  19523156500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  19523156500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  19523156500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071572                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071572                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071572                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.071572                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071572                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.071572                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13367.465412                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13367.465412                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13367.465412                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13367.465412                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13367.465412                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13367.465412                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           339330                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65261.345003                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4998363                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           404492                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            12.357137                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       9675364000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 53948.276768                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  5807.945434                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  5505.122802                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.823185                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.088622                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.084002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.995809                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          223                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          863                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5644                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2903                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55529                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         46387191                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        46387191                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks       838295                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       838295                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       187729                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       187729                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1444018                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      1444018                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       819422                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       819422                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst      1444018                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1007151                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2451169                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst      1444018                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1007151                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2451169                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data           17                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           17                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       116650                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       116650                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16415                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        16415                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       272186                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       272186                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst        16415                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       388836                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        405251                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        16415                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       388836                       # number of overall misses
system.cpu.l2cache.overall_misses::total       405251                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       404000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       404000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14861542500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  14861542500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2151733500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2151733500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  33671733000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  33671733000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2151733500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  48533275500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  50685009000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2151733500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  48533275500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  50685009000                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks       838295                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       838295                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           21                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           21                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       304379                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       304379                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1460433                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      1460433                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1091608                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1091608                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      1460433                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1395987                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2856420                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1460433                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1395987                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2856420                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.809524                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.809524                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383239                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.383239                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.011240                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.011240                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.249344                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.249344                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.011240                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.278538                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.141874                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.011240                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.278538                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.141874                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23764.705882                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23764.705882                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127402.850407                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127402.850407                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131083.368870                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131083.368870                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123708.541218                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123708.541218                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131083.368870                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124816.826374                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 125070.657444                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131083.368870                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124816.826374                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 125070.657444                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        76630                       # number of writebacks
system.cpu.l2cache.writebacks::total            76630                       # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          317                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total          317                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           17                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           17                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116650                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       116650                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16415                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16415                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       272186                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       272186                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16415                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       388836                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       405251                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16415                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       388836                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       405251                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9622                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9622                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16552                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16552                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1214500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1214500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13695042500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13695042500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1987583500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1987583500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  30951837500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  30951837500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1987583500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  44646880000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  46634463500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1987583500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  44646880000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  46634463500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1364010000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1364010000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1931836500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1931836500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3295846500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3295846500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.809524                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.809524                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383239                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383239                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.011240                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.011240                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.249344                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249344                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.011240                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.278538                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.141874                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.011240                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.278538                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.141874                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71441.176471                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71441.176471                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117402.850407                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117402.850407                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121083.368870                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121083.368870                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113715.758709                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113715.758709                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121083.368870                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114821.878633                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115075.505057                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121083.368870                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114821.878633                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115075.505057                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196826.839827                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196826.839827                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200772.864269                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200772.864269                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199120.740696                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199120.740696                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      5711775                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2855459                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1981                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1240                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1240                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2559171                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq          9622                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp         9622                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       956450                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      2277896                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           21                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           21                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       304379                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       304379                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      1460498                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1091781                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError           16                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4380147                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4219373                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8599520                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     93467712                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143047028                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          236514740                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      422969                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      6151080                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.000871                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.029504                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            6145721     99.91%     99.91% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               5359      0.09%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        6151080                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     3707269500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       284383                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    2190955582                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2105716998                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
system.iobus.trans_dist::WriteReq               51174                       # Transaction distribution
system.iobus.trans_dist::WriteResp              51174                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5100                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        33104                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  116554                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20400                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total        44340                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2705948                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              4711000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13484000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           215087245                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            23482000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41685                       # number of replacements
system.iocache.tags.tagsinuse                1.290787                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1748608829000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.290787                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.080674                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.080674                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
system.iocache.tags.data_accesses              375525                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
system.iocache.overall_misses::total              173                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21943883                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21943883                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide   5427163362                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   5427163362                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide     21943883                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     21943883                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide     21943883                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     21943883                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126843.254335                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 126843.254335                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130611.363159                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130611.363159                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 126843.254335                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 126843.254335                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 126843.254335                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 126843.254335                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13293883                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     13293883                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3349563362                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3349563362                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide     13293883                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     13293883                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide     13293883                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     13293883                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76843.254335                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76843.254335                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80611.363159                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80611.363159                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76843.254335                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76843.254335                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76843.254335                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76843.254335                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
system.membus.trans_dist::ReadResp             295688                       # Transaction distribution
system.membus.trans_dist::WriteReq               9622                       # Transaction distribution
system.membus.trans_dist::WriteResp              9622                       # Transaction distribution
system.membus.trans_dist::Writeback            118142                       # Transaction distribution
system.membus.trans_dist::CleanEvict           262192                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              159                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             159                       # Transaction distribution
system.membus.trans_dist::ReadExReq            116508                       # Transaction distribution
system.membus.trans_dist::ReadExResp           116508                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        288774                       # Transaction distribution
system.membus.trans_dist::BadAddressError           16                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33104                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1149038                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           32                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1182174                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124817                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       124817                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1306991                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44340                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30812800                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30857140                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                33514868                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              433                       # Total snoops (count)
system.membus.snoop_fanout::samples            844052                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  844052    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              844052                       # Request fanout histogram
system.membus.reqLayer0.occupancy            29776500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1319401645                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer2.occupancy               20500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2160603841                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy           69882415                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped

---------- End Simulation Statistics   ----------