path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.909061                       # Number of seconds simulated
sim_ticks                                1909061460000                       # Number of ticks simulated
final_tick                               1909061460000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  24403                       # Simulator instruction rate (inst/s)
host_op_rate                                    24403                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              829686396                       # Simulator tick rate (ticks/s)
host_mem_usage                                 385840                       # Number of bytes of host memory used
host_seconds                                  2300.94                       # Real time elapsed on the host
sim_insts                                    56149847                       # Number of instructions simulated
sim_ops                                      56149847                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst           1046656                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24857664                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             25905280                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1046656                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1046656                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7563328                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7563328                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              16354                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388401                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                404770                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          118177                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               118177                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               548257                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13020882                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               503                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13569642                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          548257                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             548257                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3961804                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3961804                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3961804                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              548257                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13020882                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide              503                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               17531446                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        404770                       # Number of read requests accepted
system.physmem.writeReqs                       118177                       # Number of write requests accepted
system.physmem.readBursts                      404770                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     118177                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 25897600                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7680                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7561728                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  25905280                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7563328                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      120                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               25467                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25712                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25810                       # Per bank write bursts
system.physmem.perBankRdBursts::3               25757                       # Per bank write bursts
system.physmem.perBankRdBursts::4               25010                       # Per bank write bursts
system.physmem.perBankRdBursts::5               25117                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24705                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24573                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25203                       # Per bank write bursts
system.physmem.perBankRdBursts::9               25292                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25386                       # Per bank write bursts
system.physmem.perBankRdBursts::11              25018                       # Per bank write bursts
system.physmem.perBankRdBursts::12              24535                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25541                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25794                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25730                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7820                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7678                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8070                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7721                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7116                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7111                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6703                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6420                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7317                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6903                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7274                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7007                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7092                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7990                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7984                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7946                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
system.physmem.totGap                    1909052547000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  404770                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 118177                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    402459                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      2130                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        49                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1514                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2905                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     7219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5886                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6024                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5843                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6456                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6884                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6578                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8579                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8848                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7457                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7892                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7078                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7321                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6026                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5605                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      214                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      208                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      184                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        64573                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      518.162823                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     316.799935                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     407.231768                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          14977     23.19%     23.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        11234     17.40%     40.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4851      7.51%     48.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3268      5.06%     53.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2473      3.83%     56.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2033      3.15%     60.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         4174      6.46%     66.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1362      2.11%     68.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        20201     31.28%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          64573                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5294                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        76.433321                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2890.025475                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           5291     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5294                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5294                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.318096                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.102648                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       19.930772                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23            4682     88.44%     88.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31              33      0.62%     89.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39              23      0.43%     89.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47              33      0.62%     90.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55             222      4.19%     94.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63              11      0.21%     94.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71              11      0.21%     94.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79              35      0.66%     95.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87             195      3.68%     99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95               5      0.09%     99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103              6      0.11%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111             4      0.08%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135             5      0.09%     99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143             2      0.04%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151             1      0.02%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167             2      0.04%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175             9      0.17%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             4      0.08%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             2      0.04%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             5      0.09%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223             1      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             2      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5294                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2639973000                       # Total ticks spent queuing
system.physmem.totMemAccLat               10227160500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2023250000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        6524.09                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  25274.09                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.57                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.96                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.57                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.96                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.18                       # Average write queue length when enqueuing
system.physmem.readRowHits                     362738                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     95491                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.64                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.80                       # Row buffer hit rate for writes
system.physmem.avgGap                      3650566.02                       # Average gap between requests
system.physmem.pageHitRate                      87.64                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  238623840                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  130201500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1576777800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                379980720                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           124690266480                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            68013230490                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1085773099500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1280802180330                       # Total energy per rank (pJ)
system.physmem_0.averagePower              670.908515                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   1806022540250                       # Time in different power states
system.physmem_0.memoryStateTime::REF     63747580000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     39286273500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  249548040                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  136162125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1579492200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                385644240                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           124690266480                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            68685352830                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1085183526750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1280909992665                       # Total energy per rank (pJ)
system.physmem_1.averagePower              670.964984                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   1805042162250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     63747580000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     40266665250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                15258422                       # Number of BP lookups
system.cpu.branchPred.condPredicted          13121569                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            520615                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             12105776                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 4568162                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             37.735392                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                  863536                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              33630                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         6539212                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits             544524                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses          5994688                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted       219095                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9320175                       # DTB read hits
system.cpu.dtb.read_misses                      17427                       # DTB read misses
system.cpu.dtb.read_acv                           211                       # DTB read access violations
system.cpu.dtb.read_accesses                   764388                       # DTB read accesses
system.cpu.dtb.write_hits                     6394455                       # DTB write hits
system.cpu.dtb.write_misses                      2545                       # DTB write misses
system.cpu.dtb.write_acv                          159                       # DTB write access violations
system.cpu.dtb.write_accesses                  298887                       # DTB write accesses
system.cpu.dtb.data_hits                     15714630                       # DTB hits
system.cpu.dtb.data_misses                      19972                       # DTB misses
system.cpu.dtb.data_acv                           370                       # DTB access violations
system.cpu.dtb.data_accesses                  1063275                       # DTB accesses
system.cpu.itb.fetch_hits                     4019631                       # ITB hits
system.cpu.itb.fetch_misses                      6355                       # ITB misses
system.cpu.itb.fetch_acv                          661                       # ITB acv
system.cpu.itb.fetch_accesses                 4025986                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numPwrStateTransitions               12756                       # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples          6378                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean     281603673.878959                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev    439873554.784215                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows            1      0.02%      0.02% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10         6377     99.98%    100.00% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::min_value          500                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total            6378                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON    112993228000                       # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 1796068232000                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        226008061                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    56149847                       # Number of instructions committed
system.cpu.committedOps                      56149847                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       2969857                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      6378                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   3592114868                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               4.025088                       # CPI: cycles per instruction
system.cpu.ipc                               0.248442                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass             3199355      5.70%      5.70% # Class of committed instruction
system.cpu.op_class_0::IntAlu                36201883     64.47%     70.17% # Class of committed instruction
system.cpu.op_class_0::IntMult                  60840      0.11%     70.28% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     70.28% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                 38079      0.07%     70.35% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                     0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                     0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                  3636      0.01%     70.35% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc                0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     70.35% # Class of committed instruction
system.cpu.op_class_0::MemRead                9320961     16.60%     86.95% # Class of committed instruction
system.cpu.op_class_0::MemWrite               6373595     11.35%     98.31% # Class of committed instruction
system.cpu.op_class_0::IprAccess               951498      1.69%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                 56149847                       # Class of committed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6378                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     211594                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74821     40.93%     40.93% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     41.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1907      1.04%     42.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  105943     57.96%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               182802                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73454     49.32%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1907      1.28%     50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73454     49.32%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                148946                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1839859866500     96.38%     96.38% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                85941500      0.00%     96.38% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               711439500      0.04%     96.42% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             68403193000      3.58%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1909060440500                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981730                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.693335                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.814794                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4173      2.17%      2.17% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl                175631     91.22%     93.43% # number of callpals executed
system.cpu.kern.callpal::rdps                    6810      3.54%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rti                     5132      2.67%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 192526                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5877                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2094                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1906                      
system.cpu.kern.mode_good::user                  1738                      
system.cpu.kern.mode_good::idle                   168                      
system.cpu.kern.mode_switch_good::kernel     0.324315                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.080229                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.392625                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        38921683000      2.04%      2.04% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           4598347000      0.24%      2.28% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1865540400500     97.72%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4174                       # number of times the context was actually changed
system.cpu.tickCycles                        85327235                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       140680826                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           1394976                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.976740                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            13944378                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1395488                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs              9.992474                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         124106500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.976740                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999955                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999955                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          227                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          217                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          63924438                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         63924438                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data      7983946                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7983946                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      5577839                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        5577839                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       183518                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       183518                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       199043                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       199043                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      13561785                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         13561785                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     13561785                       # number of overall hits
system.cpu.dcache.overall_hits::total        13561785                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1096703                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1096703                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       574639                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       574639                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        16549                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        16549                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1671342                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1671342                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1671342                       # number of overall misses
system.cpu.dcache.overall_misses::total       1671342                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  45383174000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  45383174000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  33964439500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  33964439500                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    226601500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    226601500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  79347613500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  79347613500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  79347613500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  79347613500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      9080649                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9080649                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6152478                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6152478                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200067                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       200067                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       199043                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       199043                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15233127                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15233127                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15233127                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15233127                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120774                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.120774                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093400                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.093400                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.082717                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.082717                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.109718                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.109718                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.109718                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.109718                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41381.462438                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 41381.462438                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59105.698534                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 59105.698534                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13692.760892                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13692.760892                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47475.390136                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 47475.390136                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47475.390136                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 47475.390136                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks       838068                       # number of writebacks
system.cpu.dcache.writebacks::total            838068                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        21939                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        21939                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       270415                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       270415                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       292354                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       292354                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       292354                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       292354                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074764                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1074764                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304224                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       304224                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        16546                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        16546                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1378988                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1378988                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1378988                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1378988                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9625                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total         9625                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16555                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        16555                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43721360500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  43721360500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17277660500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  17277660500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    209790000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    209790000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  60999021000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  60999021000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  60999021000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  60999021000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1527294000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1527294000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1527294000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   1527294000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.118358                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.118358                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049447                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049447                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.082702                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.082702                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090526                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.090526                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090526                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.090526                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40679.963694                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40679.963694                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56792.562388                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56792.562388                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12679.197389                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12679.197389                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44234.627858                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 44234.627858                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44234.627858                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44234.627858                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220388.744589                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220388.744589                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92255.753549                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92255.753549                       # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements           1477492                       # number of replacements
system.cpu.icache.tags.tagsinuse           508.111413                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            19219698                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1478003                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             13.003829                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       50147606500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   508.111413                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.992405                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.992405                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          407                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          22176055                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         22176055                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     19219701                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        19219701                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      19219701                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         19219701                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     19219701                       # number of overall hits
system.cpu.icache.overall_hits::total        19219701                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1478177                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1478177                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1478177                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1478177                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1478177                       # number of overall misses
system.cpu.icache.overall_misses::total       1478177                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  21231255000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  21231255000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  21231255000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  21231255000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  21231255000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  21231255000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     20697878                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     20697878                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     20697878                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     20697878                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     20697878                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     20697878                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071417                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.071417                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.071417                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.071417                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.071417                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.071417                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14363.134455                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14363.134455                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14363.134455                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14363.134455                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14363.134455                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14363.134455                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks      1477492                       # number of writebacks
system.cpu.icache.writebacks::total           1477492                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1478177                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1478177                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1478177                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1478177                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1478177                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1478177                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  19753078000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  19753078000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  19753078000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  19753078000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  19753078000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  19753078000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071417                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071417                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071417                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.071417                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071417                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.071417                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13363.134455                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13363.134455                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13363.134455                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13363.134455                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13363.134455                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13363.134455                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements           339587                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65260.798092                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            5032980                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           404749                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            12.434818                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       9689078000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 54026.178970                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  5735.607676                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  5499.011446                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.824374                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.087518                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.083908                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.995801                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          226                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          888                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5593                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2924                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55531                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         46662747                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        46662747                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks       838068                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       838068                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks      1476917                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total      1476917                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            5                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            5                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       187586                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       187586                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1461767                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      1461767                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       819079                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       819079                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst      1461767                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1006665                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2468432                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst      1461767                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1006665                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2468432                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data           15                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           15                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       116651                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       116651                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16355                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        16355                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       272198                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       272198                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst        16355                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       388849                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        405204                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        16355                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       388849                       # number of overall misses
system.cpu.l2cache.overall_misses::total       405204                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       396500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       396500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14845341000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  14845341000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2146863500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2146863500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  33671183000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  33671183000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2146863500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  48516524000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  50663387500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2146863500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  48516524000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  50663387500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks       838068                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       838068                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks      1476917                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total      1476917                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           20                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           20                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       304237                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       304237                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1478122                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      1478122                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1091277                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1091277                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      1478122                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1395514                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2873636                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1478122                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1395514                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2873636                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.750000                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.750000                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383421                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.383421                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.011065                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.011065                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.249431                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.249431                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.011065                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.278642                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.141007                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.011065                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.278642                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.141007                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 26433.333333                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 26433.333333                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127262.869585                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127262.869585                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131266.493427                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131266.493427                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123701.066870                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123701.066870                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131266.493427                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124769.573793                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 125031.804967                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131266.493427                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124769.573793                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 125031.804967                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks        76665                       # number of writebacks
system.cpu.l2cache.writebacks::total            76665                       # number of writebacks
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           15                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           15                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116651                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       116651                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16355                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16355                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       272198                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       272198                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16355                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       388849                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       405204                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16355                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       388849                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       405204                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9625                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9625                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16555                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16555                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1032500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1032500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13678831000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13678831000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1983313500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1983313500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  30952316500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  30952316500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1983313500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  44631147500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  46614461000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1983313500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  44631147500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  46614461000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1440649500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1440649500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1440649500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1440649500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.750000                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.750000                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383421                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383421                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.011065                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.011065                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.249431                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249431                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.011065                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.278642                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.141007                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.011065                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.278642                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.141007                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68833.333333                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68833.333333                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117262.869585                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117262.869585                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121266.493427                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121266.493427                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113712.505235                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113712.505235                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121266.493427                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114777.580758                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115039.488751                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121266.493427                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114777.580758                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115039.488751                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207885.930736                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207885.930736                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87022.017517                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87022.017517                       # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests      5746179                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2872664                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1960                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1250                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1250                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2576516                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq          9625                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp         9625                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       956247                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean      1477492                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       820003                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           20                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           20                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       304237                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       304237                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      1478177                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1091450                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError           24                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4433791                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4219310                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8653101                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    189159296                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143002060                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          332161356                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      423210                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic               7576960                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      3313265                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.001022                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.031947                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            3309880     99.90%     99.90% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               3385      0.10%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        3313265                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     5201739500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       291883                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    2217424681                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2105003991                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iobus.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
system.iobus.trans_dist::WriteReq               51177                       # Transaction distribution
system.iobus.trans_dist::WriteResp              51177                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5106                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        33110                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  116560                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20424                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total        44364                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2705972                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              5417500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               799000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              182000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            15625500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             2305500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             6004000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy               90500                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           215719668                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            23485000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                41685                       # number of replacements
system.iocache.tags.tagsinuse                1.297488                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1750571994000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.297488                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.081093                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.081093                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
system.iocache.tags.data_accesses              375525                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21917383                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21917383                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide   5244162285                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   5244162285                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide   5266079668                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   5266079668                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide   5266079668                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   5266079668                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 126690.075145                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126207.217101                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126207.217101                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 126209.219125                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 126209.219125                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 126209.219125                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 126209.219125                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13267383                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     13267383                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3164763984                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3164763984                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   3178031367                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   3178031367                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   3178031367                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   3178031367                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76163.938776                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76163.938776                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76166.120240                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76166.120240                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76166.120240                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76166.120240                       # average overall mshr miss latency
system.membus.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
system.membus.trans_dist::ReadResp             295632                       # Transaction distribution
system.membus.trans_dist::WriteReq               9625                       # Transaction distribution
system.membus.trans_dist::WriteResp              9625                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       118177                       # Transaction distribution
system.membus.trans_dist::CleanEvict           262256                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              167                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            116499                       # Transaction distribution
system.membus.trans_dist::ReadExResp           116499                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        288726                       # Transaction distribution
system.membus.trans_dist::BadAddressError           24                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33110                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1148698                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           48                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1181856                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83425                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        83425                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1265281                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44364                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30810880                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30855244                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                33512972                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              433                       # Total snoops (count)
system.membus.snoopTraffic                      27584                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            843934                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  843934    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              843934                       # Request fanout histogram
system.membus.reqLayer0.occupancy            30445500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1319244966                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer2.occupancy               29500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2159924750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy             943117                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states

---------- End Simulation Statistics   ----------