path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.902739                       # Number of seconds simulated
sim_ticks                                1902738973500                       # Number of ticks simulated
final_tick                               1902738973500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 132013                       # Simulator instruction rate (inst/s)
host_op_rate                                   132013                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4427958303                       # Simulator tick rate (ticks/s)
host_mem_usage                                 313120                       # Number of bytes of host memory used
host_seconds                                   429.71                       # Real time elapsed on the host
sim_insts                                    56727331                       # Number of instructions simulated
sim_ops                                      56727331                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst           900544                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24806400                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2650816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            74944                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           436992                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28869696                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       900544                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        74944                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          975488                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7821440                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7821440                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             14071                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            387600                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41419                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1171                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              6828                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                451089                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          122210                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               122210                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              473288                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            13037206                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1393158                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               39387                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              229665                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15172704                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         473288                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          39387                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             512676                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4110622                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4110622                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4110622                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             473288                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           13037206                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1393158                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              39387                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             229665                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19283326                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        451089                       # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs                       122210                       # Total number of write requests accepted by DRAM controller
system.physmem.readBursts                      451089                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts                     122210                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead                     28869696                       # Total number of bytes read from memory
system.physmem.bytesWritten                   7821440                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               28869696                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7821440                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       73                       # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite               4926                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 28134                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 28249                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 28671                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 28418                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 27918                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 28169                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 28110                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 27493                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 27636                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 28106                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                28006                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                28071                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                28522                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                28683                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                28473                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                28357                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  7885                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  7743                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  8146                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  7856                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  7349                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  7637                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  7614                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  6924                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  6873                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  7305                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 7296                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 7454                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 7954                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 8175                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 8091                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 7908                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           1                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1902738952500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  451089                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                 122210                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    323917                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     64738                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     30395                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      6616                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3317                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      3023                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1574                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1542                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1506                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1471                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1443                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1440                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1410                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     2046                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     2339                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     2216                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     1205                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      449                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      234                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      121                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      3729                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3933                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      5016                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      5304                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      5307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5312                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5312                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1585                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     1381                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        1                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        40469                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      906.491388                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     223.789110                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev    2353.116019                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67          14451     35.71%     35.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131         6072     15.00%     50.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195         3826      9.45%     60.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259         2468      6.10%     66.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323         1670      4.13%     70.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387         1520      3.76%     74.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451         1058      2.61%     76.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515          819      2.02%     78.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579          687      1.70%     80.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643          564      1.39%     81.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707          556      1.37%     83.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771          509      1.26%     84.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835          268      0.66%     85.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899          232      0.57%     85.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963          203      0.50%     86.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027          288      0.71%     86.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091          119      0.29%     87.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155          109      0.27%     87.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219          110      0.27%     87.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283          196      0.48%     88.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347          187      0.46%     88.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411          119      0.29%     89.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475          500      1.24%     90.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539          628      1.55%     91.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603           91      0.22%     92.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667           33      0.08%     92.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731           28      0.07%     92.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795           99      0.24%     92.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859           30      0.07%     92.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923           12      0.03%     92.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987           17      0.04%     92.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051           48      0.12%     92.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115           23      0.06%     92.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179            5      0.01%     92.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243            6      0.01%     92.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307           33      0.08%     92.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371            8      0.02%     92.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435            8      0.02%     92.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499            3      0.01%     92.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563            6      0.01%     92.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627            8      0.02%     92.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691            3      0.01%     92.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755            2      0.00%     92.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819            7      0.02%     92.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883            5      0.01%     92.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947            2      0.00%     93.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011            1      0.00%     93.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075            3      0.01%     93.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139            4      0.01%     93.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203            1      0.00%     93.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267            2      0.00%     93.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331            2      0.00%     93.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395            3      0.01%     93.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459            2      0.00%     93.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523            1      0.00%     93.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587            3      0.01%     93.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651            4      0.01%     93.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779            1      0.00%     93.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843            1      0.00%     93.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907            2      0.00%     93.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035            3      0.01%     93.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099            2      0.00%     93.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227            1      0.00%     93.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4291            1      0.00%     93.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355            1      0.00%     93.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419            2      0.00%     93.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547            1      0.00%     93.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4611            1      0.00%     93.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4739            1      0.00%     93.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4803            3      0.01%     93.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4867            1      0.00%     93.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931            1      0.00%     93.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5187            1      0.00%     93.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379            2      0.00%     93.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5443            1      0.00%     93.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5635            1      0.00%     93.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5763            1      0.00%     93.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6083            1      0.00%     93.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147            1      0.00%     93.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6339            1      0.00%     93.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6723            1      0.00%     93.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851            2      0.00%     93.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7043            1      0.00%     93.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7107            2      0.00%     93.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171            3      0.01%     93.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7299            2      0.00%     93.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7363            2      0.00%     93.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7427            1      0.00%     93.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7619            2      0.00%     93.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7811            2      0.00%     93.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939            1      0.00%     93.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8003            3      0.01%     93.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8067            3      0.01%     93.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8131            7      0.02%     93.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195         2429      6.00%     99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8579            1      0.00%     99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9219            1      0.00%     99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9344-9347            1      0.00%     99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10432-10435            1      0.00%     99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10560-10563            1      0.00%     99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10688-10691            1      0.00%     99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10944-10947            1      0.00%     99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13632-13635            1      0.00%     99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14016-14019            1      0.00%     99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14144-14147            1      0.00%     99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14211            1      0.00%     99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14339            1      0.00%     99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14595            2      0.00%     99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14720-14723            2      0.00%     99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14784-14787            1      0.00%     99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14915            1      0.00%     99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363           16      0.04%     99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15491            1      0.00%     99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15552-15555            1      0.00%     99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15619            1      0.00%     99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16192-16195            1      0.00%     99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387          243      0.60%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16448-16451            4      0.01%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16515            4      0.01%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16576-16579            5      0.01%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16643            5      0.01%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16704-16707            4      0.01%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16768-16771            3      0.01%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16832-16835            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16899            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16960-16963            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17088-17091            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17344-17347            2      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17728-17731            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17792-17795            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          40469                       # Bytes accessed per row activation
system.physmem.totQLat                     6403559750                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat               13868349750                       # Sum of mem lat for all requests
system.physmem.totBusLat                   2255080000                       # Total cycles spent in databus access
system.physmem.totBankLat                  5209710000                       # Total cycles spent in bank access
system.physmem.avgQLat                       14198.08                       # Average queueing delay per request
system.physmem.avgBankLat                    11551.05                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  30749.13                       # Average memory access latency
system.physmem.avgRdBW                          15.17                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           4.11                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  15.17                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   4.11                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.01                       # Average read queue length over time
system.physmem.avgWrQLen                        14.36                       # Average write queue length over time
system.physmem.readRowHits                     435126                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     97620                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   96.48                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  79.88                       # Row buffer hit rate for writes
system.physmem.avgGap                      3318929.48                       # Average gap between requests
system.membus.throughput                     19341454                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              296468                       # Transaction distribution
system.membus.trans_dist::ReadResp             296394                       # Transaction distribution
system.membus.trans_dist::WriteReq              13061                       # Transaction distribution
system.membus.trans_dist::WriteResp             13061                       # Transaction distribution
system.membus.trans_dist::Writeback            122210                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             9880                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq           5735                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4929                       # Transaction distribution
system.membus.trans_dist::ReadExReq            162867                       # Transaction distribution
system.membus.trans_dist::ReadExResp           162463                       # Transaction distribution
system.membus.trans_dist::BadAddressError           74                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40510                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       921241                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          148                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       961899                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124666                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       124666                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1086565                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        73866                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31383040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     31456906                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5308096                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5308096                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            36765002                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               36765002                       # Total data (bytes)
system.membus.snoop_data_through_bus            36736                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            37911498                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1609327499                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer2.occupancy               93500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3831145563                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy          376230495                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.l2c.tags.replacements                   344151                       # number of replacements
system.l2c.tags.tagsinuse                65253.870311                       # Cycle average of tags in use
system.l2c.tags.total_refs                    2581362                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   409161                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     6.308915                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               6889943750                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   53541.051154                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5362.839741                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     6144.208257                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      141.383324                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data       64.387836                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.816972                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.081830                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.093753                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.002157                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000982                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.995695                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst             862836                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             735075                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             214357                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              69353                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1881621                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          822225                       # number of Writeback hits
system.l2c.Writeback_hits::total               822225                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             169                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             270                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 439                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            43                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            25                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                68                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           153625                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            26073                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               179698                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              862836                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              888700                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              214357                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               95426                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2061319                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             862836                       # number of overall hits
system.l2c.overall_hits::cpu0.data             888700                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             214357                       # number of overall hits
system.l2c.overall_hits::cpu1.data              95426                       # number of overall hits
system.l2c.overall_hits::total                2061319                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            14080                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           273430                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             1180                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data              427                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               289117                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2676                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1075                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3751                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          425                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          454                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             879                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         114757                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           6453                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             121210                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             14080                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            388187                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1180                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              6880                       # number of demand (read+write) misses
system.l2c.demand_misses::total                410327                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            14080                       # number of overall misses
system.l2c.overall_misses::cpu0.data           388187                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1180                       # number of overall misses
system.l2c.overall_misses::cpu1.data             6880                       # number of overall misses
system.l2c.overall_misses::total               410327                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst   1210878995                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  17193583984                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    109764250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     37725999                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    18551953228                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      1076463                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      4839759                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      5916222                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       977458                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        93496                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      1070954                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   9311235979                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    722690467                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  10033926446                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1210878995                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  26504819963                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    109764250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    760416466                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     28585879674                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1210878995                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  26504819963                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    109764250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    760416466                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    28585879674                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         876916                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data        1008505                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         215537                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          69780                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2170738                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       822225                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           822225                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2845                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1345                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            4190                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          468                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          479                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           947                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       268382                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        32526                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           300908                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          876916                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1276887                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          215537                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          102306                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2471646                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         876916                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1276887                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         215537                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         102306                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2471646                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.016056                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.271124                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.005475                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.006119                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.133188                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.940598                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.799257                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.895227                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.908120                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.947808                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.928194                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.427588                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.198395                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.402814                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.016056                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.304010                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.005475                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.067249                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.166014                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.016056                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.304010                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.005475                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.067249                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.166014                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85999.928622                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 62881.117595                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 93020.550847                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 88351.285714                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 64167.631886                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   402.265695                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4502.101395                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1577.238603                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2299.901176                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   205.938326                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1218.377702                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81138.719024                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 111992.943902                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 82781.341853                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 85999.928622                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 68278.484243                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 93020.550847                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 110525.649128                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 69666.094783                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 85999.928622                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 68278.484243                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 93020.550847                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 110525.649128                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 69666.094783                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               80690                       # number of writebacks
system.l2c.writebacks::total                    80690                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             9                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        14072                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       273429                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         1171                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data          427                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          289099                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2676                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1075                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3751                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          425                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          454                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          879                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       114757                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         6453                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        121210                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        14072                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       388186                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1171                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         6880                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           410309                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        14072                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       388186                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1171                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         6880                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          410309                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   1031878505                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  13784019266                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     94337500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     32390501                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  14942625772                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     26984633                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     10773037                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     37757670                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      4256416                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4544453                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      8800869                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7896551021                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    642755533                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   8539306554                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1031878505                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  21680570287                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     94337500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    675146034                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  23481932326                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1031878505                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  21680570287                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     94337500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    675146034                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  23481932326                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1367321000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     22027000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1389348000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2025100000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    585946999                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2611046999                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3392421000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    607973999                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   4000394999                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.016047                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.271123                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005433                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.006119                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.133180                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.940598                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.799257                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.895227                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.908120                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.947808                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.928194                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.427588                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.198395                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.402814                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.016047                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.304010                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005433                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.067249                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.166006                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.016047                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.304010                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005433                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.067249                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.166006                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 73328.489554                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50411.694685                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 80561.485909                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75855.974239                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 51686.881560                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10083.943572                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.429767                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10066.027726                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.096471                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.808370                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.365188                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68811.061818                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99605.692391                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 70450.511954                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73328.489554                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55850.984546                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 80561.485909                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98131.690988                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 57229.873890                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73328.489554                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55850.984546                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80561.485909                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98131.690988                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 57229.873890                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                41695                       # number of replacements
system.iocache.tags.tagsinuse                0.476417                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41711                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1711329338000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     0.476417                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.029776                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.029776                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          175                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41727                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41727                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41727                       # number of overall misses
system.iocache.overall_misses::total            41727                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21570383                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21570383                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  10493964012                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10493964012                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  10515534395                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10515534395                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  10515534395                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10515534395                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          175                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41727                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41727                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41727                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41727                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123259.331429                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 123259.331429                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 252550.154313                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 252550.154313                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 252007.918015                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 252007.918015                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 252007.918015                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 252007.918015                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        275771                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                27285                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.107055                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          175                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          175                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41727                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41727                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41727                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41727                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12468883                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12468883                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   8331886522                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   8331886522                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   8344355405                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8344355405                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   8344355405                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8344355405                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71250.760000                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 71250.760000                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 200517.099586                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 200517.099586                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199974.965969                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 199974.965969                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199974.965969                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 199974.965969                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               12458299                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         10491650                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           332886                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             8054816                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                5283733                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            65.597191                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 799392                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             28656                       # Number of incorrect RAS predictions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     8872852                       # DTB read hits
system.cpu0.dtb.read_misses                     32010                       # DTB read misses
system.cpu0.dtb.read_acv                          540                       # DTB read access violations
system.cpu0.dtb.read_accesses                  628428                       # DTB read accesses
system.cpu0.dtb.write_hits                    5797852                       # DTB write hits
system.cpu0.dtb.write_misses                     8130                       # DTB write misses
system.cpu0.dtb.write_acv                         348                       # DTB write access violations
system.cpu0.dtb.write_accesses                 210128                       # DTB write accesses
system.cpu0.dtb.data_hits                    14670704                       # DTB hits
system.cpu0.dtb.data_misses                     40140                       # DTB misses
system.cpu0.dtb.data_acv                          888                       # DTB access violations
system.cpu0.dtb.data_accesses                  838556                       # DTB accesses
system.cpu0.itb.fetch_hits                     994919                       # ITB hits
system.cpu0.itb.fetch_misses                    28800                       # ITB misses
system.cpu0.itb.fetch_acv                         922                       # ITB acv
system.cpu0.itb.fetch_accesses                1023719                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       114636003                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          25048083                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      63888139                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   12458299                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           6083125                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     12009946                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1716539                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles              37364333                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles               31995                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       196940                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       358937                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          467                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  7724257                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               222992                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples          76114982                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.839364                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.177033                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                64105036     84.22%     84.22% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  766655      1.01%     85.23% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1565630      2.06%     87.29% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  705022      0.93%     88.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2586372      3.40%     91.61% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  523946      0.69%     92.30% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  578047      0.76%     93.06% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  832534      1.09%     94.15% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4451740      5.85%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            76114982                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.108677                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.557313                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                26317520                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             36878715                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 10917325                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               932522                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1068899                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              511897                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                35733                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              62704701                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               106993                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1068899                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                27334042                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               15040257                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      18326535                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 10227103                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              4118144                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              59323627                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 7153                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                638131                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1449994                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands           39722637                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             72231674                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        72093935                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           128190                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             34859464                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 4863165                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1453792                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        211881                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 11242711                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             9290886                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6078694                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1146384                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores          744084                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  52609114                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1811011                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 51412755                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           100173                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        5939256                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      3114263                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1226583                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     76114982                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.675462                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.326460                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           53279780     70.00%     70.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10372988     13.63%     83.63% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            4693410      6.17%     89.79% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            3092664      4.06%     93.86% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2443569      3.21%     97.07% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1213853      1.59%     98.66% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             652140      0.86%     99.52% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             314050      0.41%     99.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              52528      0.07%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       76114982                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  82827     12.15%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     12.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                318873     46.78%     58.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               279966     41.07%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             3785      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             35420825     68.90%     68.90% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               56384      0.11%     69.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     69.01% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              15702      0.03%     69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1879      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9231506     17.96%     87.00% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5866326     11.41%     98.41% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            816348      1.59%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              51412755                       # Type of FU issued
system.cpu0.iq.rate                          0.448487                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     681666                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.013259                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         179170597                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         60104783                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     50356616                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             551733                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            267128                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       260409                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              51801972                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 288664                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          541765                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1139912                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         4116                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        12815                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       456622                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        18431                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       154294                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1068899                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               10746647                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               795792                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           57645786                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           623000                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              9290886                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6078694                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1595130                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                581617                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 5318                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         12815                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        164656                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       351489                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              516145                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             51022070                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              8928198                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           390684                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      3225661                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14747797                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 8123465                       # Number of branches executed
system.cpu0.iew.exec_stores                   5819599                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.445079                       # Inst execution rate
system.cpu0.iew.wb_sent                      50710143                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     50617025                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 25247170                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 34011376                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.441546                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.742315                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        6411331                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         584428                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           481702                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     75046083                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.681415                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.595696                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     55785925     74.34%     74.34% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      8029512     10.70%     85.04% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      4410175      5.88%     90.91% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2388789      3.18%     94.09% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1317256      1.76%     95.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       560978      0.75%     96.60% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       472301      0.63%     97.23% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       435634      0.58%     97.81% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1645513      2.19%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     75046083                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            51137491                       # Number of instructions committed
system.cpu0.commit.committedOps              51137491                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      13773046                       # Number of memory references committed
system.cpu0.commit.loads                      8150974                       # Number of loads committed
system.cpu0.commit.membars                     198820                       # Number of memory barriers committed
system.cpu0.commit.branches                   7724848                       # Number of branches committed
system.cpu0.commit.fp_insts                    258424                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 47356368                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              655486                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1645513                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   130752703                       # The number of ROB reads
system.cpu0.rob.rob_writes                  116166541                       # The number of ROB writes
system.cpu0.timesIdled                        1097555                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       38521021                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3690835342                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   48197169                       # Number of Instructions Simulated
system.cpu0.committedOps                     48197169                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             48197169                       # Number of Instructions Simulated
system.cpu0.cpi                              2.378480                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.378480                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.420437                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.420437                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                67125195                       # number of integer regfile reads
system.cpu0.int_regfile_writes               36645952                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   127833                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  129422                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1709874                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                817230                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.toL2Bus.throughput                   111571177                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2198759                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2198668                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             13061                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            13061                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           822225                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           10020                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq          5803                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          15823                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           343740                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          302191                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError           74                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1753935                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3363647                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       431103                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       300395                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               5849080                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     56122624                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    129969996                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     13794368                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     11000190                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          210887178                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             210876874                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus         1413952                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4971684979                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.3                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           724500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        3951712593                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        5887546567                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         970657716                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         517795038                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                       1437659                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq                 7369                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7369                       # Transaction distribution
system.iobus.trans_dist::WriteReq               54613                       # Transaction distribution
system.iobus.trans_dist::WriteResp              54613                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11914                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        40510                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83454                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83454                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  123964                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        47656                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total        73866                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661624                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661624                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              2735490                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 2735490                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             11269000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13505000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             2450000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           378285900                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            27449000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            43112505                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.cpu0.icache.tags.replacements           876399                       # number of replacements
system.cpu0.icache.tags.tagsinuse          509.760309                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs            6802362                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           876908                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs             7.757213                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      26019048250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.760309                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995626                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.995626                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      6802362                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        6802362                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      6802362                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         6802362                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      6802362                       # number of overall hits
system.cpu0.icache.overall_hits::total        6802362                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       921891                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       921891                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       921891                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        921891                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       921891                       # number of overall misses
system.cpu0.icache.overall_misses::total       921891                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13290047828                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  13290047828                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  13290047828                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  13290047828                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  13290047828                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  13290047828                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      7724253                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      7724253                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      7724253                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      7724253                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      7724253                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      7724253                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.119350                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.119350                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.119350                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.119350                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.119350                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.119350                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14416.072863                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14416.072863                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14416.072863                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14416.072863                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14416.072863                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14416.072863                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         6191                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets         1109                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              232                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              2                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    26.685345                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets   554.500000                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        44872                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        44872                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        44872                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        44872                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        44872                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        44872                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       877019                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       877019                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       877019                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       877019                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       877019                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       877019                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10904529395                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  10904529395                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10904529395                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  10904529395                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10904529395                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  10904529395                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.113541                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.113541                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.113541                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.113541                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.113541                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.113541                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12433.629596                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12433.629596                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12433.629596                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12433.629596                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12433.629596                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12433.629596                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements          1278910                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          505.619274                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           10469394                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1279422                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs             8.182909                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         25842000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.619274                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.987538                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.987538                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      6440836                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6440836                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3667453                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3667453                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       162740                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       162740                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       187465                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       187465                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10108289                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        10108289                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10108289                       # number of overall hits
system.cpu0.dcache.overall_hits::total       10108289                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1585845                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1585845                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1749611                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1749611                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20563                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        20563                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2808                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         2808                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3335456                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3335456                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3335456                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3335456                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  40055257591                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  40055257591                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  78246234000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  78246234000                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    299434996                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    299434996                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     20885924                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     20885924                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 118301491591                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 118301491591                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 118301491591                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 118301491591                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      8026681                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8026681                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5417064                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5417064                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       183303                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       183303                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       190273                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       190273                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     13443745                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     13443745                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     13443745                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     13443745                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.197572                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.197572                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.322981                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.322981                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.112180                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.112180                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.014758                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.014758                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.248105                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.248105                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.248105                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.248105                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25257.990277                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 25257.990277                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44722.074793                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 44722.074793                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14561.834168                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14561.834168                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7438.007123                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7438.007123                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35467.861543                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 35467.861543                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35467.861543                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 35467.861543                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      2886351                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         1258                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            51822                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    55.697407                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   179.714286                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       752999                       # number of writebacks
system.cpu0.dcache.writebacks::total           752999                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       583027                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       583027                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1475561                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1475561                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4528                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4528                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      2058588                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      2058588                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      2058588                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      2058588                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1002818                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      1002818                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       274050                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       274050                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        16035                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        16035                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2807                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         2807                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1276868                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1276868                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1276868                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1276868                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  26563866972                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  26563866972                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11468217837                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11468217837                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    177500254                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    177500254                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     15271076                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     15271076                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  38032084809                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  38032084809                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  38032084809                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  38032084809                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1459298500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1459298500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2147907499                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2147907499                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3607205999                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3607205999                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.124936                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.124936                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.050590                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.050590                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.087478                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.087478                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.014752                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.014752                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.094979                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.094979                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.094979                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.094979                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26489.220349                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26489.220349                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41847.173279                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41847.173279                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11069.551232                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11069.551232                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5440.354827                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5440.354827                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29785.447524                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29785.447524                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29785.447524                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29785.447524                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                2517085                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          2083961                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect            72869                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             1481224                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                 844711                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            57.027904                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 172550                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect              7415                       # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1869470                       # DTB read hits
system.cpu1.dtb.read_misses                     10476                       # DTB read misses
system.cpu1.dtb.read_acv                           22                       # DTB read access violations
system.cpu1.dtb.read_accesses                  321268                       # DTB read accesses
system.cpu1.dtb.write_hits                    1203365                       # DTB write hits
system.cpu1.dtb.write_misses                     2061                       # DTB write misses
system.cpu1.dtb.write_acv                          64                       # DTB write access violations
system.cpu1.dtb.write_accesses                 130567                       # DTB write accesses
system.cpu1.dtb.data_hits                     3072835                       # DTB hits
system.cpu1.dtb.data_misses                     12537                       # DTB misses
system.cpu1.dtb.data_acv                           86                       # DTB access violations
system.cpu1.dtb.data_accesses                  451835                       # DTB accesses
system.cpu1.itb.fetch_hits                     424254                       # ITB hits
system.cpu1.itb.fetch_misses                     6539                       # ITB misses
system.cpu1.itb.fetch_acv                         190                       # ITB acv
system.cpu1.itb.fetch_accesses                 430793                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                        15249987                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles           5781097                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      11894429                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    2517085                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           1017261                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      2131045                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 385761                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles               6016414                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles               25794                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        62392                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        56888                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles           41                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  1433413                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                48410                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples          14320297                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.830599                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.206016                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                12189252     85.12%     85.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  136413      0.95%     86.07% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  229060      1.60%     87.67% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  170637      1.19%     88.86% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  294592      2.06%     90.92% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  114916      0.80%     91.72% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  126454      0.88%     92.61% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  195471      1.36%     93.97% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                  863502      6.03%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            14320297                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.165055                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.779963                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 5724387                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles              6255039                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  1992849                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               108261                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                239760                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              108451                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                 6971                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              11669639                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                20547                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                239760                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 5925475                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                 420572                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       5212839                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  1896462                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles               625187                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              10812976                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                   71                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 55937                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents               153486                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands            7119549                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups             12930789                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        12872049                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            52940                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps              6082585                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 1036964                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            436590                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         40484                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  1926881                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             1976180                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            1276143                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           178422                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           98267                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                   9491737                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             473513                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                  9233560                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            29148                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        1376057                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined       698810                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        340347                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     14320297                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.644788                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.319506                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           10263877     71.67%     71.67% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            1860247     12.99%     84.66% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2             792265      5.53%     90.20% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             533948      3.73%     93.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             454852      3.18%     97.10% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             207190      1.45%     98.55% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             132078      0.92%     99.47% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7              67607      0.47%     99.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8               8233      0.06%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       14320297                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                   3147      1.66%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                101977     53.82%     55.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                84363     44.52%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             3526      0.04%      0.04% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              5756733     62.35%     62.38% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               16005      0.17%     62.56% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.56% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd              10795      0.12%     62.67% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.67% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.67% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.67% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1763      0.02%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             1955574     21.18%     83.87% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            1226577     13.28%     97.16% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            262587      2.84%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total               9233560                       # Type of FU issued
system.cpu1.iq.rate                          0.605480                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     189487                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.020522                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          32803401                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         11243674                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses      8968182                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads             202651                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes             99238                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses        96146                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses               9314130                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 105391                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           90243                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       277299                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         1341                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         1688                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       122180                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads          318                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        14956                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                239760                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 255964                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                40163                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           10453412                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           142319                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              1976180                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             1276143                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            429143                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 33341                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 1750                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          1688                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         32963                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect        95419                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              128382                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts              9148055                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              1886987                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts            85505                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       488162                       # number of nop insts executed
system.cpu1.iew.exec_refs                     3098273                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 1362461                       # Number of branches executed
system.cpu1.iew.exec_stores                   1211286                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.599873                       # Inst execution rate
system.cpu1.iew.wb_sent                       9092483                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                      9064328                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  4254481                       # num instructions producing a value
system.cpu1.iew.wb_consumers                  5984515                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.594383                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.710915                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        1421128                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         133166                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           121427                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     14080537                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.636506                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.577564                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     10719102     76.13%     76.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      1572221     11.17%     87.29% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2       583613      4.14%     91.44% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       356342      2.53%     93.97% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       255998      1.82%     95.79% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       100117      0.71%     96.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       105425      0.75%     97.25% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       105001      0.75%     97.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       282718      2.01%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     14080537                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts             8962351                       # Number of instructions committed
system.cpu1.commit.committedOps               8962351                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       2852844                       # Number of memory references committed
system.cpu1.commit.loads                      1698881                       # Number of loads committed
system.cpu1.commit.membars                      42409                       # Number of memory barriers committed
system.cpu1.commit.branches                   1280511                       # Number of branches committed
system.cpu1.commit.fp_insts                     94891                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                  8306060                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              141484                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events               282718                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                    24092433                       # The number of ROB reads
system.cpu1.rob.rob_writes                   21005155                       # The number of ROB writes
system.cpu1.timesIdled                         128904                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                         929690                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3789568266                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                    8530162                       # Number of Instructions Simulated
system.cpu1.committedOps                      8530162                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total              8530162                       # Number of Instructions Simulated
system.cpu1.cpi                              1.787772                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.787772                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.559355                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.559355                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                11798212                       # number of integer regfile reads
system.cpu1.int_regfile_writes                6449971                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    52607                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   52314                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 504098                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                209723                       # number of misc regfile writes
system.cpu1.icache.tags.replacements           214995                       # number of replacements
system.cpu1.icache.tags.tagsinuse          470.564735                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            1210101                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           215507                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs             5.615135                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     1878702632250                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   470.564735                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.919072                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.919072                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      1210101                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        1210101                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      1210101                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         1210101                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      1210101                       # number of overall hits
system.cpu1.icache.overall_hits::total        1210101                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       223312                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       223312                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       223312                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        223312                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       223312                       # number of overall misses
system.cpu1.icache.overall_misses::total       223312                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   3028009139                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   3028009139                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   3028009139                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   3028009139                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   3028009139                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   3028009139                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      1433413                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      1433413                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      1433413                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      1433413                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      1433413                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      1433413                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.155790                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.155790                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.155790                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.155790                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.155790                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.155790                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13559.545116                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13559.545116                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13559.545116                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13559.545116                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13559.545116                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13559.545116                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs          273                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               32                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs     8.531250                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         7746                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total         7746                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst         7746                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total         7746                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst         7746                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total         7746                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       215566                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       215566                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       215566                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       215566                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       215566                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       215566                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   2508977533                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   2508977533                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   2508977533                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   2508977533                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   2508977533                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   2508977533                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.150387                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.150387                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.150387                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.150387                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.150387                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.150387                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11639.022541                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11639.022541                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11639.022541                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11639.022541                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11639.022541                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11639.022541                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           104218                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          490.671059                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            2506866                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           104618                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            23.962091                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      44824844250                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   490.671059                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.958342                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.958342                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      1537129                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1537129                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data       905397                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        905397                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        30937                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        30937                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        29831                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        29831                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      2442526                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         2442526                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      2442526                       # number of overall hits
system.cpu1.dcache.overall_hits::total        2442526                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       200186                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       200186                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       209846                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       209846                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         5149                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         5149                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data         2998                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         2998                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       410032                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        410032                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       410032                       # number of overall misses
system.cpu1.dcache.overall_misses::total       410032                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2816563957                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2816563957                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   7378261443                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   7378261443                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     51136995                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     51136995                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     22092953                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     22092953                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  10194825400                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  10194825400                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  10194825400                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  10194825400                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      1737315                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      1737315                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      1115243                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1115243                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        36086                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        36086                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        32829                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        32829                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      2852558                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      2852558                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      2852558                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      2852558                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.115227                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.115227                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.188162                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.188162                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.142687                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.142687                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.091322                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.091322                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.143742                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.143742                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.143742                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.143742                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14069.734932                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14069.734932                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35160.362566                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 35160.362566                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9931.442028                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9931.442028                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7369.230487                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7369.230487                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24863.487240                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 24863.487240                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24863.487240                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 24863.487240                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs       240672                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3904                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    61.647541                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks        69226                       # number of writebacks
system.cpu1.dcache.writebacks::total            69226                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       124077                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       124077                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       172447                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       172447                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          558                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total          558                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       296524                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       296524                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       296524                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       296524                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        76109                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total        76109                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        37399                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        37399                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4591                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4591                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         2996                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total         2996                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       113508                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       113508                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       113508                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       113508                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    856275217                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total    856275217                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1088322932                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1088322932                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     34640753                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     34640753                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     16100047                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     16100047                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   1944598149                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   1944598149                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   1944598149                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   1944598149                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     23613000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     23613000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    620064002                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    620064002                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    643677002                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    643677002                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.043808                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.043808                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.033534                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.033534                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.127224                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.127224                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.091261                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.091261                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.039792                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.039792                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.039792                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.039792                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11250.643380                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11250.643380                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29100.321720                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29100.321720                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7545.361141                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7545.361141                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5373.847463                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5373.847463                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17131.815810                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17131.815810                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17131.815810                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17131.815810                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6603                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    184198                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   65080     40.52%     40.52% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.08%     40.60% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1924      1.20%     41.80% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    193      0.12%     41.92% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  93271     58.08%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              160599                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    64086     49.21%     49.21% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.10%     49.31% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1924      1.48%     50.79% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     193      0.15%     50.94% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   63894     49.06%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               130228                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1861779564000     97.85%     97.85% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               63861000      0.00%     97.85% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              571607000      0.03%     97.88% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30               92660000      0.00%     97.89% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            40230450500      2.11%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1902738142500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.984726                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.685036                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.810889                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         7      3.32%      3.32% # number of syscalls executed
system.cpu0.kern.syscall::3                        17      8.06%     11.37% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.90%     13.27% # number of syscalls executed
system.cpu0.kern.syscall::6                        29     13.74%     27.01% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.47%     27.49% # number of syscalls executed
system.cpu0.kern.syscall::17                       10      4.74%     32.23% # number of syscalls executed
system.cpu0.kern.syscall::19                        7      3.32%     35.55% # number of syscalls executed
system.cpu0.kern.syscall::20                        4      1.90%     37.44% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.47%     37.91% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.42%     39.34% # number of syscalls executed
system.cpu0.kern.syscall::33                        8      3.79%     43.13% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.95%     44.08% # number of syscalls executed
system.cpu0.kern.syscall::45                       37     17.54%     61.61% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.42%     63.03% # number of syscalls executed
system.cpu0.kern.syscall::48                        8      3.79%     66.82% # number of syscalls executed
system.cpu0.kern.syscall::54                        9      4.27%     71.09% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.47%     71.56% # number of syscalls executed
system.cpu0.kern.syscall::59                        5      2.37%     73.93% # number of syscalls executed
system.cpu0.kern.syscall::71                       27     12.80%     86.73% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.42%     88.15% # number of syscalls executed
system.cpu0.kern.syscall::74                        7      3.32%     91.47% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.47%     91.94% # number of syscalls executed
system.cpu0.kern.syscall::90                        2      0.95%     92.89% # number of syscalls executed
system.cpu0.kern.syscall::92                        7      3.32%     96.21% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.95%     97.16% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.95%     98.10% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.47%     98.58% # number of syscalls executed
system.cpu0.kern.syscall::144                       1      0.47%     99.05% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.95%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   211                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  284      0.17%      0.17% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.17% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.17% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.17% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3514      2.08%      2.25% # number of callpals executed
system.cpu0.kern.callpal::tbi                      48      0.03%      2.27% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.28% # number of callpals executed
system.cpu0.kern.callpal::swpipl               153834     90.90%     93.18% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6534      3.86%     97.04% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.04% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     4      0.00%     97.04% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     8      0.00%     97.05% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     97.05% # number of callpals executed
system.cpu0.kern.callpal::rti                    4517      2.67%     99.72% # number of callpals executed
system.cpu0.kern.callpal::callsys                 345      0.20%     99.92% # number of callpals executed
system.cpu0.kern.callpal::imb                     137      0.08%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                169239                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             7061                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1286                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1285                      
system.cpu0.kern.mode_good::user                 1286                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.181986                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.308015                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1900726417500     99.89%     99.89% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          2011717000      0.11%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3515                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2440                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     55424                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   17233     36.50%     36.50% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1922      4.07%     40.57% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    284      0.60%     41.17% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  27775     58.83%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               47214                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    16850     47.30%     47.30% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1922      5.40%     52.70% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     284      0.80%     53.50% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   16566     46.50%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                35622                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1871948155000     98.40%     98.40% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              531300500      0.03%     98.43% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              128640500      0.01%     98.43% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            29802235500      1.57%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1902410331500                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.977775                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.596436                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.754480                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2                         1      0.87%      0.87% # number of syscalls executed
system.cpu1.kern.syscall::3                        13     11.30%     12.17% # number of syscalls executed
system.cpu1.kern.syscall::6                        13     11.30%     23.48% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.87%     24.35% # number of syscalls executed
system.cpu1.kern.syscall::17                        5      4.35%     28.70% # number of syscalls executed
system.cpu1.kern.syscall::19                        3      2.61%     31.30% # number of syscalls executed
system.cpu1.kern.syscall::20                        2      1.74%     33.04% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.61%     35.65% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.61%     38.26% # number of syscalls executed
system.cpu1.kern.syscall::33                        3      2.61%     40.87% # number of syscalls executed
system.cpu1.kern.syscall::45                       17     14.78%     55.65% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.61%     58.26% # number of syscalls executed
system.cpu1.kern.syscall::48                        2      1.74%     60.00% # number of syscalls executed
system.cpu1.kern.syscall::54                        1      0.87%     60.87% # number of syscalls executed
system.cpu1.kern.syscall::59                        2      1.74%     62.61% # number of syscalls executed
system.cpu1.kern.syscall::71                       27     23.48%     86.09% # number of syscalls executed
system.cpu1.kern.syscall::74                        9      7.83%     93.91% # number of syscalls executed
system.cpu1.kern.syscall::90                        1      0.87%     94.78% # number of syscalls executed
system.cpu1.kern.syscall::92                        2      1.74%     96.52% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.61%     99.13% # number of syscalls executed
system.cpu1.kern.syscall::144                       1      0.87%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   115                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  193      0.40%      0.40% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.40% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.40% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 1095      2.25%      2.65% # number of callpals executed
system.cpu1.kern.callpal::tbi                       6      0.01%      2.66% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      2.67% # number of callpals executed
system.cpu1.kern.callpal::swpipl                41959     86.06%     88.73% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2221      4.56%     93.29% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.29% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     3      0.01%     93.30% # number of callpals executed
system.cpu1.kern.callpal::rdusp                     1      0.00%     93.30% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     93.31% # number of callpals executed
system.cpu1.kern.callpal::rti                    3048      6.25%     99.56% # number of callpals executed
system.cpu1.kern.callpal::callsys                 172      0.35%     99.91% # number of callpals executed
system.cpu1.kern.callpal::imb                      43      0.09%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 48756                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             1363                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                459                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2408                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                668                      
system.cpu1.kern.mode_good::user                  459                      
system.cpu1.kern.mode_good::idle                  209                      
system.cpu1.kern.mode_switch_good::kernel     0.490095                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.086794                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.315839                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        4405402000      0.23%      0.23% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           814709500      0.04%      0.27% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1897179577000     99.73%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    1096                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------