path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.896396                       # Number of seconds simulated
sim_ticks                                1896395899500                       # Number of ticks simulated
final_tick                               1896395899500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 196112                       # Simulator instruction rate (inst/s)
host_op_rate                                   196112                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6628227410                       # Simulator tick rate (ticks/s)
host_mem_usage                                 302056                       # Number of bytes of host memory used
host_seconds                                   286.11                       # Real time elapsed on the host
sim_insts                                    56109524                       # Number of instructions simulated
sim_ops                                      56109524                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst           881728                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24808704                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2650688                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            99648                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           472640                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28913408                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       881728                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        99648                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          981376                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7865856                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7865856                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             13777                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            387636                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41417                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1557                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              7385                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                451772                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          122904                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               122904                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              464949                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            13082028                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1397750                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               52546                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              249231                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15246504                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         464949                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          52546                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             517495                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4147792                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4147792                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4147792                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             464949                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           13082028                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1397750                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              52546                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             249231                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19394296                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        344859                       # number of replacements
system.l2c.tagsinuse                     65321.127934                       # Cycle average of tags in use
system.l2c.total_refs                         2609636                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        410035                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          6.364423                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                    6312493000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        53767.491128                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          5338.607060                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          6047.920982                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst           140.590955                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data            26.517809                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.820427                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.081461                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.092284                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.002145                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.000405                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.996721                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst             978177                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             784326                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             102747                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              33274                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1898524                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          832872                       # number of Writeback hits
system.l2c.Writeback_hits::total               832872                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             159                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              41                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 200                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            29                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            22                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                51                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           175658                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             7994                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               183652                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              978177                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              959984                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              102747                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               41268                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2082176                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             978177                       # number of overall hits
system.l2c.overall_hits::cpu0.data             959984                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             102747                       # number of overall hits
system.l2c.overall_hits::cpu1.data              41268                       # number of overall hits
system.l2c.overall_hits::total                2082176                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            13779                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           273160                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             1574                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data              765                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               289278                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2448                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           557                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3005                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           42                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           80                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             122                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         114897                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           6716                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             121613                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             13779                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            388057                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1574                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              7481                       # number of demand (read+write) misses
system.l2c.demand_misses::total                410891                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            13779                       # number of overall misses
system.l2c.overall_misses::cpu0.data           388057                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1574                       # number of overall misses
system.l2c.overall_misses::cpu1.data             7481                       # number of overall misses
system.l2c.overall_misses::total               410891                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst    720793500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  14208419500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     82364000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     41213000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    15052790000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      2256000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      1409000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      3665000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       419000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       157000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       576000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   6027292500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    352112000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6379404500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst    720793500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  20235712000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     82364000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    393325000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     21432194500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst    720793500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  20235712000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     82364000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    393325000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    21432194500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         991956                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data        1057486                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         104321                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          34039                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2187802                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       832872                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           832872                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2607                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          598                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3205                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           71                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          102                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           173                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       290555                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        14710                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           305265                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          991956                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1348041                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          104321                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           48749                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2493067                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         991956                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1348041                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         104321                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          48749                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2493067                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.013891                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.258311                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.015088                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.022474                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.132223                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.939010                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.931438                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.937598                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.591549                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.784314                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.705202                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.395440                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.456560                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.398385                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.013891                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.287867                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.015088                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.153460                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.164813                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.013891                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.287867                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.015088                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.153460                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.164813                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52311.016765                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52015.007688                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52327.827192                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 53873.202614                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52035.723422                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   921.568627                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2529.622980                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1219.633943                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  9976.190476                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1962.500000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  4721.311475                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52458.223452                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52428.826683                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52456.600035                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52311.016765                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52146.236249                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 52327.827192                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52576.527202                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52160.291902                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52311.016765                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52146.236249                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 52327.827192                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52576.527202                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52160.291902                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               81384                       # number of writebacks
system.l2c.writebacks::total                    81384                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst            17                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             17                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            17                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        13778                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       273160                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         1557                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data          765                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          289260                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2448                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          557                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3005                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           42                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           80                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          122                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       114897                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         6716                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        121613                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        13778                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       388057                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1557                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         7481                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           410873                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        13778                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       388057                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1557                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         7481                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          410873                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    552060500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10929358000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     62432500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     31914000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  11575765000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     97983500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     22281000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    120264500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      1681500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      3200000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      4881500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4629799500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    270393000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   4900192500                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    552060500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  15559157500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     62432500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    302307000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16475957500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    552060500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  15559157500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     62432500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    302307000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16475957500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    821481000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     16663000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total    838144000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1131946998                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    287746500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1419693498                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1953427998                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    304409500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   2257837498                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.013890                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.258311                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.014925                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.022474                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.132215                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.939010                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.931438                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.937598                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.591549                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.784314                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.705202                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.395440                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.456560                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.398385                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013890                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.287867                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014925                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.153460                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.164806                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013890                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.287867                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014925                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.153460                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.164806                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40068.260996                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40010.828818                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40097.944766                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41717.647059                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40018.547328                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40025.939542                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40001.795332                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40021.464226                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40035.714286                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40012.295082                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40295.216585                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40261.018463                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40293.328016                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40068.260996                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40095.031142                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40097.944766                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40409.971929                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40099.878795                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40068.260996                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40095.031142                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40097.944766                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40409.971929                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40099.878795                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41697                       # number of replacements
system.iocache.tagsinuse                     0.462803                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41713                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1708345741000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       0.462803                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.028925                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.028925                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          177                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              177                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41729                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41729                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41729                       # number of overall misses
system.iocache.overall_misses::total            41729                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     20390998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     20390998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide   5719191806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   5719191806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide   5739582804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   5739582804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide   5739582804                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   5739582804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          177                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            177                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41729                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41729                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41729                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41729                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115203.378531                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 115203.378531                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137639.386937                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 137639.386937                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 137544.221141                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 137544.221141                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 137544.221141                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 137544.221141                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs      64663068                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                10457                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  6183.711198                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          177                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          177                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41729                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41729                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41729                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41729                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11186998                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     11186998                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   3558333000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   3558333000                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   3569519998                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   3569519998                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   3569519998                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   3569519998                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63203.378531                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 63203.378531                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85635.661340                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 85635.661340                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85540.511347                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 85540.511347                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85540.511347                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 85540.511347                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     9453856                       # DTB read hits
system.cpu0.dtb.read_misses                     36184                       # DTB read misses
system.cpu0.dtb.read_acv                          571                       # DTB read access violations
system.cpu0.dtb.read_accesses                  675976                       # DTB read accesses
system.cpu0.dtb.write_hits                    6300368                       # DTB write hits
system.cpu0.dtb.write_misses                     8347                       # DTB write misses
system.cpu0.dtb.write_acv                         346                       # DTB write access violations
system.cpu0.dtb.write_accesses                 234133                       # DTB write accesses
system.cpu0.dtb.data_hits                    15754224                       # DTB hits
system.cpu0.dtb.data_misses                     44531                       # DTB misses
system.cpu0.dtb.data_acv                          917                       # DTB access violations
system.cpu0.dtb.data_accesses                  910109                       # DTB accesses
system.cpu0.itb.fetch_hits                    1108660                       # ITB hits
system.cpu0.itb.fetch_misses                    28136                       # ITB misses
system.cpu0.itb.fetch_acv                        1047                       # ITB acv
system.cpu0.itb.fetch_accesses                1136796                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       111705884                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                13423445                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted          11229595                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect            405618                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups              9732141                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                 5644182                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                  889528                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect              35792                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles          28347650                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      67883922                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   13423445                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           6533710                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     12779049                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1882893                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles              34959873                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles               30735                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       200156                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       304542                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          145                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  8317299                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               264993                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples          77847394                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.872013                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.211541                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                65068345     83.58%     83.58% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  840291      1.08%     84.66% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1663244      2.14%     86.80% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  773630      0.99%     87.79% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2654406      3.41%     91.20% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  587924      0.76%     91.96% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  633021      0.81%     92.77% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  971381      1.25%     94.02% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4655152      5.98%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            77847394                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.120168                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.607702                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                29292805                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             34750406                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 11695757                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               922620                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1185805                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              575553                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                39816                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              66717094                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               118720                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1185805                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                30365496                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               12492089                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      18756431                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 10933791                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              4113780                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              63191653                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 6630                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                474971                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1473898                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands           42180100                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             76536527                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        76096983                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           439544                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             36808161                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 5371931                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1596682                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        238140                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 11595704                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             9967009                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6589337                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1245862                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores          818929                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  55970736                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            2008418                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 54697537                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           108647                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6579388                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      3235320                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1364468                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     77847394                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.702625                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.358580                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           53933184     69.28%     69.28% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10617760     13.64%     82.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            4942911      6.35%     89.27% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            3320001      4.26%     93.53% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2532609      3.25%     96.79% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1408678      1.81%     98.60% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             686959      0.88%     99.48% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             303964      0.39%     99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             101328      0.13%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       77847394                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  87681     11.80%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     11.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                349168     46.97%     58.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               306477     41.23%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             3778      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             37484034     68.53%     68.54% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               60241      0.11%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              16826      0.03%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9867065     18.04%     86.72% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            6373328     11.65%     98.37% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            890382      1.63%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              54697537                       # Type of FU issued
system.cpu0.iq.rate                          0.489657                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     743326                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.013590                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         187461216                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         64264846                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     53535096                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             633224                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            306465                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       298013                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              55105300                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 331785                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          567631                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1269870                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         3726                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        13071                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       496722                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        18808                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       143577                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1185805                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                8725439                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               608869                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           61441844                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           619329                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              9967009                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6589337                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1767664                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                482033                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                12133                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         13071                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        215254                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       393579                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              608833                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             54218225                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9516523                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           479311                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      3462690                       # number of nop insts executed
system.cpu0.iew.exec_refs                    15839640                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 8639850                       # Number of branches executed
system.cpu0.iew.exec_stores                   6323117                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.485366                       # Inst execution rate
system.cpu0.iew.wb_sent                      53937806                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     53833109                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 26624302                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 35973761                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.481918                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.740103                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts      54183968                       # The number of committed instructions
system.cpu0.commit.commitCommittedOps        54183968                       # The number of committed instructions
system.cpu0.commit.commitSquashedInsts        7167159                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         643950                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           567683                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     76661589                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.706794                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.627118                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     56437400     73.62%     73.62% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      8432395     11.00%     84.62% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      4492859      5.86%     90.48% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2495159      3.25%     93.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1450592      1.89%     95.63% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       646072      0.84%     96.47% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       460772      0.60%     97.07% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       487702      0.64%     97.71% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1758638      2.29%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     76661589                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            54183968                       # Number of instructions committed
system.cpu0.commit.committedOps              54183968                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      14789754                       # Number of memory references committed
system.cpu0.commit.loads                      8697139                       # Number of loads committed
system.cpu0.commit.membars                     219715                       # Number of memory barriers committed
system.cpu0.commit.branches                   8176675                       # Number of branches committed
system.cpu0.commit.fp_insts                    295518                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 50137398                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              709743                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1758638                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   136054419                       # The number of ROB reads
system.cpu0.rob.rob_writes                  123888625                       # The number of ROB writes
system.cpu0.timesIdled                        1249831                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       33858490                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3681079567                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   51051860                       # Number of Instructions Simulated
system.cpu0.committedOps                     51051860                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             51051860                       # Number of Instructions Simulated
system.cpu0.cpi                              2.188086                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.188086                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.457020                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.457020                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                71111535                       # number of integer regfile reads
system.cpu0.int_regfile_writes               38857328                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   146185                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  148692                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1886112                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                899559                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.icache.replacements                991395                       # number of replacements
system.cpu0.icache.tagsinuse               510.024196                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 7272203                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                991905                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  7.331552                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           23165696000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   510.024196                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.996141                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.996141                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      7272203                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        7272203                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      7272203                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         7272203                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      7272203                       # number of overall hits
system.cpu0.icache.overall_hits::total        7272203                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1045096                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1045096                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1045096                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1045096                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1045096                       # number of overall misses
system.cpu0.icache.overall_misses::total      1045096                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  15554108994                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  15554108994                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  15554108994                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  15554108994                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  15554108994                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  15554108994                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      8317299                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      8317299                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      8317299                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      8317299                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      8317299                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      8317299                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.125653                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.125653                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.125653                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.125653                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.125653                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.125653                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14882.947590                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14882.947590                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14882.947590                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14882.947590                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14882.947590                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14882.947590                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs      1419995                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              129                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 11007.713178                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks          253                       # number of writebacks
system.cpu0.icache.writebacks::total              253                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        53062                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        53062                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        53062                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        53062                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        53062                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        53062                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       992034                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       992034                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       992034                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       992034                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       992034                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       992034                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11805368995                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11805368995                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11805368995                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11805368995                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11805368995                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11805368995                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.119274                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.119274                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.119274                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.119274                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.119274                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.119274                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11900.165715                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11900.165715                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11900.165715                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11900.165715                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11900.165715                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11900.165715                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1352160                       # number of replacements
system.cpu0.dcache.tagsinuse               506.886378                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                11309312                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1352672                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                  8.360720                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              19277000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   506.886378                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.990012                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.990012                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      6911324                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6911324                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3997215                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3997215                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       183850                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       183850                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       210761                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       210761                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10908539                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        10908539                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10908539                       # number of overall hits
system.cpu0.dcache.overall_hits::total       10908539                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1709932                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1709932                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1869031                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1869031                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        22271                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        22271                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data          641                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total          641                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3578963                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3578963                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3578963                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3578963                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  36329127500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  36329127500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  56639435392                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  56639435392                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    326225500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    326225500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      5918000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      5918000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  92968562892                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  92968562892                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  92968562892                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  92968562892                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      8621256                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8621256                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5866246                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5866246                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       206121                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       206121                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       211402                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       211402                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     14487502                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     14487502                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     14487502                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     14487502                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.198339                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.198339                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.318608                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.318608                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.108048                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.108048                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.003032                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.003032                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.247038                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.247038                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.247038                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.247038                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21245.948669                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 21245.948669                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30304.171195                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 30304.171195                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.995151                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.995151                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  9232.449298                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  9232.449298                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25976.396764                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 25976.396764                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25976.396764                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 25976.396764                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs    790531306                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       168000                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            99401                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  7952.951238                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets        24000                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       805259                       # number of writebacks
system.cpu0.dcache.writebacks::total           805259                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       661851                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       661851                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1575507                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1575507                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         5029                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         5029                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      2237358                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      2237358                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      2237358                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      2237358                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1048081                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      1048081                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       293524                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       293524                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        17242                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        17242                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          640                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total          640                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1341605                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1341605                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1341605                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1341605                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  23566810500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  23566810500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8456840306                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8456840306                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    195574000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    195574000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      3991500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      3991500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  32023650806                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  32023650806                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  32023650806                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  32023650806                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    917307000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    917307000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1253595498                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1253595498                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2170902498                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2170902498                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.121569                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.121569                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.050036                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.050036                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.083650                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.083650                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.003027                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.003027                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.092604                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.092604                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.092604                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.092604                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22485.676680                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22485.676680                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28811.409990                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28811.409990                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11342.883656                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.883656                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6236.718750                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6236.718750                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23869.656722                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23869.656722                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23869.656722                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23869.656722                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1211336                       # DTB read hits
system.cpu1.dtb.read_misses                      9865                       # DTB read misses
system.cpu1.dtb.read_acv                            6                       # DTB read access violations
system.cpu1.dtb.read_accesses                  283619                       # DTB read accesses
system.cpu1.dtb.write_hits                     674221                       # DTB write hits
system.cpu1.dtb.write_misses                     1908                       # DTB write misses
system.cpu1.dtb.write_acv                          40                       # DTB write access violations
system.cpu1.dtb.write_accesses                 107232                       # DTB write accesses
system.cpu1.dtb.data_hits                     1885557                       # DTB hits
system.cpu1.dtb.data_misses                     11773                       # DTB misses
system.cpu1.dtb.data_acv                           46                       # DTB access violations
system.cpu1.dtb.data_accesses                  390851                       # DTB accesses
system.cpu1.itb.fetch_hits                     332989                       # ITB hits
system.cpu1.itb.fetch_misses                     6158                       # ITB misses
system.cpu1.itb.fetch_acv                         143                       # ITB acv
system.cpu1.itb.fetch_accesses                 339147                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                         8872891                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                 1582523                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted           1301899                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect             53959                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups               749480                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                  495600                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                  108561                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect               5012                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles           3100077                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                       7469135                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    1582523                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches            604161                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      1348473                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 293042                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles               3524434                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles               23987                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        56676                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        47433                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles           22                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                   951392                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                34043                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples           8293149                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.900639                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.276932                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                 6944676     83.74%     83.74% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   71085      0.86%     84.60% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  161786      1.95%     86.55% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  117935      1.42%     87.97% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  195029      2.35%     90.32% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   79896      0.96%     91.29% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                   91030      1.10%     92.38% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                   58799      0.71%     93.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                  572913      6.91%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total             8293149                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.178355                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.841793                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 3156648                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles              3626684                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  1266182                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                55854                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                187780                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved               69682                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                 4376                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts               7275177                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                13096                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                187780                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 3279437                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                 303001                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       2955129                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  1188563                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles               379237                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts               6712088                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                   44                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 36332                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents                73621                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands            4503320                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups              8147567                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups         8100022                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            47545                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps              3660294                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                  843026                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            283944                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         19782                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  1166048                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             1294582                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores             736122                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           125256                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           86989                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                   5902743                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             293921                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                  5640439                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            22605                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        1087589                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined       606184                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        224688                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples      8293149                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.680132                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.353961                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0            5841725     70.44%     70.44% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            1091278     13.16%     83.60% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2             496152      5.98%     89.58% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             349787      4.22%     93.80% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             258149      3.11%     96.91% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             126242      1.52%     98.43% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6              71640      0.86%     99.30% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7              51558      0.62%     99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8               6618      0.08%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total        8293149                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                   3067      2.40%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      2.40% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                 73236     57.36%     59.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                51382     40.24%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             3518      0.06%      0.06% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              3484656     61.78%     61.84% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               10025      0.18%     62.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.02% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd               8917      0.16%     62.18% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.18% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.18% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.18% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1759      0.03%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             1261676     22.37%     84.58% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite             692210     12.27%     96.85% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            177678      3.15%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total               5640439                       # Type of FU issued
system.cpu1.iq.rate                          0.635693                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     127685                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.022637                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          19654183                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes          7250568                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses      5466934                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              70134                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes             35039                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses        33778                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses               5728452                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                  36154                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           64737                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       237812                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          428                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         1426                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       105246                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads          373                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        23964                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                187780                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 210633                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                 9248                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts            6437285                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts            88203                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              1294582                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts              736122                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            274301                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                  3887                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 3376                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          1426                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         25150                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect        66283                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts               91433                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts              5579037                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              1224301                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts            61402                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       240621                       # number of nop insts executed
system.cpu1.iew.exec_refs                     1903575                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                  816845                       # Number of branches executed
system.cpu1.iew.exec_stores                    679274                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.628773                       # Inst execution rate
system.cpu1.iew.wb_sent                       5526738                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                      5500712                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  2655801                       # num instructions producing a value
system.cpu1.iew.wb_consumers                  3693565                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.619946                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.719035                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts       5260797                       # The number of committed instructions
system.cpu1.commit.commitCommittedOps         5260797                       # The number of committed instructions
system.cpu1.commit.commitSquashedInsts        1110508                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls          69233                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts            85933                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples      8105369                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.649051                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.577854                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0      6083727     75.06%     75.06% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1       977563     12.06%     87.12% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2       351716      4.34%     91.46% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       209459      2.58%     94.04% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       128681      1.59%     95.63% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        67803      0.84%     96.47% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6        72265      0.89%     97.36% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7        49144      0.61%     97.96% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       165011      2.04%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total      8105369                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts             5260797                       # Number of instructions committed
system.cpu1.commit.committedOps               5260797                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       1687646                       # Number of memory references committed
system.cpu1.commit.loads                      1056770                       # Number of loads committed
system.cpu1.commit.membars                      18284                       # Number of memory barriers committed
system.cpu1.commit.branches                    746127                       # Number of branches committed
system.cpu1.commit.fp_insts                     32538                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                  4917553                       # Number of committed integer instructions.
system.cpu1.commit.function_calls               83297                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events               165011                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                    14229924                       # The number of ROB reads
system.cpu1.rob.rob_writes                   12929135                       # The number of ROB writes
system.cpu1.timesIdled                          74630                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                         579742                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3783284242                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                    5057664                       # Number of Instructions Simulated
system.cpu1.committedOps                      5057664                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total              5057664                       # Number of Instructions Simulated
system.cpu1.cpi                              1.754346                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.754346                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.570013                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.570013                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                 7235777                       # number of integer regfile reads
system.cpu1.int_regfile_writes                3986410                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    21879                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   20613                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 262487                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                123180                       # number of misc regfile writes
system.cpu1.icache.replacements                103776                       # number of replacements
system.cpu1.icache.tagsinuse               452.422972                       # Cycle average of tags in use
system.cpu1.icache.total_refs                  841895                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                104287                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                  8.072866                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1873827117000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   452.422972                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.883639                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.883639                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst       841895                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total         841895                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst       841895                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total          841895                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst       841895                       # number of overall hits
system.cpu1.icache.overall_hits::total         841895                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       109497                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       109497                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       109497                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        109497                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       109497                       # number of overall misses
system.cpu1.icache.overall_misses::total       109497                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   1632285999                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   1632285999                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   1632285999                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   1632285999                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   1632285999                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   1632285999                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst       951392                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total       951392                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst       951392                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total       951392                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst       951392                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total       951392                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.115091                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.115091                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.115091                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.115091                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.115091                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.115091                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14907.129867                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14907.129867                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14907.129867                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14907.129867                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14907.129867                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14907.129867                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs       108999                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               15                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs  7266.600000                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks           39                       # number of writebacks
system.cpu1.icache.writebacks::total               39                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         5150                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total         5150                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst         5150                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total         5150                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst         5150                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total         5150                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       104347                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       104347                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       104347                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       104347                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       104347                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       104347                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   1240890499                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   1240890499                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   1240890499                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   1240890499                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   1240890499                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   1240890499                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.109678                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.109678                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.109678                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.109678                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.109678                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.109678                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11891.961427                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11891.961427                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11891.961427                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11891.961427                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11891.961427                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11891.961427                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                 49122                       # number of replacements
system.cpu1.dcache.tagsinuse               427.490507                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 1549420                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                 49435                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 31.342571                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle          1873347092000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   427.490507                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.834942                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.834942                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      1023689                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1023689                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data       507974                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        507974                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        14665                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        14665                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        12767                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        12767                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      1531663                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         1531663                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      1531663                       # number of overall hits
system.cpu1.dcache.overall_hits::total        1531663                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data        89035                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total        89035                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       104470                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       104470                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         1314                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         1314                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data          680                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total          680                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       193505                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        193505                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       193505                       # number of overall misses
system.cpu1.dcache.overall_misses::total       193505                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1323211000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   1323211000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   3353600320                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   3353600320                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     16083500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     16083500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      7995500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total      7995500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   4676811320                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   4676811320                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   4676811320                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   4676811320                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      1112724                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      1112724                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data       612444                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total       612444                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        15979                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        15979                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        13447                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        13447                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      1725168                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      1725168                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      1725168                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      1725168                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.080015                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.080015                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.170579                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.170579                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.082233                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.082233                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.050569                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.050569                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.112166                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.112166                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.112166                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.112166                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14861.694839                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14861.694839                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32101.084713                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 32101.084713                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12240.106545                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12240.106545                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11758.088235                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11758.088235                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24168.943025                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 24168.943025                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24168.943025                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 24168.943025                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs     52059498                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             4983                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10447.420831                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks        27321                       # number of writebacks
system.cpu1.dcache.writebacks::total            27321                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        51379                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        51379                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        87869                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total        87869                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          246                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total          246                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       139248                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       139248                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       139248                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       139248                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        37656                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total        37656                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        16601                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        16601                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         1068                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         1068                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          674                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total          674                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data        54257                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total        54257                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data        54257                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total        54257                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    431650500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total    431650500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    497061484                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total    497061484                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data      9472500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total      9472500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      5965000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      5965000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data    928711984                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total    928711984                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data    928711984                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total    928711984                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18616500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18616500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    318558500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    318558500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    337175000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    337175000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033841                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.033841                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027106                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027106                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.066838                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.066838                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.050123                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.050123                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031450                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.031450                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031450                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.031450                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11462.993945                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11462.993945                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29941.659177                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29941.659177                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8869.382022                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8869.382022                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  8850.148368                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  8850.148368                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17116.906279                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17116.906279                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17116.906279                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17116.906279                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6349                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    201504                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   72229     40.68%     40.68% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    237      0.13%     40.82% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1919      1.08%     41.90% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                      6      0.00%     41.90% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                 103147     58.10%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              177538                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    70862     49.25%     49.25% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     237      0.16%     49.42% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1919      1.33%     50.75% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                       6      0.00%     50.75% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   70856     49.25%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               143880                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1857798011000     97.96%     97.96% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               91384000      0.00%     97.97% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              387547000      0.02%     97.99% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30                3124500      0.00%     97.99% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            38114922000      2.01%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1896394988500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.981074                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.686942                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.810418                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.51%      3.51% # number of syscalls executed
system.cpu0.kern.syscall::3                        19      8.33%     11.84% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.75%     13.60% # number of syscalls executed
system.cpu0.kern.syscall::6                        33     14.47%     28.07% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.44%     28.51% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      3.95%     32.46% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.39%     36.84% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.63%     39.47% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.44%     39.91% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.32%     41.23% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.07%     44.30% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.88%     45.18% # number of syscalls executed
system.cpu0.kern.syscall::45                       36     15.79%     60.96% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.32%     62.28% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.39%     66.67% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.39%     71.05% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.44%     71.49% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.63%     74.12% # number of syscalls executed
system.cpu0.kern.syscall::71                       27     11.84%     85.96% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.32%     87.28% # number of syscalls executed
system.cpu0.kern.syscall::74                        7      3.07%     90.35% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.44%     90.79% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.32%     92.11% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      3.95%     96.05% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.88%     96.93% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.88%     97.81% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.44%     98.25% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.88%     99.12% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.88%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   228                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  104      0.06%      0.06% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3893      2.09%      2.15% # number of callpals executed
system.cpu0.kern.callpal::tbi                      50      0.03%      2.17% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.18% # number of callpals executed
system.cpu0.kern.callpal::swpipl               170509     91.52%     93.70% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6338      3.40%     97.10% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.10% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     97.10% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.00%     97.11% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     97.11% # number of callpals executed
system.cpu0.kern.callpal::rti                    4866      2.61%     99.72% # number of callpals executed
system.cpu0.kern.callpal::callsys                 386      0.21%     99.93% # number of callpals executed
system.cpu0.kern.callpal::imb                     138      0.07%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                186310                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             7415                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1346                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1345                      
system.cpu0.kern.mode_good::user                 1346                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.181389                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.307157                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1894436238500     99.90%     99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          1958742000      0.10%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3894                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2266                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     36241                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                    9521     32.62%     32.62% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1918      6.57%     39.19% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    104      0.36%     39.54% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  17647     60.46%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               29190                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                     9511     45.42%     45.42% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1918      9.16%     54.58% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     104      0.50%     55.08% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                    9407     44.92%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                20940                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1870201149000     98.64%     98.64% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              342845500      0.02%     98.65% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30               41642500      0.00%     98.66% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            25494039500      1.34%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1896079676500                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.998950                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.533065                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.717369                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        11     11.22%     11.22% # number of syscalls executed
system.cpu1.kern.syscall::6                         9      9.18%     20.41% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      1.02%     21.43% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      6.12%     27.55% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      3.06%     30.61% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      3.06%     33.67% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      4.08%     37.76% # number of syscalls executed
system.cpu1.kern.syscall::45                       18     18.37%     56.12% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      3.06%     59.18% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      1.02%     60.20% # number of syscalls executed
system.cpu1.kern.syscall::71                       27     27.55%     87.76% # number of syscalls executed
system.cpu1.kern.syscall::74                        9      9.18%     96.94% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      3.06%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                    98                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                    6      0.02%      0.02% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::swpctx                  334      1.11%      1.14% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.01%      1.15% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.02%      1.17% # number of callpals executed
system.cpu1.kern.callpal::swpipl                24745     82.19%     83.36% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2407      7.99%     91.36% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     91.36% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     91.37% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     91.38% # number of callpals executed
system.cpu1.kern.callpal::rti                    2422      8.04%     99.43% # number of callpals executed
system.cpu1.kern.callpal::callsys                 129      0.43%     99.86% # number of callpals executed
system.cpu1.kern.callpal::imb                      42      0.14%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 30107                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel              710                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                392                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2048                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                420                      
system.cpu1.kern.mode_good::user                  392                      
system.cpu1.kern.mode_good::idle                   28                      
system.cpu1.kern.mode_switch_good::kernel     0.591549                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.013672                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.266667                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        1688462500      0.09%      0.09% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           719657500      0.04%      0.13% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1893332404000     99.87%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                     335                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------