path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.900728                       # Number of seconds simulated
sim_ticks                                1900727697500                       # Number of ticks simulated
final_tick                               1900727697500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  95395                       # Simulator instruction rate (inst/s)
host_op_rate                                    95395                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3185234659                       # Simulator tick rate (ticks/s)
host_mem_usage                                 355712                       # Number of bytes of host memory used
host_seconds                                   596.73                       # Real time elapsed on the host
sim_insts                                    56925219                       # Number of instructions simulated
sim_ops                                      56925219                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst           854208                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24595840                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2651904                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           123328                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           541952                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28767232                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       854208                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       123328                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          977536                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7730048                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7730048                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             13347                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            384310                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41436                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1927                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              8468                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                449488                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          120782                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               120782                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              449411                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12940223                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1395205                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               64885                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              285129                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15134852                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         449411                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          64885                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             514296                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4066889                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4066889                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4066889                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             449411                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12940223                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1395205                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              64885                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             285129                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19201740                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        449488                       # Total number of read requests seen
system.physmem.writeReqs                       120782                       # Total number of write requests seen
system.physmem.cpureqs                         575881                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     28767232                       # Total number of bytes read from memory
system.physmem.bytesWritten                   7730048                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               28767232                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7730048                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       76                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               5601                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 28386                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 28227                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 28192                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 27982                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 28465                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 28241                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 28220                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 28022                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 28087                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 28039                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                28071                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                27938                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                27835                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                28000                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                27859                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                27848                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  7821                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  7706                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  7703                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  7519                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  7864                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  7579                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  7606                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  7518                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  7651                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  7586                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 7578                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 7350                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 7241                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 7443                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 7270                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 7347                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                          10                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1900723138000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  449488                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                 120782                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    319759                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     59264                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     32659                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      7637                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3173                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2957                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      2688                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      2676                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2637                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2595                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1524                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1455                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1415                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1369                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1353                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1389                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     1622                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                     1546                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      914                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      762                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       14                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      3169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3807                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4327                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4374                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      4886                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5235                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     2083                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     1445                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      925                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                      878                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                      366                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                       13                       # What write queue length does an incoming req see
system.physmem.totQLat                     7717714750                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat               15508692250                       # Sum of mem lat for all requests
system.physmem.totBusLat                   2247060000                       # Total cycles spent in databus access
system.physmem.totBankLat                  5543917500                       # Total cycles spent in bank access
system.physmem.avgQLat                       17172.92                       # Average queueing delay per request
system.physmem.avgBankLat                    12335.94                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  34508.85                       # Average memory access latency
system.physmem.avgRdBW                          15.13                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           4.07                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  15.13                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   4.07                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.01                       # Average read queue length over time
system.physmem.avgWrQLen                         9.47                       # Average write queue length over time
system.physmem.readRowHits                     421565                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     92877                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.80                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  76.90                       # Row buffer hit rate for writes
system.physmem.avgGap                      3333023.20                       # Average gap between requests
system.l2c.replacements                        342612                       # number of replacements
system.l2c.tagsinuse                     65284.978501                       # Cycle average of tags in use
system.l2c.total_refs                         2568846                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        407591                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          6.302509                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                    5466319751                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        53776.613719                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          5305.208058                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          5913.214949                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst           209.652371                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data            80.289403                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.820566                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.080951                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.090228                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.003199                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.001225                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.996170                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst             815517                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             714323                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             262022                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              83603                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1875465                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          814738                       # number of Writeback hits
system.l2c.Writeback_hits::total               814738                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             171                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             348                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 519                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            48                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            27                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                75                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           146870                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            31835                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               178705                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              815517                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              861193                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              262022                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              115438                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2054170                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             815517                       # number of overall hits
system.l2c.overall_hits::cpu0.data             861193                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             262022                       # number of overall hits
system.l2c.overall_hits::cpu1.data             115438                       # number of overall hits
system.l2c.overall_hits::total                2054170                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            13350                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           272975                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             1943                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data              909                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               289177                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2763                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1336                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              4099                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          560                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          587                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1147                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         111935                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           7677                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             119612                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             13350                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            384910                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1943                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              8586                       # number of demand (read+write) misses
system.l2c.demand_misses::total                408789                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            13350                       # number of overall misses
system.l2c.overall_misses::cpu0.data           384910                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1943                       # number of overall misses
system.l2c.overall_misses::cpu1.data             8586                       # number of overall misses
system.l2c.overall_misses::total               408789                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst    905376000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  11896032500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    147196500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     67006500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    13015611500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      1013500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      6347986                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      7361486                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       894999                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       135500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      1030499                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   7317066000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    777197999                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   8094263999                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst    905376000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  19213098500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    147196500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    844204499                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     21109875499                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst    905376000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  19213098500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    147196500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    844204499                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    21109875499                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         828867                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         987298                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         263965                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          84512                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2164642                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       814738                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           814738                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2934                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1684                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            4618                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          608                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          614                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1222                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       258805                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        39512                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           298317                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          828867                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1246103                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          263965                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          124024                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2462959                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         828867                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1246103                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         263965                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         124024                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2462959                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.016106                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.276487                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.007361                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.010756                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.133591                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.941718                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.793349                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.887614                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.921053                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.956026                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.938625                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.432507                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.194295                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.400956                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.016106                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.308891                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.007361                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.069229                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.165975                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.016106                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.308891                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.007361                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.069229                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.165975                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67818.426966                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 43579.201392                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75757.334020                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 73714.521452                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 45009.151834                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   366.811437                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4751.486527                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1795.922420                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1598.212500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   230.834753                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total   898.429817                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65368.883727                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101237.201902                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 67671.002901                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 67818.426966                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 49915.820581                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 75757.334020                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 98323.375146                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 51640.028227                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 67818.426966                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 49915.820581                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 75757.334020                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 98323.375146                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 51640.028227                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               79262                       # number of writebacks
system.l2c.writebacks::total                    79262                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst            16                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             16                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            16                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        13349                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       272975                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         1927                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data          908                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          289159                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2763                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1336                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         4099                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          560                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          587                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1147                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       111935                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         7677                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        119612                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        13349                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       384910                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1927                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         8585                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           408771                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        13349                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       384910                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1927                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         8585                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          408771                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    738885342                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data   8553784026                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    122441645                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     55847948                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   9470958961                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     27836728                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     13416820                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     41253548                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      5620046                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      5879586                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     11499632                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   5952955820                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    683390713                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   6636346533                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    738885342                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  14506739846                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    122441645                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    739238661                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16107305494                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    738885342                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  14506739846                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    122441645                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    739238661                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16107305494                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1360324000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     28759000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1389083000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2032921000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    637490500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2670411500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3393245000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    666249500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   4059494500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.016105                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.276487                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.007300                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.010744                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.133583                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941718                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.793349                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.887614                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.921053                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.956026                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.938625                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.432507                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.194295                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.400956                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.016105                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.308891                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007300                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.069220                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.165967                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.016105                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.308891                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007300                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.069220                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.165967                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55351.362799                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31335.411763                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63540.033731                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61506.550661                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 32753.464222                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10074.820123                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10042.529940                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10064.295682                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.796429                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10016.330494                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.834350                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53182.255952                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89017.938387                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 55482.280482                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55351.362799                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37688.654091                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63540.033731                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86108.172510                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 39404.227536                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55351.362799                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37688.654091                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63540.033731                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86108.172510                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 39404.227536                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41699                       # number of replacements
system.iocache.tagsinuse                     0.509421                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41715                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1705456216000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       0.509421                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.031839                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.031839                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          179                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              179                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41731                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41731                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41731                       # number of overall misses
system.iocache.overall_misses::total            41731                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21615998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21615998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  10647231164                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10647231164                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  10668847162                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10668847162                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  10668847162                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10668847162                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          179                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            179                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41731                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41731                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41731                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41731                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120759.765363                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120759.765363                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256238.716885                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 256238.716885                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 255657.596559                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 255657.596559                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 255657.596559                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 255657.596559                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        286486                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                27218                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.525608                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          179                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          179                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41731                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41731                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41731                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41731                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12307249                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12307249                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   8485239667                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   8485239667                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   8497546916                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8497546916                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   8497546916                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8497546916                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68755.581006                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68755.581006                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204207.731686                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 204207.731686                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203626.726319                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 203626.726319                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203626.726319                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 203626.726319                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               12035820                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         10146181                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           320311                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             7799891                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                5138186                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            65.875100                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 760204                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             30176                       # Number of incorrect RAS predictions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     8551483                       # DTB read hits
system.cpu0.dtb.read_misses                     30199                       # DTB read misses
system.cpu0.dtb.read_acv                          541                       # DTB read access violations
system.cpu0.dtb.read_accesses                  624803                       # DTB read accesses
system.cpu0.dtb.write_hits                    5601236                       # DTB write hits
system.cpu0.dtb.write_misses                     7972                       # DTB write misses
system.cpu0.dtb.write_acv                         345                       # DTB write access violations
system.cpu0.dtb.write_accesses                 208308                       # DTB write accesses
system.cpu0.dtb.data_hits                    14152719                       # DTB hits
system.cpu0.dtb.data_misses                     38171                       # DTB misses
system.cpu0.dtb.data_acv                          886                       # DTB access violations
system.cpu0.dtb.data_accesses                  833111                       # DTB accesses
system.cpu0.itb.fetch_hits                     970030                       # ITB hits
system.cpu0.itb.fetch_misses                    28776                       # ITB misses
system.cpu0.itb.fetch_acv                         920                       # ITB acv
system.cpu0.itb.fetch_accesses                 998806                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       100119117                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          24086973                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      61837518                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   12035820                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           5898390                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     11653378                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1636628                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles              36048574                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles               32004                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       195358                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       286105                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          287                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  7499654                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               215735                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples          73358875                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.842945                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.179502                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                61705497     84.11%     84.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  747609      1.02%     85.13% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1536097      2.09%     87.23% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  679694      0.93%     88.15% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2532720      3.45%     91.61% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  506441      0.69%     92.30% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  557934      0.76%     93.06% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  775120      1.06%     94.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4317763      5.89%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            73358875                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.120215                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.617639                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                25314409                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             35520182                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 10594612                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               907065                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1022606                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              498090                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                33900                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              60717129                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               100549                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1022606                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                26293542                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               14517617                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      17593984                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  9931348                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              3999776                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              57516764                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 6773                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                634732                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1395914                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands           38573698                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             70135572                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        69772127                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           363445                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             33935332                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 4638358                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1391962                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        201915                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 10849961                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             8944130                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5848227                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1106835                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores          734658                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  51076458                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1725873                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 49974476                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            73247                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        5675710                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      2876244                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1167818                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     73358875                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.681233                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.330312                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           51151747     69.73%     69.73% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10102031     13.77%     83.50% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            4555933      6.21%     89.71% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2996125      4.08%     93.79% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2381484      3.25%     97.04% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1187378      1.62%     98.66% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             631915      0.86%     99.52% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             300208      0.41%     99.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              52054      0.07%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       73358875                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  82701     12.59%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     12.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                300975     45.82%     58.41% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               273171     41.59%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             3774      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             34554089     69.14%     69.15% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               54830      0.11%     69.26% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     69.26% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              15268      0.03%     69.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     69.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1879      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             8894109     17.80%     87.09% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5667707     11.34%     98.43% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            782820      1.57%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              49974476                       # Type of FU issued
system.cpu0.iq.rate                          0.499150                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     656847                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.013144                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         173517181                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         58238103                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     48994356                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             520739                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            252277                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       246003                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              50355146                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 272403                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          532794                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1055829                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         3465                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        12581                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       434891                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        18411                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       121190                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1022606                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               10355478                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               778603                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           55935625                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           586886                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              8944130                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5848227                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1520110                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                566642                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 4768                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         12581                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        160372                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       334885                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              495257                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             49597141                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              8604090                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           377334                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      3133294                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14226525                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 7904799                       # Number of branches executed
system.cpu0.iew.exec_stores                   5622435                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.495381                       # Inst execution rate
system.cpu0.iew.wb_sent                      49326582                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     49240359                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 24624844                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 33143444                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.491818                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.742978                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        6108836                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         558055                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           462633                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     72336269                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.687326                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.603373                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     53637775     74.15%     74.15% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      7794815     10.78%     84.93% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      4279099      5.92%     90.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2307939      3.19%     94.03% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1284633      1.78%     95.81% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       537599      0.74%     96.55% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       458507      0.63%     97.19% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       423032      0.58%     97.77% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1612870      2.23%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     72336269                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            49718583                       # Number of instructions committed
system.cpu0.commit.committedOps              49718583                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      13301637                       # Number of memory references committed
system.cpu0.commit.loads                      7888301                       # Number of loads committed
system.cpu0.commit.membars                     189589                       # Number of memory barriers committed
system.cpu0.commit.branches                   7515884                       # Number of branches committed
system.cpu0.commit.fp_insts                    243820                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 46055357                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              629203                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1612870                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   126355419                       # The number of ROB reads
system.cpu0.rob.rob_writes                  112677687                       # The number of ROB writes
system.cpu0.timesIdled                        1033455                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       26760242                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3701329669                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   46863203                       # Number of Instructions Simulated
system.cpu0.committedOps                     46863203                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             46863203                       # Number of Instructions Simulated
system.cpu0.cpi                              2.136412                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.136412                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.468074                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.468074                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                65361385                       # number of integer regfile reads
system.cpu0.int_regfile_writes               35679513                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   120846                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  122066                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1631915                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                781460                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.icache.replacements                828283                       # number of replacements
system.cpu0.icache.tagsinuse               510.309737                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 6629306                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                828795                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  7.998728                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           20510250000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   510.309737                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.996699                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.996699                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      6629306                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        6629306                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      6629306                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         6629306                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      6629306                       # number of overall hits
system.cpu0.icache.overall_hits::total        6629306                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       870348                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       870348                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       870348                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        870348                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       870348                       # number of overall misses
system.cpu0.icache.overall_misses::total       870348                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  12313538494                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  12313538494                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  12313538494                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  12313538494                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  12313538494                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  12313538494                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      7499654                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      7499654                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      7499654                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      7499654                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      7499654                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      7499654                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.116052                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.116052                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.116052                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.116052                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.116052                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.116052                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14147.833388                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14147.833388                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14147.833388                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14147.833388                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14147.833388                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14147.833388                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         3221                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets         1246                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              147                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              2                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    21.911565                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          623                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        41379                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        41379                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        41379                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        41379                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        41379                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        41379                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       828969                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       828969                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       828969                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       828969                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       828969                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       828969                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10141631994                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  10141631994                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10141631994                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  10141631994                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10141631994                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  10141631994                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.110534                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.110534                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.110534                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.110534                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.110534                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.110534                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12234.030457                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12234.030457                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12234.030457                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12234.030457                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12234.030457                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12234.030457                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1248455                       # number of replacements
system.cpu0.dcache.tagsinuse               505.645673                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                10073371                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1248967                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                  8.065362                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              22124000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   505.645673                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.987589                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.987589                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      6208704                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6208704                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3519183                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3519183                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       154511                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       154511                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       177820                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       177820                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      9727887                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         9727887                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      9727887                       # number of overall hits
system.cpu0.dcache.overall_hits::total        9727887                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1543041                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1543041                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1697976                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1697976                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        19729                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        19729                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         3730                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         3730                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3241017                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3241017                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3241017                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3241017                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  33524463000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  33524463000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  64948533233                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  64948533233                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    277752500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    277752500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     27309500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     27309500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  98472996233                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  98472996233                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  98472996233                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  98472996233                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7751745                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      7751745                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5217159                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5217159                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       174240                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       174240                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       181550                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       181550                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     12968904                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     12968904                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     12968904                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     12968904                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.199057                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.199057                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.325460                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.325460                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.113229                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.113229                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.020545                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.020545                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.249907                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.249907                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.249907                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.249907                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21726.229569                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 21726.229569                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38250.560216                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38250.560216                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14078.387146                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14078.387146                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7321.581769                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7321.581769                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30383.363072                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 30383.363072                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30383.363072                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 30383.363072                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      2097721                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         1192                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            47310                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    44.339907                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   170.285714                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       729852                       # number of writebacks
system.cpu0.dcache.writebacks::total           729852                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       558383                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       558383                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1432185                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1432185                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4312                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4312                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1990568                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1990568                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1990568                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1990568                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       984658                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       984658                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       265791                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       265791                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        15417                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        15417                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         3730                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         3730                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1250449                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1250449                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1250449                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1250449                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  21282308500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  21282308500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9459587261                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9459587261                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    170557000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    170557000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     19849500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     19849500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  30741895761                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  30741895761                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  30741895761                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  30741895761                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1451668000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1451668000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2155602499                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2155602499                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3607270499                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3607270499                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127024                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127024                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.050946                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.050946                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.088481                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.088481                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.020545                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.020545                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.096419                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.096419                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.096419                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.096419                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21613.909093                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21613.909093                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35590.321948                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35590.321948                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11062.917559                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11062.917559                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5321.581769                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5321.581769                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24584.685790                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24584.685790                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24584.685790                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24584.685790                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                2951275                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          2437405                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect            83356                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             1836683                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                 994148                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            54.127359                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 203977                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect              9132                       # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     2175721                       # DTB read hits
system.cpu1.dtb.read_misses                     10990                       # DTB read misses
system.cpu1.dtb.read_acv                           22                       # DTB read access violations
system.cpu1.dtb.read_accesses                  324709                       # DTB read accesses
system.cpu1.dtb.write_hits                    1432957                       # DTB write hits
system.cpu1.dtb.write_misses                     2208                       # DTB write misses
system.cpu1.dtb.write_acv                          64                       # DTB write access violations
system.cpu1.dtb.write_accesses                 133156                       # DTB write accesses
system.cpu1.dtb.data_hits                     3608678                       # DTB hits
system.cpu1.dtb.data_misses                     13198                       # DTB misses
system.cpu1.dtb.data_acv                           86                       # DTB access violations
system.cpu1.dtb.data_accesses                  457865                       # DTB accesses
system.cpu1.itb.fetch_hits                     458401                       # ITB hits
system.cpu1.itb.fetch_misses                     7664                       # ITB misses
system.cpu1.itb.fetch_acv                         238                       # ITB acv
system.cpu1.itb.fetch_accesses                 466065                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                        18142763                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles           7059665                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      13904860                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    2951275                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           1198125                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      2489767                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 435348                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles               7028149                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles               27735                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        66683                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        53717                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles            8                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  1666090                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                56854                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples          17001992                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.817837                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.192062                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                14512225     85.36%     85.36% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  164132      0.97%     86.32% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  264549      1.56%     87.88% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  196224      1.15%     89.03% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  340931      2.01%     91.04% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  130664      0.77%     91.81% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  146583      0.86%     92.67% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  247056      1.45%     94.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                  999628      5.88%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            17001992                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.162670                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.766414                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 6935204                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles              7342187                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  2328189                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               128213                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                268198                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              130237                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                 8176                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              13648246                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                24564                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                268198                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 7169583                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                 530321                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       6090332                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  2220482                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles               723074                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              12659443                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                   49                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 62425                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents               176745                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands            8295078                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups             15050859                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        14876046                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           174813                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps              7154813                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 1140265                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            506846                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         51390                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  2247067                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             2298271                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            1513317                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           213048                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          119189                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  11099753                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             565057                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 10829119                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            31632                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        1536258                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined       758334                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        401417                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     17001992                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.636932                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.310611                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           12225446     71.91%     71.91% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            2205450     12.97%     84.88% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2             929224      5.47%     90.34% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             621702      3.66%     94.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             537509      3.16%     97.16% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             242497      1.43%     98.59% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             153407      0.90%     99.49% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7              76904      0.45%     99.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8               9853      0.06%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       17001992                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                   3913      1.80%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                115549     53.23%     55.03% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                97618     44.97%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             3526      0.03%      0.03% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              6756968     62.40%     62.43% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               17928      0.17%     62.59% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.59% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd              11481      0.11%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1763      0.02%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             2278200     21.04%     83.75% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            1457808     13.46%     97.22% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            301445      2.78%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              10829119                       # Type of FU issued
system.cpu1.iq.rate                          0.596884                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     217080                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.020046                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          38657394                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         13080099                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     10523969                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads             251548                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            122819                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       119141                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              10911695                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 130978                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          103489                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       301882                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          508                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         1924                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       130297                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads          383                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked         9692                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                268198                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 347966                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                52179                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           12265641                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           165598                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              2298271                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             1513317                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            508976                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 44383                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 2331                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          1924                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         37819                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       111790                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              149609                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             10726333                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              2195343                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           102786                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       600831                       # number of nop insts executed
system.cpu1.iew.exec_refs                     3637407                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 1609945                       # Number of branches executed
system.cpu1.iew.exec_stores                   1442064                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.591218                       # Inst execution rate
system.cpu1.iew.wb_sent                      10671459                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     10643110                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  4954176                       # num instructions producing a value
system.cpu1.iew.wb_consumers                  6965889                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.586631                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.711205                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        1581528                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         163640                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           139954                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     16733794                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.633013                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.579692                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     12789139     76.43%     76.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      1829893     10.94%     87.36% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2       688745      4.12%     91.48% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       420012      2.51%     93.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       300647      1.80%     95.78% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       117990      0.71%     96.49% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       119790      0.72%     97.21% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       126616      0.76%     97.96% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       340962      2.04%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     16733794                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            10592705                       # Number of instructions committed
system.cpu1.commit.committedOps              10592705                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       3379409                       # Number of memory references committed
system.cpu1.commit.loads                      1996389                       # Number of loads committed
system.cpu1.commit.membars                      53397                       # Number of memory barriers committed
system.cpu1.commit.branches                   1516939                       # Number of branches committed
system.cpu1.commit.fp_insts                    117937                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                  9798676                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              169964                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events               340962                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                    28474562                       # The number of ROB reads
system.cpu1.rob.rob_writes                   24615096                       # The number of ROB writes
system.cpu1.timesIdled                         153586                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        1140771                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3782727730                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   10062016                       # Number of Instructions Simulated
system.cpu1.committedOps                     10062016                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             10062016                       # Number of Instructions Simulated
system.cpu1.cpi                              1.803094                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.803094                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.554602                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.554602                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                13798564                       # number of integer regfile reads
system.cpu1.int_regfile_writes                7546386                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    63884                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   63971                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 608483                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                251084                       # number of misc regfile writes
system.cpu1.icache.replacements                263412                       # number of replacements
system.cpu1.icache.tagsinuse               470.047023                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 1392951                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                263924                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                  5.277849                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1875177958000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   470.047023                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.918061                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.918061                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      1392951                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        1392951                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      1392951                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         1392951                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      1392951                       # number of overall hits
system.cpu1.icache.overall_hits::total        1392951                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       273139                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       273139                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       273139                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        273139                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       273139                       # number of overall misses
system.cpu1.icache.overall_misses::total       273139                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   3753112000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   3753112000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   3753112000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   3753112000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   3753112000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   3753112000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      1666090                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      1666090                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      1666090                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      1666090                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      1666090                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      1666090                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.163940                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.163940                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.163940                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.163940                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.163940                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.163940                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13740.666840                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13740.666840                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13740.666840                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13740.666840                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13740.666840                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13740.666840                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs          264                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               18                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    14.666667                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         9144                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total         9144                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst         9144                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total         9144                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst         9144                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total         9144                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       263995                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       263995                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       263995                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       263995                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       263995                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       263995                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3126547000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   3126547000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3126547000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   3126547000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3126547000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   3126547000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.158452                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.158452                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.158452                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.158452                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.158452                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.158452                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11843.205364                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11843.205364                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11843.205364                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11843.205364                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11843.205364                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11843.205364                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                126526                       # number of replacements
system.cpu1.dcache.tagsinuse               490.827782                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 2952051                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                126931                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 23.257132                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           37142562000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   490.827782                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.958648                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.958648                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      1783702                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1783702                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      1082593                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       1082593                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        39936                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        39936                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        38619                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        38619                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      2866295                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         2866295                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      2866295                       # number of overall hits
system.cpu1.dcache.overall_hits::total        2866295                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       242985                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       242985                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       251423                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       251423                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         6626                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         6626                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data         3957                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         3957                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       494408                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        494408                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       494408                       # number of overall misses
system.cpu1.dcache.overall_misses::total       494408                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3665622000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   3665622000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   8223225631                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   8223225631                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     67675500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     67675500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     29039500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     29039500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  11888847631                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  11888847631                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  11888847631                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  11888847631                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      2026687                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      2026687                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      1334016                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1334016                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        46562                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        46562                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        42576                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        42576                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      3360703                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      3360703                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      3360703                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      3360703                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.119893                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.119893                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.188471                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.188471                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.142305                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.142305                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.092940                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.092940                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.147114                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.147114                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.147114                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.147114                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15085.795419                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15085.795419                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32706.735784                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 32706.735784                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10213.628132                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10213.628132                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7338.766742                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7338.766742                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24046.632803                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 24046.632803                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24046.632803                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 24046.632803                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs       255815                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3992                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    64.081914                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks        84886                       # number of writebacks
system.cpu1.dcache.writebacks::total            84886                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       150812                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       150812                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       205594                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       205594                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          644                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total          644                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       356406                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       356406                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       356406                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       356406                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        92173                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total        92173                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        45829                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        45829                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5982                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5982                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         3957                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total         3957                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       138002                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       138002                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       138002                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       138002                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1122474000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1122474000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1228877987                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1228877987                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     47579000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     47579000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     21125500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     21125500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2351351987                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   2351351987                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2351351987                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   2351351987                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     30976000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     30976000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    675219000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    675219000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    706195000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    706195000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.045480                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.045480                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.034354                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.034354                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.128474                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.128474                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.092940                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.092940                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.041063                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.041063                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.041063                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.041063                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12177.904592                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12177.904592                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26814.418534                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26814.418534                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7953.694417                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7953.694417                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5338.766742                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5338.766742                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17038.535579                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17038.535579                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17038.535579                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17038.535579                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6610                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    175912                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   61740     40.36%     40.36% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.09%     40.45% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1928      1.26%     41.71% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    255      0.17%     41.88% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  88907     58.12%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              152961                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    60876     49.17%     49.17% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.11%     49.27% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1928      1.56%     50.83% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     255      0.21%     51.04% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   60621     48.96%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               123811                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1865672058500     98.16%     98.16% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               62377000      0.00%     98.16% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              564179500      0.03%     98.19% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30              124028500      0.01%     98.20% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            34304214500      1.80%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1900726858000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.986006                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.681847                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.809429                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         7      3.47%      3.47% # number of syscalls executed
system.cpu0.kern.syscall::3                        16      7.92%     11.39% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.98%     13.37% # number of syscalls executed
system.cpu0.kern.syscall::6                        29     14.36%     27.72% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.50%     28.22% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      4.46%     32.67% # number of syscalls executed
system.cpu0.kern.syscall::19                        7      3.47%     36.14% # number of syscalls executed
system.cpu0.kern.syscall::20                        4      1.98%     38.12% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.50%     38.61% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.49%     40.10% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.47%     43.56% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.99%     44.55% # number of syscalls executed
system.cpu0.kern.syscall::45                       34     16.83%     61.39% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.49%     62.87% # number of syscalls executed
system.cpu0.kern.syscall::48                        8      3.96%     66.83% # number of syscalls executed
system.cpu0.kern.syscall::54                        9      4.46%     71.29% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.50%     71.78% # number of syscalls executed
system.cpu0.kern.syscall::59                        5      2.48%     74.26% # number of syscalls executed
system.cpu0.kern.syscall::71                       25     12.38%     86.63% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.49%     88.12% # number of syscalls executed
system.cpu0.kern.syscall::74                        6      2.97%     91.09% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.50%     91.58% # number of syscalls executed
system.cpu0.kern.syscall::90                        2      0.99%     92.57% # number of syscalls executed
system.cpu0.kern.syscall::92                        7      3.47%     96.04% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.99%     97.03% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.99%     98.02% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.50%     98.51% # number of syscalls executed
system.cpu0.kern.syscall::144                       1      0.50%     99.01% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.99%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   202                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  359      0.22%      0.22% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.22% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.22% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.23% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3342      2.08%      2.30% # number of callpals executed
system.cpu0.kern.callpal::tbi                      48      0.03%      2.33% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.33% # number of callpals executed
system.cpu0.kern.callpal::swpipl               146221     90.79%     93.12% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6169      3.83%     96.95% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.95% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     96.95% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     8      0.00%     96.96% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.96% # number of callpals executed
system.cpu0.kern.callpal::rti                    4425      2.75%     99.71% # number of callpals executed
system.cpu0.kern.callpal::callsys                 333      0.21%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     137      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                161059                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             6926                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1257                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1256                      
system.cpu0.kern.mode_good::user                 1257                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.181346                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.307100                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1898828643000     99.90%     99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          1898207000      0.10%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3343                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2523                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     64668                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   20885     37.61%     37.61% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1927      3.47%     41.08% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    359      0.65%     41.72% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  32365     58.28%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               55536                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    20372     47.74%     47.74% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1927      4.52%     52.26% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     359      0.84%     53.10% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   20014     46.90%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                42672                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1875010715500     98.66%     98.66% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              532408500      0.03%     98.69% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              162327000      0.01%     98.70% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            24731034000      1.30%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1900436485000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.975437                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.618384                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.768366                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2                         1      0.81%      0.81% # number of syscalls executed
system.cpu1.kern.syscall::3                        14     11.29%     12.10% # number of syscalls executed
system.cpu1.kern.syscall::6                        13     10.48%     22.58% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.81%     23.39% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      4.84%     28.23% # number of syscalls executed
system.cpu1.kern.syscall::19                        3      2.42%     30.65% # number of syscalls executed
system.cpu1.kern.syscall::20                        2      1.61%     32.26% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.42%     34.68% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.42%     37.10% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      3.23%     40.32% # number of syscalls executed
system.cpu1.kern.syscall::45                       20     16.13%     56.45% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.42%     58.87% # number of syscalls executed
system.cpu1.kern.syscall::48                        2      1.61%     60.48% # number of syscalls executed
system.cpu1.kern.syscall::54                        1      0.81%     61.29% # number of syscalls executed
system.cpu1.kern.syscall::59                        2      1.61%     62.90% # number of syscalls executed
system.cpu1.kern.syscall::71                       29     23.39%     86.29% # number of syscalls executed
system.cpu1.kern.syscall::74                       10      8.06%     94.35% # number of syscalls executed
system.cpu1.kern.syscall::90                        1      0.81%     95.16% # number of syscalls executed
system.cpu1.kern.syscall::92                        2      1.61%     96.77% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.42%     99.19% # number of syscalls executed
system.cpu1.kern.syscall::144                       1      0.81%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   124                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  255      0.44%      0.44% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.45% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.45% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 1393      2.41%      2.86% # number of callpals executed
system.cpu1.kern.callpal::tbi                       6      0.01%      2.87% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      2.88% # number of callpals executed
system.cpu1.kern.callpal::swpipl                49964     86.52%     89.41% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2595      4.49%     93.90% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.90% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     93.91% # number of callpals executed
system.cpu1.kern.callpal::rdusp                     1      0.00%     93.91% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     93.91% # number of callpals executed
system.cpu1.kern.callpal::rti                    3286      5.69%     99.61% # number of callpals executed
system.cpu1.kern.callpal::callsys                 184      0.32%     99.92% # number of callpals executed
system.cpu1.kern.callpal::imb                      43      0.07%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 57746                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             1619                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                488                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2559                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                771                      
system.cpu1.kern.mode_good::user                  488                      
system.cpu1.kern.mode_good::idle                  283                      
system.cpu1.kern.mode_switch_good::kernel     0.476220                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.110590                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.330476                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        5768410500      0.30%      0.30% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           833727500      0.04%      0.35% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1893823776000     99.65%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    1394                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------