path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.924156                       # Number of seconds simulated
sim_ticks                                1924156135000                       # Number of ticks simulated
final_tick                               1924156135000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 131013                       # Simulator instruction rate (inst/s)
host_op_rate                                   131013                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4442767791                       # Simulator tick rate (ticks/s)
host_mem_usage                                 340636                       # Number of bytes of host memory used
host_seconds                                   433.10                       # Real time elapsed on the host
sim_insts                                    56741431                       # Number of instructions simulated
sim_ops                                      56741431                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst           858624                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24610432                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           114304                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           675520                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             26259840                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       858624                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       114304                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          972928                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7862976                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7862976                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             13416                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            384538                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1786                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             10555                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                410310                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          122859                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               122859                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              446234                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12790247                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               59405                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              351073                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               499                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13647458                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         446234                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          59405                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             505639                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4086454                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4086454                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4086454                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             446234                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12790247                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              59405                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             351073                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide              499                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               17733912                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        410310                       # Number of read requests accepted
system.physmem.writeReqs                       122859                       # Number of write requests accepted
system.physmem.readBursts                      410310                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     122859                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 26253184                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6656                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7861568                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  26259840                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7862976                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      104                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               26222                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25818                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25998                       # Per bank write bursts
system.physmem.perBankRdBursts::3               25425                       # Per bank write bursts
system.physmem.perBankRdBursts::4               25236                       # Per bank write bursts
system.physmem.perBankRdBursts::5               25660                       # Per bank write bursts
system.physmem.perBankRdBursts::6               25903                       # Per bank write bursts
system.physmem.perBankRdBursts::7               25509                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25730                       # Per bank write bursts
system.physmem.perBankRdBursts::9               25899                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25820                       # Per bank write bursts
system.physmem.perBankRdBursts::11              25243                       # Per bank write bursts
system.physmem.perBankRdBursts::12              25580                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25319                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25297                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25547                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8465                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7798                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8098                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7477                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7191                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7211                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7415                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7062                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7370                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7621                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7713                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7334                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7954                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8039                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8051                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8038                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          15                       # Number of times write queue was full causing retry
system.physmem.totGap                    1924155087500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  410310                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 122859                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    318040                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     37920                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     29346                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     24786                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        90                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        14                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1668                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3015                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4600                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6208                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6694                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7242                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6798                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8748                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7762                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8489                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8781                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7815                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6077                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      339                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      240                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       41                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65042                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      524.503429                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     321.000815                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     410.854297                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          14739     22.66%     22.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        11347     17.45%     40.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5326      8.19%     48.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2916      4.48%     52.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2591      3.98%     56.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1650      2.54%     59.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         3760      5.78%     65.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1191      1.83%     66.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        21522     33.09%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65042                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5512                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        74.419267                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2843.464031                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           5509     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5512                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5512                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.285377                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.129455                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       20.189692                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23            4905     88.99%     88.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31              46      0.83%     89.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39              19      0.34%     90.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47              46      0.83%     91.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55             202      3.66%     94.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63               8      0.15%     94.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71               9      0.16%     94.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79              26      0.47%     95.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87             191      3.47%     98.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95               5      0.09%     99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103              5      0.09%     99.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111             4      0.07%     99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119             3      0.05%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135             9      0.16%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143             5      0.09%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167             2      0.04%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175             5      0.09%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             8      0.15%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             4      0.07%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199             3      0.05%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             2      0.04%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             1      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255             1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             2      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5512                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4435069250                       # Total ticks spent queuing
system.physmem.totMemAccLat               12126431750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2051030000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10811.81                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29561.81                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.64                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           4.09                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.65                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        4.09                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         2.26                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.01                       # Average write queue length when enqueuing
system.physmem.readRowHits                     369385                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     98616                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.05                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.27                       # Row buffer hit rate for writes
system.physmem.avgGap                      3608902.78                       # Average gap between requests
system.physmem.pageHitRate                      87.79                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  245503440                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  133955250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1605013800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                393446160                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           125676364320                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            63335469060                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1098934930500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1290324682530                       # Total energy per rank (pJ)
system.physmem_0.averagePower              670.593273                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   1827969159500                       # Time in different power states
system.physmem_0.memoryStateTime::REF     64251720000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     31933066750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  246214080                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  134343000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1594593000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                402537600                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           125676364320                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            62736550965                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1099460297250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1290250900215                       # Total energy per rank (pJ)
system.physmem_1.averagePower              670.554927                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   1828845452000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     64251720000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     31056774250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu0.branchPred.lookups               15943421                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         13949758                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           305064                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            10079074                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                5240379                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            51.992663                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 792227                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             17177                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     9007287                       # DTB read hits
system.cpu0.dtb.read_misses                     30074                       # DTB read misses
system.cpu0.dtb.read_acv                          538                       # DTB read access violations
system.cpu0.dtb.read_accesses                  622567                       # DTB read accesses
system.cpu0.dtb.write_hits                    5740520                       # DTB write hits
system.cpu0.dtb.write_misses                     6136                       # DTB write misses
system.cpu0.dtb.write_acv                         351                       # DTB write access violations
system.cpu0.dtb.write_accesses                 205436                       # DTB write accesses
system.cpu0.dtb.data_hits                    14747807                       # DTB hits
system.cpu0.dtb.data_misses                     36210                       # DTB misses
system.cpu0.dtb.data_acv                          889                       # DTB access violations
system.cpu0.dtb.data_accesses                  828003                       # DTB accesses
system.cpu0.itb.fetch_hits                    1373369                       # ITB hits
system.cpu0.itb.fetch_misses                    18540                       # ITB misses
system.cpu0.itb.fetch_acv                         561                       # ITB acv
system.cpu0.itb.fetch_accesses                1391909                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       146208045                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          26065681                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      69138767                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   15943421                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           6032606                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    111931288                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1030760                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                       960                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               29091                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       863166                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       466353                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          499                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  7979260                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               223234                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples         139872418                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.494299                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.727987                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               126942613     90.76%     90.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  822727      0.59%     91.34% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1793626      1.28%     92.63% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  758856      0.54%     93.17% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2553230      1.83%     94.99% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  559004      0.40%     95.39% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  640050      0.46%     95.85% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  814516      0.58%     96.43% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4987796      3.57%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           139872418                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.109046                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.472879                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                21051176                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            108291493                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  8312277                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1736520                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                480951                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              505721                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                34877                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              60486220                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               106478                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                480951                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                21868372                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               77772833                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      19641346                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  9147803                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             10961111                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              58426169                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents               200234                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               2003921                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                229197                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               7028864                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           39061354                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             71018610                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        70882139                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           127236                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             34481529                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 4579825                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1435923                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        207898                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 12319734                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             9087403                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6005193                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1334507                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores          982358                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  52110504                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1852436                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 51364410                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            50265                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6320051                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      2764098                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1275155                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    139872418                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.367223                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.083437                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          118742134     84.89%     84.89% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            9166235      6.55%     91.45% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3802026      2.72%     94.16% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2678681      1.92%     96.08% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2780722      1.99%     98.07% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1354022      0.97%     99.04% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             885059      0.63%     99.67% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             353584      0.25%     99.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             109955      0.08%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      139872418                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                 178057     18.55%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     2      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     18.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                457973     47.71%     66.26% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               323912     33.74%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             3341      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             35317882     68.76%     68.77% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               56025      0.11%     68.88% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.88% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              27459      0.05%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1664      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.93% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9346041     18.20%     87.13% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5809377     11.31%     98.44% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            802621      1.56%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              51364410                       # Type of FU issued
system.cpu0.iq.rate                          0.351310                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     959944                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.018689                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         243048711                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         60036028                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     50017442                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             562736                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            263720                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       258274                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              52017534                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 303479                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          574771                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1026959                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         3812                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        17061                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       487007                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        18708                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       390954                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                480951                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               74383875                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               944737                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           57300574                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           113056                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              9087403                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6005193                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1637090                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 39248                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents               704660                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         17061                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        148957                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       344315                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              493272                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             50873166                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9059669                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           491244                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      3337634                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14819622                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 8093106                       # Number of branches executed
system.cpu0.iew.exec_stores                   5759953                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.347951                       # Inst execution rate
system.cpu0.iew.wb_sent                      50383521                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     50275716                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 25952077                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 35940166                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.343864                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.722091                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts        6643709                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         577281                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           452311                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    138699255                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.364540                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.252346                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    120842585     87.13%     87.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      7068214      5.10%     92.22% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      3896866      2.81%     95.03% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2026273      1.46%     96.49% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1580895      1.14%     97.63% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       566091      0.41%     98.04% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       426311      0.31%     98.35% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       427447      0.31%     98.66% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1864573      1.34%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    138699255                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            50561379                       # Number of instructions committed
system.cpu0.commit.committedOps              50561379                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      13578630                       # Number of memory references committed
system.cpu0.commit.loads                      8060444                       # Number of loads committed
system.cpu0.commit.membars                     196368                       # Number of memory barriers committed
system.cpu0.commit.branches                   7652854                       # Number of branches committed
system.cpu0.commit.fp_insts                    255352                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 46813547                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              647795                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass      2921820      5.78%      5.78% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        32972422     65.21%     70.99% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          54875      0.11%     71.10% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     71.10% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd         26997      0.05%     71.15% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     71.15% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     71.15% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     71.15% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv          1664      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.16% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead        8256812     16.33%     87.49% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite       5524169     10.93%     98.41% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess       802620      1.59%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         50561379                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1864573                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                   193850877                       # The number of ROB reads
system.cpu0.rob.rob_writes                  115577492                       # The number of ROB writes
system.cpu0.timesIdled                         518122                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        6335627                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3701455446                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   47642888                       # Number of Instructions Simulated
system.cpu0.committedOps                     47642888                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              3.068833                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        3.068833                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.325857                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.325857                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                66867100                       # number of integer regfile reads
system.cpu0.int_regfile_writes               36418674                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   126247                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  127860                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1687235                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                805033                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements          1264949                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          506.087207                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           10332814                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1265389                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs             8.165721                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         36569500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.087207                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988452                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.988452                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          440                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          424                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3           16                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.859375                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         55743901                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        55743901                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      6363552                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6363552                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3619661                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3619661                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       160076                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       160076                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       184973                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       184973                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      9983213                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         9983213                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      9983213                       # number of overall hits
system.cpu0.dcache.overall_hits::total        9983213                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1569683                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1569683                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1696149                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1696149                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20607                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        20607                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2893                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         2893                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3265832                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3265832                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3265832                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3265832                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  54492082500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  54492082500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 110535541459                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 110535541459                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    385765500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    385765500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     44605000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     44605000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 165027623959                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 165027623959                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 165027623959                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 165027623959                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7933235                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      7933235                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5315810                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5315810                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       180683                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       180683                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       187866                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       187866                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     13249045                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     13249045                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     13249045                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     13249045                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.197862                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.197862                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.319076                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.319076                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.114051                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.114051                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.015399                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.015399                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.246496                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.246496                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.246496                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.246496                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34715.342206                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 34715.342206                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65168.532634                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 65168.532634                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18720.119377                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18720.119377                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15418.250951                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15418.250951                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50531.571728                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 50531.571728                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50531.571728                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 50531.571728                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      6758088                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        13420                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           113551                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets             96                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    59.515883                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   139.791667                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       742386                       # number of writebacks
system.cpu0.dcache.writebacks::total           742386                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       562218                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       562218                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1439926                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1439926                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4884                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4884                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      2002144                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      2002144                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      2002144                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      2002144                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1007465                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      1007465                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       256223                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       256223                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        15723                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        15723                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2893                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         2893                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1263688                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1263688                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1263688                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1263688                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7031                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7031                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10093                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10093                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17124                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17124                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43361344000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  43361344000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  17653250388                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  17653250388                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    186143500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    186143500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     41712000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     41712000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  61014594388                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  61014594388                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  61014594388                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  61014594388                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1559676000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1559676000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2293857500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2293857500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3853533500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3853533500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.126993                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.126993                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048200                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048200                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.087020                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.087020                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.015399                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.015399                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.095380                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.095380                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.095380                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.095380                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 43040.050027                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 43040.050027                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68897.992717                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68897.992717                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11838.930230                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11838.930230                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14418.250951                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14418.250951                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48282.957809                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48282.957809                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48282.957809                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48282.957809                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221828.473901                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221828.473901                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227272.119291                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227272.119291                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 225036.994861                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225036.994861                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements           894689                       # number of replacements
system.cpu0.icache.tags.tagsinuse          508.080310                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs            7039625                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           895201                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs             7.863737                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      42372449500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.080310                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992344                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.992344                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          507                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses          8874714                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses         8874714                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst      7039625                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        7039625                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      7039625                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         7039625                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      7039625                       # number of overall hits
system.cpu0.icache.overall_hits::total        7039625                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       939633                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       939633                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       939633                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        939633                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       939633                       # number of overall misses
system.cpu0.icache.overall_misses::total       939633                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14412797481                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  14412797481                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  14412797481                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  14412797481                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  14412797481                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  14412797481                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      7979258                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      7979258                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      7979258                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      7979258                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      7979258                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      7979258                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.117759                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.117759                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.117759                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.117759                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.117759                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.117759                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15338.751918                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 15338.751918                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15338.751918                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 15338.751918                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15338.751918                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 15338.751918                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         9737                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              297                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    32.784512                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks       894689                       # number of writebacks
system.cpu0.icache.writebacks::total           894689                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        44177                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        44177                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        44177                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        44177                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        44177                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        44177                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       895456                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       895456                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       895456                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       895456                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       895456                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       895456                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12742984487                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  12742984487                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12742984487                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  12742984487                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12742984487                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  12742984487                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.112223                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.112223                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.112223                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.112223                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.112223                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.112223                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14230.720981                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14230.720981                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14230.720981                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 14230.720981                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14230.720981                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 14230.720981                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                3770405                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          3287478                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect            72852                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             2172402                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                 929208                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            42.773299                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 184259                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect              5155                       # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     2058998                       # DTB read hits
system.cpu1.dtb.read_misses                     11600                       # DTB read misses
system.cpu1.dtb.read_acv                           21                       # DTB read access violations
system.cpu1.dtb.read_accesses                  345698                       # DTB read accesses
system.cpu1.dtb.write_hits                    1317225                       # DTB write hits
system.cpu1.dtb.write_misses                     3094                       # DTB write misses
system.cpu1.dtb.write_acv                          53                       # DTB write access violations
system.cpu1.dtb.write_accesses                 138357                       # DTB write accesses
system.cpu1.dtb.data_hits                     3376223                       # DTB hits
system.cpu1.dtb.data_misses                     14694                       # DTB misses
system.cpu1.dtb.data_acv                           74                       # DTB access violations
system.cpu1.dtb.data_accesses                  484055                       # DTB accesses
system.cpu1.itb.fetch_hits                     573986                       # ITB hits
system.cpu1.itb.fetch_misses                     6844                       # ITB misses
system.cpu1.itb.fetch_acv                         105                       # ITB acv
system.cpu1.itb.fetch_accesses                 580830                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                        16344557                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles           6567420                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      14895137                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    3770405                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           1113467                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      8326976                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 284690                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                       333                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles               25529                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles       274833                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        63331                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles           18                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  1681040                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                57489                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples          15400785                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.967167                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.371525                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                12783684     83.01%     83.01% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  166452      1.08%     84.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  261215      1.70%     85.78% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  200313      1.30%     87.08% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  351067      2.28%     89.36% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  133990      0.87%     90.23% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  151147      0.98%     91.22% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  199120      1.29%     92.51% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 1153797      7.49%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            15400785                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.230683                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.911321                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 5395420                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles              7755332                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  1888719                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               226049                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                135264                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              116204                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                 7167                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              12211095                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                22842                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                135264                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 5551383                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                 663921                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       5888186                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  1958901                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              1203128                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              11612321                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 4312                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 84745                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                 20732                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents                660077                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands            7621170                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups             13919150                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        13857621                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            55424                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps              6464282                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 1156880                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            465120                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         44099                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  2006629                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             2105779                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            1396456                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           250989                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          150424                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  10250493                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             528025                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 10010931                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            21465                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        1679970                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined       786543                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        387236                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     15400785                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.650027                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.374650                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           11244282     73.01%     73.01% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            1815288     11.79%     84.80% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2             776099      5.04%     89.84% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             545502      3.54%     93.38% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             489702      3.18%     96.56% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             259974      1.69%     98.25% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             169251      1.10%     99.35% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7              72741      0.47%     99.82% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              27946      0.18%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       15400785                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  26802      9.62%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                149738     53.73%     63.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               102168     36.66%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             3957      0.04%      0.04% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              6209301     62.03%     62.06% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               16861      0.17%     62.23% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd              11959      0.12%     62.35% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.35% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.35% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.35% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1978      0.02%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.37% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             2148593     21.46%     83.83% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            1341864     13.40%     97.24% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            276418      2.76%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              10010931                       # Type of FU issued
system.cpu1.iq.rate                          0.612493                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     278708                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.027840                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          35509985                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         12361464                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses      9636562                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads             212834                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            101438                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses        98868                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              10172012                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 113670                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          100974                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       300733                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          901                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         4546                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       138575                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads          436                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        85477                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                135264                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 341224                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               281245                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           11333478                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts            30763                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              2105779                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             1396456                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            478482                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                  4958                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents               275268                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          4546                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         33466                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       102178                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              135644                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts              9885056                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              2078095                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           125874                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       554960                       # number of nop insts executed
system.cpu1.iew.exec_refs                     3404439                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 1465257                       # Number of branches executed
system.cpu1.iew.exec_stores                   1326344                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.604792                       # Inst execution rate
system.cpu1.iew.wb_sent                       9770196                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                      9735430                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  4636977                       # num instructions producing a value
system.cpu1.iew.wb_consumers                  6583946                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.595637                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.704285                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts        1707241                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         140789                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           123833                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     15089302                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.633097                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.610231                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     11642359     77.16%     77.16% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      1582874     10.49%     87.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2       578528      3.83%     91.48% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       347459      2.30%     93.78% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       270616      1.79%     95.58% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       111368      0.74%     96.31% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       102382      0.68%     96.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       112638      0.75%     97.74% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       341078      2.26%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     15089302                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts             9552993                       # Number of instructions committed
system.cpu1.commit.committedOps               9552993                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       3062927                       # Number of memory references committed
system.cpu1.commit.loads                      1805046                       # Number of loads committed
system.cpu1.commit.membars                      44912                       # Number of memory barriers committed
system.cpu1.commit.branches                   1363215                       # Number of branches committed
system.cpu1.commit.fp_insts                     97092                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                  8861525                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              149395                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass       458406      4.80%      4.80% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu         5679268     59.45%     64.25% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          16577      0.17%     64.42% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.42% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd         11953      0.13%     64.55% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.55% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.55% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.55% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv          1978      0.02%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.57% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead        1849958     19.37%     83.93% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite       1258435     13.17%     97.11% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess       276418      2.89%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total          9552993                       # Class of committed instruction
system.cpu1.commit.bw_lim_events               341078                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                    25912274                       # The number of ROB reads
system.cpu1.rob.rob_writes                   22828201                       # The number of ROB writes
system.cpu1.timesIdled                         132318                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                         943772                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3831967714                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                    9098543                       # Number of Instructions Simulated
system.cpu1.committedOps                      9098543                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.796393                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.796393                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.556671                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.556671                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                12770865                       # number of integer regfile reads
system.cpu1.int_regfile_writes                6910748                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    54739                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   53934                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 528553                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                224621                       # number of misc regfile writes
system.cpu1.dcache.tags.replacements           116660                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          487.079416                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            2668588                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           117172                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            22.774963                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     1048837209000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   487.079416                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.951327                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.951327                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          216                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          248                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         12701896                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        12701896                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      1640446                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1640446                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data       950506                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        950506                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        34609                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        34609                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        32422                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        32422                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      2590952                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         2590952                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      2590952                       # number of overall hits
system.cpu1.dcache.overall_hits::total        2590952                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       211694                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       211694                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       265779                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       265779                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         5362                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         5362                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data         3043                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         3043                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       477473                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        477473                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       477473                       # number of overall misses
system.cpu1.dcache.overall_misses::total       477473                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2807776500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2807776500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  12432535778                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  12432535778                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     52442500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     52442500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     46465500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     46465500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  15240312278                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  15240312278                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  15240312278                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  15240312278                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      1852140                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      1852140                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      1216285                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1216285                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        39971                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        39971                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        35465                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        35465                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      3068425                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      3068425                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      3068425                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      3068425                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.114297                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.114297                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.218517                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.218517                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.134147                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.134147                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.085803                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.085803                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.155608                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.155608                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.155608                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.155608                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13263.373076                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13263.373076                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46777.720505                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 46777.720505                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9780.399105                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9780.399105                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15269.635228                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15269.635228                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31918.689178                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 31918.689178                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31918.689178                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 31918.689178                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs       748281                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets         2150                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs            22290                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets             12                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    33.570256                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets   179.166667                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks        77506                       # number of writebacks
system.cpu1.dcache.writebacks::total            77506                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       130194                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       130194                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       220941                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       220941                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          639                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total          639                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       351135                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       351135                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       351135                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       351135                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        81500                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total        81500                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        44838                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        44838                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4723                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4723                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         3042                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total         3042                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       126338                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       126338                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       126338                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       126338                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          162                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total          162                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2978                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2978                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3140                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3140                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1028731500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1028731500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2065280441                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2065280441                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     40973500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     40973500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     43423500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     43423500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3094011941                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   3094011941                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3094011941                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   3094011941                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     32188500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     32188500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    693701000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    693701000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    725889500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    725889500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.044003                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.044003                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036865                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036865                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.118161                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.118161                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.085775                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.085775                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.041174                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.041174                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.041174                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.041174                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12622.472393                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12622.472393                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46060.940296                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46060.940296                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8675.312302                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8675.312302                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14274.654832                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14274.654832                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24489.955049                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24489.955049                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24489.955049                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24489.955049                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198694.444444                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198694.444444                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 232941.907320                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 232941.907320                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data       231175                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total       231175                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           236774                       # number of replacements
system.cpu1.icache.tags.tagsinuse          467.367156                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            1435165                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           237286                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs             6.048250                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     1897657857500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   467.367156                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.912826                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.912826                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          428                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses          1918394                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses         1918394                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      1435165                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        1435165                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      1435165                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         1435165                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      1435165                       # number of overall hits
system.cpu1.icache.overall_hits::total        1435165                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       245875                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       245875                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       245875                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        245875                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       245875                       # number of overall misses
system.cpu1.icache.overall_misses::total       245875                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   3543557000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   3543557000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   3543557000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   3543557000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   3543557000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   3543557000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      1681040                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      1681040                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      1681040                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      1681040                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      1681040                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      1681040                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.146264                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.146264                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.146264                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.146264                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.146264                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.146264                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14412.026436                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14412.026436                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14412.026436                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14412.026436                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14412.026436                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14412.026436                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs          967                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               47                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    20.574468                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks       236774                       # number of writebacks
system.cpu1.icache.writebacks::total           236774                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         8521                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total         8521                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst         8521                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total         8521                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst         8521                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total         8521                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       237354                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       237354                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       237354                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       237354                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       237354                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       237354                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3178535500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   3178535500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3178535500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   3178535500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3178535500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   3178535500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.141195                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.141195                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.141195                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.141195                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.141195                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.141195                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13391.539641                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13391.539641                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13391.539641                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13391.539641                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13391.539641                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13391.539641                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq                 7368                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7368                       # Transaction distribution
system.iobus.trans_dist::WriteReq               54623                       # Transaction distribution
system.iobus.trans_dist::WriteResp              54623                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11936                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1002                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        40528                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83454                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83454                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  123982                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        47744                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2701                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total        73938                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661624                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total      2661624                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2735562                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             12379500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               818500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              177500                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            14310000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             2829000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5965001                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy               87000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           215710405                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            27457000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            41950000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41695                       # number of replacements
system.iocache.tags.tagsinuse                0.518954                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41711                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1726981777000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     0.518954                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.032435                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.032435                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375543                       # Number of tag accesses
system.iocache.tags.data_accesses              375543                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          175                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
system.iocache.demand_misses::tsunami.ide          175                       # number of demand (read+write) misses
system.iocache.demand_misses::total               175                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide          175                       # number of overall misses
system.iocache.overall_misses::total              175                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     23088383                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     23088383                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide   5246547022                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   5246547022                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide     23088383                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     23088383                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide     23088383                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     23088383                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          175                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide          175                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             175                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide          175                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            175                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 131933.617143                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 131933.617143                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126264.608731                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126264.608731                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 131933.617143                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 131933.617143                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 131933.617143                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 131933.617143                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    1                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs            0                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          175                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          175                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide          175                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          175                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide          175                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          175                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     14338383                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     14338383                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3167138735                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3167138735                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide     14338383                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     14338383                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide     14338383                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     14338383                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81933.617143                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 81933.617143                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76221.090080                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76221.090080                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 81933.617143                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 81933.617143                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 81933.617143                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 81933.617143                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   345132                       # number of replacements
system.l2c.tags.tagsinuse                65190.773198                       # Cycle average of tags in use
system.l2c.tags.total_refs                    3987579                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   410285                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     9.719047                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              11177481000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   53112.873337                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5260.284322                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     6538.875697                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      210.626415                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data       68.113427                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.810438                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.080266                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.099775                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.003214                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.001039                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.994732                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        65153                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          214                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1         3005                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         4362                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5957                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        51615                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.994156                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 38355291                       # Number of tag accesses
system.l2c.tags.data_accesses                38355291                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks       819892                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          819892                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks       858364                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total          858364                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data             165                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             273                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 438                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            47                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            30                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                77                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           148311                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            29871                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               178182                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        881771                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        235510                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1117281                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       728849                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data        74394                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           803243                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst              881771                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              877160                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              235510                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              104265                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2098706                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             881771                       # number of overall hits
system.l2c.overall_hits::cpu0.data             877160                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             235510                       # number of overall hits
system.l2c.overall_hits::cpu1.data             104265                       # number of overall hits
system.l2c.overall_hits::total                2098706                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          2745                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1129                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3874                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          421                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          438                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             859                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         112211                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           9825                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             122036                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        13418                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst         1804                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           15222                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       272977                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data          837                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         273814                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst             13418                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            385188                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1804                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             10662                       # number of demand (read+write) misses
system.l2c.demand_misses::total                411072                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            13418                       # number of overall misses
system.l2c.overall_misses::cpu0.data           385188                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1804                       # number of overall misses
system.l2c.overall_misses::cpu1.data            10662                       # number of overall misses
system.l2c.overall_misses::total               411072                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data      2600000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     16721000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     19321000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      2754000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       393500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3147500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  15556825000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1578015500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  17134840500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1793058000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    243367000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   2036425000                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  33886643500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    118714500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  34005358000                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1793058000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  49443468500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    243367000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1696730000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     53176623500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1793058000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  49443468500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    243367000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1696730000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    53176623500                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       819892                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       819892                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks       858364                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total       858364                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2910                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1402                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            4312                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          468                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          468                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           936                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       260522                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        39696                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           300218                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       895189                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       237314                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1132503                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      1001826                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        75231                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      1077057                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          895189                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1262348                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          237314                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          114927                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2509778                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         895189                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1262348                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         237314                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         114927                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2509778                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.943299                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.805278                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.898423                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.899573                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.935897                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.917735                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.430716                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.247506                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.406491                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.014989                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.007602                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.013441                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.272479                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.011126                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.254224                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.014989                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.305136                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.007602                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.092772                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.163788                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.014989                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.305136                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.007602                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.092772                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.163788                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   947.176685                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14810.451727                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  4987.351575                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6541.567696                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   898.401826                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3664.144354                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138639.037171                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 160612.264631                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 140408.080403                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133630.794455                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 134904.101996                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 133781.697543                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 124137.357726                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141833.333333                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 124191.451131                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 133630.794455                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 128361.912884                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 134904.101996                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 159138.060401                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 129360.850411                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 133630.794455                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 128361.912884                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 134904.101996                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 159138.060401                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 129360.850411                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               81339                       # number of writebacks
system.l2c.writebacks::total                    81339                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst           18                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           19                       # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             18                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 19                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            18                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                19                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks           11                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total           11                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2745                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1129                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3874                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          421                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          438                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          859                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       112211                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         9825                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        122036                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        13417                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1786                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        15203                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       272977                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data          837                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       273814                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        13417                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       385188                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1786                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        10662                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           411053                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        13417                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       385188                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1786                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        10662                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          411053                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.data         7031                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data          162                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total         7193                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        10093                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2978                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        13071                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        17124                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         3140                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        20264                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    189141000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     77954000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    267095000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     28855000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     30191500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     59046500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  14434715000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1479761518                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  15914476518                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1658755004                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    223319004                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   1882074008                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  31166738507                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    110342008                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  31277080515                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1658755004                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  45601453507                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    223319004                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1590103526                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  49073631041                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1658755004                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  45601453507                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    223319004                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1590103526                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  49073631041                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1471729000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     30152500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1501881500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2177586500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    657605500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2835192000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3649315500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    687758000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   4337073500                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.943299                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.805278                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.898423                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.899573                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.935897                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.917735                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.430716                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.247506                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.406491                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.014988                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.007526                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013424                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.272479                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.011126                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.254224                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014988                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.305136                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007526                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.092772                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.163781                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014988                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.305136                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007526                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.092772                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.163781                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68903.825137                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 69046.944198                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68945.534331                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68539.192399                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68930.365297                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68738.649593                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128639.037171                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 150611.859338                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 130408.047773                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123630.841768                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125038.636058                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123796.224956                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114173.496328                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131830.356033                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114227.470162                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123630.841768                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118387.523773                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125038.636058                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 149137.453198                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 119385.166976                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123630.841768                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118387.523773                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125038.636058                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 149137.453198                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 119385.166976                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209320.011378                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186126.543210                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208797.650494                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215752.154959                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220821.188717                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216907.046133                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213111.159776                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 219031.210191                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 214028.498816                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq                7193                       # Transaction distribution
system.membus.trans_dist::ReadResp             296309                       # Transaction distribution
system.membus.trans_dist::WriteReq              13071                       # Transaction distribution
system.membus.trans_dist::WriteResp             13071                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       122859                       # Transaction distribution
system.membus.trans_dist::CleanEvict           263080                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            10389                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq           5858                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
system.membus.trans_dist::ReadExReq            122048                       # Transaction distribution
system.membus.trans_dist::ReadExResp           121637                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        289192                       # Transaction distribution
system.membus.trans_dist::BadAddressError           76                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40528                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1181775                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          152                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      1222455                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83437                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        83437                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1305892                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        73938                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31464576                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     31538514                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658240                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2658240                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                34196754                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            11972                       # Total snoops (count)
system.membus.snoop_fanout::samples            875257                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  875257    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              875257                       # Request fanout histogram
system.membus.reqLayer0.occupancy            36588499                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1355446474                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer2.occupancy              101000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2176763250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy             924363                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests      5062297                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2530952                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       339931                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           1332                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         1264                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops           68                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq               7193                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2238586                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             13071                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            13071                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       942766                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean      1131462                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          825685                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           10428                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq          5935                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          16363                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           301553                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          301553                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1132810                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      1098675                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError           76                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2685333                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3847367                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       711442                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       373868                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7618010                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    114552128                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    128359012                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     30341632                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     12338926                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              285591698                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          462928                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          2998059                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.119755                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.324954                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                2639295     88.03%     88.03% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 358495     11.96%     99.99% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    268      0.01%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                      1      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            2998059                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         4499211916                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           295885                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1344759827                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1928238108                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         358125739                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         195506142                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6521                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    181676                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   64229     40.40%     40.40% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.08%     40.49% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1930      1.21%     41.70% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    188      0.12%     41.82% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  92486     58.18%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              158964                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    63227     49.20%     49.20% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.10%     49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1930      1.50%     50.80% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     188      0.15%     50.95% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   63039     49.05%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               128515                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1866746585000     97.03%     97.03% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               63847000      0.00%     97.04% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              578525000      0.03%     97.07% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30               89345000      0.00%     97.07% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            56353429000      2.93%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1923831731000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.984400                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.681606                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.808453                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         7      3.65%      3.65% # number of syscalls executed
system.cpu0.kern.syscall::3                        16      8.33%     11.98% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      2.08%     14.06% # number of syscalls executed
system.cpu0.kern.syscall::6                        28     14.58%     28.65% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.52%     29.17% # number of syscalls executed
system.cpu0.kern.syscall::17                        8      4.17%     33.33% # number of syscalls executed
system.cpu0.kern.syscall::19                        7      3.65%     36.98% # number of syscalls executed
system.cpu0.kern.syscall::20                        4      2.08%     39.06% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.52%     39.58% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.56%     41.15% # number of syscalls executed
system.cpu0.kern.syscall::33                        6      3.12%     44.27% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      1.04%     45.31% # number of syscalls executed
system.cpu0.kern.syscall::45                       31     16.15%     61.46% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.56%     63.02% # number of syscalls executed
system.cpu0.kern.syscall::48                        8      4.17%     67.19% # number of syscalls executed
system.cpu0.kern.syscall::54                        9      4.69%     71.88% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.52%     72.40% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      3.12%     75.52% # number of syscalls executed
system.cpu0.kern.syscall::71                       21     10.94%     86.46% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.56%     88.02% # number of syscalls executed
system.cpu0.kern.syscall::74                        5      2.60%     90.62% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.52%     91.15% # number of syscalls executed
system.cpu0.kern.syscall::90                        2      1.04%     92.19% # number of syscalls executed
system.cpu0.kern.syscall::92                        7      3.65%     95.83% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      1.04%     96.88% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      1.04%     97.92% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.52%     98.44% # number of syscalls executed
system.cpu0.kern.syscall::144                       1      0.52%     98.96% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      1.04%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   192                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  288      0.17%      0.17% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.17% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.17% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.17% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3442      2.06%      2.23% # number of callpals executed
system.cpu0.kern.callpal::tbi                      49      0.03%      2.26% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.27% # number of callpals executed
system.cpu0.kern.callpal::swpipl               152297     91.02%     93.29% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6331      3.78%     97.07% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.07% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     2      0.00%     97.07% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     8      0.00%     97.08% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     97.08% # number of callpals executed
system.cpu0.kern.callpal::rti                    4417      2.64%     99.72% # number of callpals executed
system.cpu0.kern.callpal::callsys                 330      0.20%     99.92% # number of callpals executed
system.cpu0.kern.callpal::imb                     139      0.08%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                167317                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             6879                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1175                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1175                      
system.cpu0.kern.mode_good::user                 1175                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.170810                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.291780                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1921452590000     99.89%     99.89% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          2041385500      0.11%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3443                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2563                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     58062                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   18132     36.97%     36.97% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1928      3.93%     40.90% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    288      0.59%     41.49% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  28696     58.51%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               49044                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    17757     47.43%     47.43% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1928      5.15%     52.57% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     288      0.77%     53.34% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   17469     46.66%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                37442                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1877611262500     97.58%     97.58% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              563601000      0.03%     97.61% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              141411000      0.01%     97.62% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            45839038500      2.38%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1924155313000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.979318                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.608761                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.763437                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2                         1      0.75%      0.75% # number of syscalls executed
system.cpu1.kern.syscall::3                        14     10.45%     11.19% # number of syscalls executed
system.cpu1.kern.syscall::6                        14     10.45%     21.64% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.75%     22.39% # number of syscalls executed
system.cpu1.kern.syscall::17                        7      5.22%     27.61% # number of syscalls executed
system.cpu1.kern.syscall::19                        3      2.24%     29.85% # number of syscalls executed
system.cpu1.kern.syscall::20                        2      1.49%     31.34% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.24%     33.58% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.24%     35.82% # number of syscalls executed
system.cpu1.kern.syscall::33                        5      3.73%     39.55% # number of syscalls executed
system.cpu1.kern.syscall::45                       23     17.16%     56.72% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.24%     58.96% # number of syscalls executed
system.cpu1.kern.syscall::48                        2      1.49%     60.45% # number of syscalls executed
system.cpu1.kern.syscall::54                        1      0.75%     61.19% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      0.75%     61.94% # number of syscalls executed
system.cpu1.kern.syscall::71                       33     24.63%     86.57% # number of syscalls executed
system.cpu1.kern.syscall::74                       11      8.21%     94.78% # number of syscalls executed
system.cpu1.kern.syscall::90                        1      0.75%     95.52% # number of syscalls executed
system.cpu1.kern.syscall::92                        2      1.49%     97.01% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.24%     99.25% # number of syscalls executed
system.cpu1.kern.syscall::144                       1      0.75%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   134                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  188      0.37%      0.37% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.37% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.38% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 1149      2.26%      2.64% # number of callpals executed
system.cpu1.kern.callpal::tbi                       4      0.01%      2.64% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      2.66% # number of callpals executed
system.cpu1.kern.callpal::swpipl                43675     85.89%     88.55% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2435      4.79%     93.34% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.34% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     5      0.01%     93.35% # number of callpals executed
system.cpu1.kern.callpal::rdusp                     1      0.00%     93.35% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     93.35% # number of callpals executed
system.cpu1.kern.callpal::rti                    3152      6.20%     99.55% # number of callpals executed
system.cpu1.kern.callpal::callsys                 185      0.36%     99.92% # number of callpals executed
system.cpu1.kern.callpal::imb                      41      0.08%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 50850                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             1515                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                561                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2424                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                773                      
system.cpu1.kern.mode_good::user                  561                      
system.cpu1.kern.mode_good::idle                  212                      
system.cpu1.kern.mode_switch_good::kernel     0.510231                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.087459                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.343556                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        4865757000      0.25%      0.25% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           846470000      0.04%      0.30% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1918443078000     99.70%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    1150                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------