path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.896442                       # Number of seconds simulated
sim_ticks                                1896441913500                       # Number of ticks simulated
final_tick                               1896441913500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 132187                       # Simulator instruction rate (inst/s)
host_op_rate                                   132187                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4418345683                       # Simulator tick rate (ticks/s)
host_mem_usage                                 311512                       # Number of bytes of host memory used
host_seconds                                   429.22                       # Real time elapsed on the host
sim_insts                                    56737124                       # Number of instructions simulated
sim_ops                                      56737124                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst           937984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24915648                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2650688                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            39872                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           337088                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28881280                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       937984                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        39872                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          977856                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7850944                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7850944                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             14656                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            389307                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41417                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst               623                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              5267                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                451270                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          122671                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               122671                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              494602                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            13138102                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1397716                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               21025                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              177748                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15229193                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         494602                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          21025                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             515627                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4139828                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4139828                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4139828                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             494602                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           13138102                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1397716                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              21025                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             177748                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19369021                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        451270                       # Total number of read requests seen
system.physmem.writeReqs                       122671                       # Total number of write requests seen
system.physmem.cpureqs                         578881                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     28881280                       # Total number of bytes read from memory
system.physmem.bytesWritten                   7850944                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               28881280                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7850944                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       67                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               4936                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 28286                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 28331                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 28232                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 28037                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 28769                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 28511                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 28476                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 28312                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 28256                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 28154                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                28207                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                27864                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                27902                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                28010                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                27813                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                28043                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  7715                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  7756                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  7743                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  7541                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  8184                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  7906                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  7897                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  7828                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  7761                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  7702                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 7706                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 7342                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 7423                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 7442                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 7221                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 7504                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           4                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1896440622000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  451270                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                 122671                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    320077                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     59739                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     33398                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      7716                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3200                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2984                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      2709                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      2710                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2673                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2618                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1536                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1465                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1405                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1359                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1357                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1405                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     1629                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                     1501                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      921                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      776                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       16                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      3224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3863                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4392                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4442                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      4963                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5320                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5328                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5330                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5330                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     2110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     1471                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      942                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                      892                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                      371                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        4                       # What write queue length does an incoming req see
system.physmem.totQLat                     7836942250                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat               15642141000                       # Sum of mem lat for all requests
system.physmem.totBusLat                   2256015000                       # Total cycles spent in databus access
system.physmem.totBankLat                  5549183750                       # Total cycles spent in bank access
system.physmem.avgQLat                       17368.99                       # Average queueing delay per request
system.physmem.avgBankLat                    12298.64                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  34667.64                       # Average memory access latency
system.physmem.avgRdBW                          15.23                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           4.14                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  15.23                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   4.14                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.01                       # Average read queue length over time
system.physmem.avgWrQLen                        10.84                       # Average write queue length over time
system.physmem.readRowHits                     423356                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     94009                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.83                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  76.64                       # Row buffer hit rate for writes
system.physmem.avgGap                      3304243.16                       # Average gap between requests
system.l2c.replacements                        344349                       # number of replacements
system.l2c.tagsinuse                     65273.956353                       # Cycle average of tags in use
system.l2c.total_refs                         2577923                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        409542                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          6.294649                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                    5466319751                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        53748.349121                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          5295.726441                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          5975.264441                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst           194.705269                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data            59.911080                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.820135                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.080806                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.091175                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.002971                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.000914                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.996002                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst             875549                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             736473                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             202355                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              65181                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1879558                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          819599                       # number of Writeback hits
system.l2c.Writeback_hits::total               819599                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             179                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             274                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 453                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            44                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            23                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                67                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           155361                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            23678                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               179039                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              875549                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              891834                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              202355                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               88859                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2058597                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             875549                       # number of overall hits
system.l2c.overall_hits::cpu0.data             891834                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             202355                       # number of overall hits
system.l2c.overall_hits::cpu1.data              88859                       # number of overall hits
system.l2c.overall_hits::total                2058597                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            14659                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           273675                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst              639                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data              307                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               289280                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2691                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1055                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3746                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          427                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          465                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             892                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         116250                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           4980                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             121230                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             14659                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            389925                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst               639                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              5287                       # number of demand (read+write) misses
system.l2c.demand_misses::total                410510                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            14659                       # number of overall misses
system.l2c.overall_misses::cpu0.data           389925                       # number of overall misses
system.l2c.overall_misses::cpu1.inst              639                       # number of overall misses
system.l2c.overall_misses::cpu1.data             5287                       # number of overall misses
system.l2c.overall_misses::total               410510                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst   1016905000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  11936684500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     45525000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     24193500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    13023308000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      1127500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      4752997                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      5880497                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       645500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        90500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       736000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   7781459000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    505939000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   8287398000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1016905000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  19718143500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     45525000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    530132500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     21310706000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1016905000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  19718143500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     45525000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    530132500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    21310706000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         890208                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data        1010148                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         202994                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          65488                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2168838                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       819599                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           819599                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2870                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1329                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            4199                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          471                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          488                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           959                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       271611                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        28658                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           300269                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          890208                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1281759                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          202994                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           94146                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2469107                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         890208                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1281759                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         202994                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          94146                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2469107                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.016467                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.270926                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.003148                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.004688                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.133380                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.937631                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.793830                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.892117                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.906582                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.952869                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.930136                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.428002                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.173773                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.403738                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.016467                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.304211                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.003148                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.056157                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.166258                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.016467                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.304211                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.003148                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.056157                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.166258                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69370.693772                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 43616.276605                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71244.131455                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 78806.188925                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 45019.731748                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   418.989223                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4505.210427                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1569.806994                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1511.709602                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   194.623656                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total   825.112108                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66937.281720                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101594.176707                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 68360.950260                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 69370.693772                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 50569.067128                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 71244.131455                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 100270.947607                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 51912.757302                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 69370.693772                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 50569.067128                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 71244.131455                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 100270.947607                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 51912.757302                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               81151                       # number of writebacks
system.l2c.writebacks::total                    81151                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst            16                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             16                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            16                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        14658                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       273675                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst          623                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data          306                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          289262                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2691                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1055                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3746                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          427                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          465                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          892                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       116250                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         4980                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        121230                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        14658                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       389925                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst          623                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         5286                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           410492                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        14658                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       389925                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst          623                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         5286                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          410492                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    834103687                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data   8585035851                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     37029025                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     20346967                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   9476515530                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     27099154                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     10559051                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     37658205                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      4284925                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4655464                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      8940389                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   6364978414                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    444979380                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   6809957794                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    834103687                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  14950014265                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     37029025                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    465326347                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16286473324                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    834103687                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  14950014265                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     37029025                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    465326347                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16286473324                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1372719000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     16976500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1389695500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2043365000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    571046500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2614411500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3416084000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    588023000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   4004107000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.016466                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.270926                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.003069                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.004673                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.133372                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.937631                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.793830                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.892117                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.906582                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.952869                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.930136                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.428002                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.173773                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.403738                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.016466                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.304211                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.003069                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.056147                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.166251                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.016466                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.304211                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.003069                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.056147                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.166251                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56904.331218                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31369.455928                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59436.637239                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66493.356209                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 32761.010883                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10070.291342                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.579147                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.911105                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10034.953162                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.750538                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.857623                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54752.502486                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89353.289157                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56173.866155                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56904.331218                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38340.743130                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59436.637239                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 88029.955921                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 39675.495074                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56904.331218                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38340.743130                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59436.637239                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 88029.955921                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 39675.495074                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41694                       # number of replacements
system.iocache.tagsinuse                     0.474409                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41710                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1705455708000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       0.474409                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.029651                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.029651                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
system.iocache.overall_misses::total            41726                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21041998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21041998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  10633425431                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10633425431                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  10654467429                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10654467429                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  10654467429                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10654467429                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120931.022989                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120931.022989                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255906.464936                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 255906.464936                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 255343.608997                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 255343.608997                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 255343.608997                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 255343.608997                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        285994                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                27316                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.469835                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          174                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          174                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41726                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41726                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41726                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41726                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11993249                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     11993249                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   8471449424                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   8471449424                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   8483442673                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8483442673                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   8483442673                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8483442673                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68926.718391                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68926.718391                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203875.852522                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 203875.852522                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203313.106289                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 203313.106289                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203313.106289                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 203313.106289                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               12584062                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         10588139                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           341886                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             8301483                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                5323497                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            64.127060                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 804999                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             33376                       # Number of incorrect RAS predictions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     8950032                       # DTB read hits
system.cpu0.dtb.read_misses                     34820                       # DTB read misses
system.cpu0.dtb.read_acv                          539                       # DTB read access violations
system.cpu0.dtb.read_accesses                  674081                       # DTB read accesses
system.cpu0.dtb.write_hits                    5877992                       # DTB write hits
system.cpu0.dtb.write_misses                     8366                       # DTB write misses
system.cpu0.dtb.write_acv                         348                       # DTB write access violations
system.cpu0.dtb.write_accesses                 235610                       # DTB write accesses
system.cpu0.dtb.data_hits                    14828024                       # DTB hits
system.cpu0.dtb.data_misses                     43186                       # DTB misses
system.cpu0.dtb.data_acv                          887                       # DTB access violations
system.cpu0.dtb.data_accesses                  909691                       # DTB accesses
system.cpu0.itb.fetch_hits                    1040487                       # ITB hits
system.cpu0.itb.fetch_misses                    31672                       # ITB misses
system.cpu0.itb.fetch_acv                        1020                       # ITB acv
system.cpu0.itb.fetch_accesses                1072159                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       103751291                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          25592047                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      64430414                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   12584062                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           6128496                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     12114182                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1732019                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles              37108557                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles               31932                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       208707                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       355709                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          408                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  7808396                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               232068                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples          76528583                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.841913                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.179850                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                64414401     84.17%     84.17% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  777905      1.02%     85.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1574114      2.06%     87.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  716339      0.94%     88.18% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2604704      3.40%     91.58% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  529326      0.69%     92.28% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  586322      0.77%     93.04% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  831890      1.09%     94.13% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4493582      5.87%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            76528583                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.121291                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.621008                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                26850978                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             36641611                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 11018000                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               937421                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1080572                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              523116                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                36832                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              63252649                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               110299                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1080572                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                27872767                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               14726920                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      18377517                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 10342666                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              4128139                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              59880890                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 6989                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                638699                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1446922                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands           40104744                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             72926681                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        72541237                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           385444                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             35232895                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 4871841                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1468873                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        214348                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 11259122                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             9368607                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6150188                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1144221                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores          763596                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  53152910                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1825418                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 51980474                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            87912                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        5962808                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      3052808                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1237037                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     76528583                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.679230                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.328773                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           53422858     69.81%     69.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10519380     13.75%     83.55% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            4737419      6.19%     89.74% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            3110993      4.07%     93.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2482363      3.24%     97.05% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1230781      1.61%     98.66% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             656198      0.86%     99.52% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             315996      0.41%     99.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              52595      0.07%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       76528583                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  81649     11.89%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     11.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                319979     46.59%     58.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               285231     41.53%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             3782      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             35814992     68.90%     68.91% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               57898      0.11%     69.02% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     69.02% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              15714      0.03%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.05% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9315059     17.92%     86.97% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5946213     11.44%     98.41% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            824933      1.59%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              51980474                       # Type of FU issued
system.cpu0.iq.rate                          0.501010                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     686859                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.013214                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         180712322                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         60686814                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     50945996                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             551979                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            267326                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       260492                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              52374713                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 288838                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          545458                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1121947                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2762                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        13266                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       454260                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        18544                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       124618                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1080572                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               10513662                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               794213                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           58228726                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           618999                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              9368607                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6150188                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1608738                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                580049                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 5099                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         13266                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        168319                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       356582                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              524901                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             51585627                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9008604                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           394846                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      3250398                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14908735                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 8218209                       # Number of branches executed
system.cpu0.iew.exec_stores                   5900131                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.497205                       # Inst execution rate
system.cpu0.iew.wb_sent                      51301062                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     51206488                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 25493361                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 34352042                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.493550                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.742121                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        6443785                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         588381                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           491234                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     75448011                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.685042                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.601476                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     56013876     74.24%     74.24% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      8117892     10.76%     85.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      4422865      5.86%     90.86% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2392310      3.17%     94.03% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1343441      1.78%     95.81% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       564278      0.75%     96.56% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       477580      0.63%     97.20% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       442296      0.59%     97.78% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1673473      2.22%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     75448011                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            51685042                       # Number of instructions committed
system.cpu0.commit.committedOps              51685042                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      13942588                       # Number of memory references committed
system.cpu0.commit.loads                      8246660                       # Number of loads committed
system.cpu0.commit.membars                     199926                       # Number of memory barriers committed
system.cpu0.commit.branches                   7810095                       # Number of branches committed
system.cpu0.commit.fp_insts                    258326                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 47876421                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              664533                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1673473                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   131700376                       # The number of ROB reads
system.cpu0.rob.rob_writes                  117338865                       # The number of ROB writes
system.cpu0.timesIdled                        1069961                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       27222708                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3689125904                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   48725185                       # Number of Instructions Simulated
system.cpu0.committedOps                     48725185                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             48725185                       # Number of Instructions Simulated
system.cpu0.cpi                              2.129315                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.129315                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.469634                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.469634                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                67898060                       # number of integer regfile reads
system.cpu0.int_regfile_writes               37063784                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   127956                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  129360                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1719000                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                824833                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.icache.replacements                889638                       # number of replacements
system.cpu0.icache.tagsinuse               510.303457                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 6872883                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                890147                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  7.721065                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           20517812000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   510.303457                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.996686                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.996686                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      6872883                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        6872883                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      6872883                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         6872883                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      6872883                       # number of overall hits
system.cpu0.icache.overall_hits::total        6872883                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       935512                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       935512                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       935512                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        935512                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       935512                       # number of overall misses
system.cpu0.icache.overall_misses::total       935512                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13284271991                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  13284271991                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  13284271991                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  13284271991                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  13284271991                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  13284271991                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      7808395                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      7808395                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      7808395                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      7808395                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      7808395                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      7808395                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.119808                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.119808                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.119808                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.119808                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.119808                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.119808                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14200.001701                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14200.001701                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14200.001701                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14200.001701                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14200.001701                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14200.001701                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         5547                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets         2537                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              162                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              3                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    34.240741                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets   845.666667                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        45203                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        45203                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        45203                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        45203                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        45203                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        45203                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       890309                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       890309                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       890309                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       890309                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       890309                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       890309                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10926647992                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  10926647992                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10926647992                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  10926647992                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10926647992                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  10926647992                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.114019                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.114019                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.114019                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.114019                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.114019                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.114019                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12272.871545                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12272.871545                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12272.871545                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12272.871545                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12272.871545                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12272.871545                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1284134                       # number of replacements
system.cpu0.dcache.tagsinuse               505.722211                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                10611019                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1284646                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                  8.259878                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              22124000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   505.722211                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.987739                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.987739                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      6528989                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6528989                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3717707                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3717707                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       164546                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       164546                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       188999                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       188999                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10246696                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        10246696                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10246696                       # number of overall hits
system.cpu0.dcache.overall_hits::total       10246696                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1596925                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1596925                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1771522                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1771522                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20418                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        20418                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2763                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         2763                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3368447                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3368447                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3368447                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3368447                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  34533208000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  34533208000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  68837486976                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  68837486976                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    293802000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    293802000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     20678500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     20678500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 103370694976                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 103370694976                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 103370694976                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 103370694976                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      8125914                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8125914                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5489229                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5489229                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       184964                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       184964                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       191762                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       191762                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     13615143                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     13615143                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     13615143                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     13615143                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.196523                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.196523                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.322727                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.322727                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.110389                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.110389                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.014408                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.014408                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.247404                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.247404                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.247404                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.247404                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21624.815192                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 21624.815192                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38857.822243                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38857.822243                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14389.362327                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14389.362327                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7484.075280                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7484.075280                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30687.938678                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 30687.938678                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30687.938678                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 30687.938678                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      2260715                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets          560                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            49054                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    46.086252                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets           80                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       757117                       # number of writebacks
system.cpu0.dcache.writebacks::total           757117                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       591865                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       591865                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1494302                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1494302                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4660                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4660                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      2086167                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      2086167                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      2086167                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      2086167                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1005060                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      1005060                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       277220                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       277220                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        15758                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        15758                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2763                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         2763                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1282280                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1282280                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1282280                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1282280                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  21590310000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  21590310000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10033221203                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10033221203                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    180646500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    180646500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     15152500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     15152500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  31623531203                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  31623531203                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  31623531203                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  31623531203                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1465155500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1465155500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2167706499                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2167706499                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3632861999                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3632861999                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.123686                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.123686                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.050503                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.050503                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.085195                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.085195                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.014408                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.014408                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.094180                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.094180                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.094180                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.094180                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21481.613038                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21481.613038                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36192.270410                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36192.270410                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11463.796167                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11463.796167                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5484.075280                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5484.075280                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24661.954646                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24661.954646                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24661.954646                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24661.954646                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                2374472                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          1973565                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect            63683                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             1357670                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                 789569                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            58.156179                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 159848                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect              6979                       # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1755569                       # DTB read hits
system.cpu1.dtb.read_misses                      9259                       # DTB read misses
system.cpu1.dtb.read_acv                            6                       # DTB read access violations
system.cpu1.dtb.read_accesses                  277737                       # DTB read accesses
system.cpu1.dtb.write_hits                    1124169                       # DTB write hits
system.cpu1.dtb.write_misses                     1775                       # DTB write misses
system.cpu1.dtb.write_acv                          38                       # DTB write access violations
system.cpu1.dtb.write_accesses                 104346                       # DTB write accesses
system.cpu1.dtb.data_hits                     2879738                       # DTB hits
system.cpu1.dtb.data_misses                     11034                       # DTB misses
system.cpu1.dtb.data_acv                           44                       # DTB access violations
system.cpu1.dtb.data_accesses                  382083                       # DTB accesses
system.cpu1.itb.fetch_hits                     378886                       # ITB hits
system.cpu1.itb.fetch_misses                     5643                       # ITB misses
system.cpu1.itb.fetch_acv                         144                       # ITB acv
system.cpu1.itb.fetch_accesses                 384529                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                        14403389                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles           5507969                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      11118541                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    2374472                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches            949417                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      1985955                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 349018                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles               5777579                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles               25749                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        54503                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        55745                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles            7                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  1323443                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                42238                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples          13629786                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.815753                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.191288                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                11643831     85.43%     85.43% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  125140      0.92%     86.35% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  217081      1.59%     87.94% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  155934      1.14%     89.08% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  266080      1.95%     91.04% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  106134      0.78%     91.82% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  117650      0.86%     92.68% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  192941      1.42%     94.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                  804995      5.91%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            13629786                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.164855                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.771939                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 5440584                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles              6013692                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  1859543                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                99467                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                216499                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved               99353                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                 5852                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              10916304                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                17556                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                216499                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 5632614                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                 346968                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       5076489                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  1765081                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles               592133                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              10097386                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                   38                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 55596                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents               134498                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands            6632848                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups             12019300                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        11877082                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           142218                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps              5717715                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                  915133                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            422143                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         38586                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  1845577                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             1850340                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            1191384                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           164933                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           85198                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                   8855097                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             461396                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                  8635428                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            27588                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        1251794                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined       621930                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        331901                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     13629786                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.633570                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.306468                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0            9807862     71.96%     71.96% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            1774840     13.02%     84.98% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2             743934      5.46%     90.44% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             492954      3.62%     94.06% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             425816      3.12%     97.18% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             193635      1.42%     98.60% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             119802      0.88%     99.48% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7              63937      0.47%     99.95% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8               7006      0.05%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       13629786                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                   2819      1.60%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                 95112     53.88%     55.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                78586     44.52%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             3518      0.04%      0.04% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              5368636     62.17%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               14579      0.17%     62.38% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.38% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd              10813      0.13%     62.50% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.50% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.50% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.50% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1759      0.02%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             1836056     21.26%     83.79% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            1146030     13.27%     97.06% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            254037      2.94%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total               8635428                       # Type of FU issued
system.cpu1.iq.rate                          0.599541                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     176517                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.020441                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          30899211                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         10469267                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses      8392820                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads             205536                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            100351                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses        97198                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses               8701253                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 107174                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           85247                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       244767                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          715                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         1400                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       111607                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads          264                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked         8613                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                216499                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 208020                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                39541                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts            9780313                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           131211                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              1850340                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             1191384                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            418145                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 33976                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 1692                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          1400                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         28557                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect        89287                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              117844                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts              8559872                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              1771461                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts            75556                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       463820                       # number of nop insts executed
system.cpu1.iew.exec_refs                     2903123                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 1270722                       # Number of branches executed
system.cpu1.iew.exec_stores                   1131662                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.594296                       # Inst execution rate
system.cpu1.iew.wb_sent                       8515413                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                      8490018                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  3998147                       # num instructions producing a value
system.cpu1.iew.wb_consumers                  5641896                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.589446                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.708653                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        1285480                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         129495                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           111745                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     13413287                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.628190                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.573982                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     10261662     76.50%     76.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      1478959     11.03%     87.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2       542849      4.05%     91.58% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       333012      2.48%     94.06% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       234215      1.75%     95.81% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        91771      0.68%     96.49% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6        99946      0.75%     97.24% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7        99972      0.75%     97.98% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       270901      2.02%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     13413287                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts             8426096                       # Number of instructions committed
system.cpu1.commit.committedOps               8426096                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       2685350                       # Number of memory references committed
system.cpu1.commit.loads                      1605573                       # Number of loads committed
system.cpu1.commit.membars                      41432                       # Number of memory barriers committed
system.cpu1.commit.branches                   1197085                       # Number of branches committed
system.cpu1.commit.fp_insts                     95994                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                  7795496                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              132738                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events               270901                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                    22771832                       # The number of ROB reads
system.cpu1.rob.rob_writes                   19637981                       # The number of ROB writes
system.cpu1.timesIdled                         118769                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                         773603                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3777797828                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                    8011939                       # Number of Instructions Simulated
system.cpu1.committedOps                      8011939                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total              8011939                       # Number of Instructions Simulated
system.cpu1.cpi                              1.797741                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.797741                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.556254                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.556254                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                11010177                       # number of integer regfile reads
system.cpu1.int_regfile_writes                6039470                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    53089                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   52904                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 494875                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                202385                       # number of misc regfile writes
system.cpu1.icache.replacements                202443                       # number of replacements
system.cpu1.icache.tagsinuse               470.727745                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 1113774                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                202955                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                  5.487788                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1886714019000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   470.727745                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.919390                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.919390                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      1113774                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        1113774                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      1113774                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         1113774                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      1113774                       # number of overall hits
system.cpu1.icache.overall_hits::total        1113774                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       209669                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       209669                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       209669                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        209669                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       209669                       # number of overall misses
system.cpu1.icache.overall_misses::total       209669                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   2812457500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   2812457500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   2812457500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   2812457500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   2812457500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   2812457500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      1323443                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      1323443                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      1323443                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      1323443                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      1323443                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      1323443                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.158427                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.158427                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.158427                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.158427                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.158427                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.158427                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13413.797462                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13413.797462                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13413.797462                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13413.797462                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13413.797462                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13413.797462                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs           72                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                9                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs            8                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         6654                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total         6654                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst         6654                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total         6654                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst         6654                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total         6654                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       203015                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       203015                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       203015                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       203015                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       203015                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       203015                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   2347033500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   2347033500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   2347033500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   2347033500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   2347033500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   2347033500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.153399                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.153399                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.153399                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.153399                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.153399                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.153399                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11560.887127                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11560.887127                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11560.887127                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11560.887127                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11560.887127                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11560.887127                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                 95898                       # number of replacements
system.cpu1.dcache.tagsinuse               491.044785                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 2359205                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                 96213                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 24.520647                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           39003208000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   491.044785                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.959072                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.959072                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      1444297                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1444297                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data       860369                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        860369                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        29709                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        29709                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        28445                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        28445                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      2304666                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         2304666                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      2304666                       # number of overall hits
system.cpu1.dcache.overall_hits::total        2304666                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       191100                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       191100                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       182257                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       182257                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         4958                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         4958                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data         3002                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         3002                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       373357                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        373357                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       373357                       # number of overall misses
system.cpu1.dcache.overall_misses::total       373357                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2726429000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2726429000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   5605304282                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   5605304282                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     50865000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     50865000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     22043000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     22043000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   8331733282                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   8331733282                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   8331733282                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   8331733282                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      1635397                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      1635397                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      1042626                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1042626                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        34667                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        34667                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        31447                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        31447                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      2678023                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      2678023                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      2678023                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      2678023                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.116852                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.116852                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.174806                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.174806                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.143018                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.143018                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.095462                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.095462                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.139415                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.139415                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.139415                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.139415                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14267.027734                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14267.027734                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30754.946488                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 30754.946488                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10259.177088                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10259.177088                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7342.771486                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7342.771486                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22315.728062                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 22315.728062                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22315.728062                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 22315.728062                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs       178298                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3033                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    58.786020                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks        62482                       # number of writebacks
system.cpu1.dcache.writebacks::total            62482                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       119560                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       119560                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       148811                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       148811                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          417                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total          417                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       268371                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       268371                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       268371                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       268371                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        71540                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total        71540                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        33446                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        33446                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4541                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4541                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         3000                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total         3000                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       104986                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       104986                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       104986                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       104986                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    843257000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total    843257000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    841845993                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total    841845993                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     36401500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     36401500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     16047000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     16047000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         2000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         2000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   1685102993                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   1685102993                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   1685102993                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   1685102993                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18098500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18098500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    603885500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    603885500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    621984000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    621984000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.043745                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.043745                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032079                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.032079                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.130989                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.130989                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.095399                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.095399                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.039203                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.039203                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.039203                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.039203                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11787.209952                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11787.209952                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25170.304162                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25170.304162                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8016.185862                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8016.185862                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data         5349                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total         5349                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16050.740032                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16050.740032                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16050.740032                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16050.740032                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6633                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    185817                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   65566     40.59%     40.59% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.08%     40.67% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1923      1.19%     41.86% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    201      0.12%     41.99% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  93709     58.01%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              161530                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    64589     49.22%     49.22% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.10%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1923      1.47%     50.78% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     201      0.15%     50.94% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   64388     49.06%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               131232                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1860847795500     98.12%     98.12% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               64543000      0.00%     98.13% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              567978500      0.03%     98.16% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30               98193500      0.01%     98.16% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            34862560000      1.84%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1896441070500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.985099                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.687106                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.812431                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.42%      3.42% # number of syscalls executed
system.cpu0.kern.syscall::3                        20      8.55%     11.97% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.71%     13.68% # number of syscalls executed
system.cpu0.kern.syscall::6                        33     14.10%     27.78% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.43%     28.21% # number of syscalls executed
system.cpu0.kern.syscall::17                       10      4.27%     32.48% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.27%     36.75% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.56%     39.32% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.43%     39.74% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.28%     41.03% # number of syscalls executed
system.cpu0.kern.syscall::33                        8      3.42%     44.44% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.85%     45.30% # number of syscalls executed
system.cpu0.kern.syscall::45                       39     16.67%     61.97% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.28%     63.25% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.27%     67.52% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.27%     71.79% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.43%     72.22% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.56%     74.79% # number of syscalls executed
system.cpu0.kern.syscall::71                       27     11.54%     86.32% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.28%     87.61% # number of syscalls executed
system.cpu0.kern.syscall::74                        7      2.99%     90.60% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.43%     91.03% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.28%     92.31% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      3.85%     96.15% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.85%     97.01% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.85%     97.86% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.43%     98.29% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.85%     99.15% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.85%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   234                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  284      0.17%      0.17% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.17% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.17% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.17% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3552      2.08%      2.25% # number of callpals executed
system.cpu0.kern.callpal::tbi                      51      0.03%      2.28% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.29% # number of callpals executed
system.cpu0.kern.callpal::swpipl               154681     90.79%     93.08% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6653      3.90%     96.98% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.98% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     4      0.00%     96.98% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.01%     96.99% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.99% # number of callpals executed
system.cpu0.kern.callpal::rti                    4593      2.70%     99.69% # number of callpals executed
system.cpu0.kern.callpal::callsys                 394      0.23%     99.92% # number of callpals executed
system.cpu0.kern.callpal::imb                     139      0.08%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                170374                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             7193                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1370                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1369                      
system.cpu0.kern.mode_good::user                 1370                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.190324                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.319865                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1894375479500     99.89%     99.89% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          2065583000      0.11%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3553                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2383                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     53842                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   16791     36.23%     36.23% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1921      4.14%     40.37% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    284      0.61%     40.99% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  27352     59.01%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               46348                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    16391     47.23%     47.23% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1921      5.54%     52.77% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     284      0.82%     53.59% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   16107     46.41%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                34703                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1871184919000     98.69%     98.69% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              531151500      0.03%     98.71% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              127549500      0.01%     98.72% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            24258165000      1.28%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1896101785000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.976178                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.588878                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.748749                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        10     10.87%     10.87% # number of syscalls executed
system.cpu1.kern.syscall::6                         9      9.78%     20.65% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      1.09%     21.74% # number of syscalls executed
system.cpu1.kern.syscall::17                        5      5.43%     27.17% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      3.26%     30.43% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      3.26%     33.70% # number of syscalls executed
system.cpu1.kern.syscall::33                        3      3.26%     36.96% # number of syscalls executed
system.cpu1.kern.syscall::45                       15     16.30%     53.26% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      3.26%     56.52% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      1.09%     57.61% # number of syscalls executed
system.cpu1.kern.syscall::71                       27     29.35%     86.96% # number of syscalls executed
system.cpu1.kern.syscall::74                        9      9.78%     96.74% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      3.26%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                    92                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  201      0.42%      0.42% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.43% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.43% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 1067      2.24%      2.67% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.01%      2.67% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      2.69% # number of callpals executed
system.cpu1.kern.callpal::swpipl                41171     86.33%     89.01% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2098      4.40%     93.41% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.41% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     3      0.01%     93.42% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     93.43% # number of callpals executed
system.cpu1.kern.callpal::rti                    2971      6.23%     99.66% # number of callpals executed
system.cpu1.kern.callpal::callsys                 121      0.25%     99.91% # number of callpals executed
system.cpu1.kern.callpal::imb                      42      0.09%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 47692                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             1242                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                368                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2406                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                576                      
system.cpu1.kern.mode_good::user                  368                      
system.cpu1.kern.mode_good::idle                  208                      
system.cpu1.kern.mode_switch_good::kernel     0.463768                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.086451                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.286853                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        4070064000      0.21%      0.21% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           689483000      0.04%      0.25% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1891020032000     99.75%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    1068                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------