path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.905240                       # Number of seconds simulated
sim_ticks                                1905239522500                       # Number of ticks simulated
final_tick                               1905239522500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 125426                       # Simulator instruction rate (inst/s)
host_op_rate                                   125426                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4213194084                       # Simulator tick rate (ticks/s)
host_mem_usage                                 351852                       # Number of bytes of host memory used
host_seconds                                   452.21                       # Real time elapsed on the host
sim_insts                                    56718526                       # Number of instructions simulated
sim_ops                                      56718526                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst           764480                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24384256                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2649344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           214080                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           925440                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28937600                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       764480                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       214080                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          978560                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7885248                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7885248                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             11945                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            381004                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41396                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              3345                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             14460                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                452150                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          123207                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               123207                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              401251                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12798525                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1390557                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              112364                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              485734                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15188432                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         401251                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         112364                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             513615                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4138717                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4138717                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4138717                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             401251                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12798525                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1390557                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             112364                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             485734                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19327149                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        452150                       # Number of read requests accepted
system.physmem.writeReqs                       123207                       # Number of write requests accepted
system.physmem.readBursts                      452150                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     123207                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 28929984                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7616                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7883136                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  28937600                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7885248                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      119                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           5017                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               28700                       # Per bank write bursts
system.physmem.perBankRdBursts::1               28863                       # Per bank write bursts
system.physmem.perBankRdBursts::2               29008                       # Per bank write bursts
system.physmem.perBankRdBursts::3               28541                       # Per bank write bursts
system.physmem.perBankRdBursts::4               28135                       # Per bank write bursts
system.physmem.perBankRdBursts::5               28059                       # Per bank write bursts
system.physmem.perBankRdBursts::6               27918                       # Per bank write bursts
system.physmem.perBankRdBursts::7               27861                       # Per bank write bursts
system.physmem.perBankRdBursts::8               27885                       # Per bank write bursts
system.physmem.perBankRdBursts::9               28003                       # Per bank write bursts
system.physmem.perBankRdBursts::10              27955                       # Per bank write bursts
system.physmem.perBankRdBursts::11              28030                       # Per bank write bursts
system.physmem.perBankRdBursts::12              28165                       # Per bank write bursts
system.physmem.perBankRdBursts::13              28514                       # Per bank write bursts
system.physmem.perBankRdBursts::14              28239                       # Per bank write bursts
system.physmem.perBankRdBursts::15              28155                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8383                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8222                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8291                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7900                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7506                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7518                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7426                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7231                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7193                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7295                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7315                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7381                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7680                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8142                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8013                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7678                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
system.physmem.totGap                    1905235063000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  452150                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 123207                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    319865                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     54341                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     31702                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9495                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      1181                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      4300                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      3776                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      3798                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3977                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2606                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     2173                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2035                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1927                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1842                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1542                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1515                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     1493                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                     1512                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                     1685                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                     1253                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      778                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      807                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                      994                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     2374                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3618                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4468                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5021                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5917                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5811                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5880                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6693                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6628                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6580                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6554                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     3796                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     2487                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1653                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1093                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1060                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     1234                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1357                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1523                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1618                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1796                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1807                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1882                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1750                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1868                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     1849                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1781                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1824                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                     1698                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                     1470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                     1247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      893                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      633                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      442                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      275                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       24                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        51367                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      630.908404                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     404.510586                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     424.248985                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127           9707     18.90%     18.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         6974     13.58%     32.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         3124      6.08%     38.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1892      3.68%     42.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1518      2.96%     45.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          943      1.84%     47.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          823      1.60%     48.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          886      1.72%     50.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        25500     49.64%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          51367                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7232                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        62.502074                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2469.163441                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           7229     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7232                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7232                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.031803                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.787924                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        3.763450                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               6148     85.01%     85.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 35      0.48%     85.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                 69      0.95%     86.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                422      5.84%     92.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                144      1.99%     94.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 50      0.69%     94.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 33      0.46%     95.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 29      0.40%     95.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 50      0.69%     96.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 33      0.46%     96.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                 22      0.30%     97.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                 30      0.41%     97.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                 23      0.32%     98.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                 33      0.46%     98.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  3      0.04%     98.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                 10      0.14%     98.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                  7      0.10%     98.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33                  5      0.07%     98.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34                  2      0.03%     98.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35                  3      0.04%     98.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36                  4      0.06%     98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37                  3      0.04%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38                  4      0.06%     99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39                  6      0.08%     99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40                  7      0.10%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::41                  2      0.03%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42                  5      0.07%     99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43                  4      0.06%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44                  2      0.03%     99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::45                  2      0.03%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46                  2      0.03%     99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::47                  9      0.12%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48                  8      0.11%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::49                  6      0.08%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50                  1      0.01%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::51                  4      0.06%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52                  3      0.04%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::53                  2      0.03%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::54                  1      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::55                  4      0.06%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56                  2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7232                       # Writes before turning the bus around for reads
system.physmem.totQLat                    10473139750                       # Total ticks spent queuing
system.physmem.totMemAccLat               18209837250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2260155000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  5476542500                       # Total ticks spent accessing banks
system.physmem.avgQLat                       23169.07                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    12115.41                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  40284.49                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          15.18                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           4.14                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       15.19                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        4.14                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.83                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.68                       # Average write queue length when enqueuing
system.physmem.readRowHits                     407908                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     99848                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.24                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  81.04                       # Row buffer hit rate for writes
system.physmem.avgGap                      3311396.34                       # Average gap between requests
system.physmem.pageHitRate                      88.27                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               0.40                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                     19386335                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              296672                       # Transaction distribution
system.membus.trans_dist::ReadResp             296448                       # Transaction distribution
system.membus.trans_dist::WriteReq              13044                       # Transaction distribution
system.membus.trans_dist::WriteResp             13044                       # Transaction distribution
system.membus.trans_dist::Writeback            123207                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             9628                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq           5545                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            5017                       # Transaction distribution
system.membus.trans_dist::ReadExReq            163957                       # Transaction distribution
system.membus.trans_dist::ReadExResp           163513                       # Transaction distribution
system.membus.trans_dist::BadAddressError          224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40492                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       924104                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          448                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       965044                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124646                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       124646                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1089690                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        73787                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31516032                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     31589819                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5306816                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5306816                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            36896635                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               36896635                       # Total data (bytes)
system.membus.snoop_data_through_bus            38976                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            37949499                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1621348498                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer2.occupancy              283500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3837196476                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy          376708248                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                   345233                       # number of replacements
system.l2c.tags.tagsinuse                65245.285653                       # Cycle average of tags in use
system.l2c.tags.total_refs                    2551644                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   410415                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     6.217229                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               7106352750                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   53519.548176                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4149.494238                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     5612.081999                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1358.843164                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      605.318076                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.816643                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.063316                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.085634                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.020734                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.009236                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.995564                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        65182                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1         2472                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         5440                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5794                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        51245                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.994598                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 26808140                       # Number of tag accesses
system.l2c.tags.data_accesses                26808140                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst             890534                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             623023                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             181208                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             171976                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1866741                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          807199                       # number of Writeback hits
system.l2c.Writeback_hits::total               807199                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             179                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             196                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 375                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            42                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            30                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                72                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           156975                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            15152                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               172127                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              890534                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              779998                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              181208                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              187128                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2038868                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             890534                       # number of overall hits
system.l2c.overall_hits::cpu0.data             779998                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             181208                       # number of overall hits
system.l2c.overall_hits::cpu1.data             187128                       # number of overall hits
system.l2c.overall_hits::total                2038868                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            11953                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           272223                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             3356                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1782                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               289314                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          3186                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           726                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3912                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          379                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          428                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             807                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         109189                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          13070                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             122259                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             11953                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            381412                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              3356                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             14852                       # number of demand (read+write) misses
system.l2c.demand_misses::total                411573                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            11953                       # number of overall misses
system.l2c.overall_misses::cpu0.data           381412                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             3356                       # number of overall misses
system.l2c.overall_misses::cpu1.data            14852                       # number of overall misses
system.l2c.overall_misses::total               411573                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst    917004250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  17843471250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    269423486                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    137552496                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    19167451482                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      1326945                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       933461                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      2260406                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       265489                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2039412                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      2304901                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   9056624622                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1307071580                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  10363696202                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst    917004250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  26900095872                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    269423486                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1444624076                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     29531147684                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst    917004250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  26900095872                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    269423486                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1444624076                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    29531147684                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         902487                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         895246                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         184564                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         173758                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2156055                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       807199                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           807199                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         3365                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          922                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            4287                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          421                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          458                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           879                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       266164                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        28222                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           294386                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          902487                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1161410                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          184564                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          201980                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2450441                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         902487                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1161410                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         184564                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         201980                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2450441                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.013245                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.304076                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.018183                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.010256                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.134187                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.946805                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.787419                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.912526                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.900238                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.934498                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.918089                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.410232                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.463114                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.415302                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.013245                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.328404                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.018183                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.073532                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.167959                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.013245                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.328404                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.018183                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.073532                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.167959                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76717.497699                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 65547.258130                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80281.134088                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 77189.952862                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 66251.379062                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   416.492467                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1285.758953                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   577.813395                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   700.498681                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  4764.981308                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  2856.135068                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82944.478125                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 100005.476664                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 84768.370443                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 76717.497699                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 70527.660042                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 80281.134088                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 97267.982494                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 71751.907156                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 76717.497699                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 70527.660042                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 80281.134088                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 97267.982494                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 71751.907156                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               81684                       # number of writebacks
system.l2c.writebacks::total                    81684                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst            11                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                19                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 19                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                19                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        11946                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       272222                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         3345                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1782                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          289295                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         3186                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          726                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3912                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          379                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          428                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          807                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       109189                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        13070                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        122259                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        11946                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       381411                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         3345                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        14852                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           411554                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        11946                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       381411                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         3345                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        14852                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          411554                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    765862000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  14447057750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    226574764                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    136795504                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  15576290018                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     31921141                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      7272722                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     39193863                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      3803378                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4284427                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      8087805                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7721269876                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1146179920                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   8867449796                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    765862000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  22168327626                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    226574764                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1282975424                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  24443739814                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    765862000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  22168327626                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    226574764                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1282975424                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  24443739814                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    936599500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    454544000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1391143500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1663713500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    943761500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2607475000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2600313000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1398305500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   3998618500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.013237                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.304075                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.018124                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.010256                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.134178                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.946805                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.787419                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.912526                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.900238                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.934498                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.918089                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.410232                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.463114                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.415302                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013237                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.328403                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.018124                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.073532                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.167951                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013237                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.328403                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.018124                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.073532                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.167951                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64110.329818                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53070.867711                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67735.355456                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76765.153760                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 53842.237225                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10019.190521                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.523416                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10018.881135                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.298153                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10010.343458                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.063197                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70714.722875                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 87695.479725                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 72530.037020                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64110.329818                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58121.888530                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67735.355456                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86384.017237                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 59393.760756                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64110.329818                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58121.888530                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67735.355456                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86384.017237                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 59393.760756                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                41698                       # number of replacements
system.iocache.tags.tagsinuse                0.475429                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41714                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1712299730000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     0.475429                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.029714                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.029714                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375543                       # Number of tag accesses
system.iocache.tags.data_accesses              375543                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          175                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41727                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41727                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41727                       # number of overall misses
system.iocache.overall_misses::total            41727                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21363133                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21363133                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  13166015946                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  13166015946                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  13187379079                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  13187379079                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  13187379079                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  13187379079                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          175                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41727                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41727                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41727                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41727                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122075.045714                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122075.045714                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 316856.371438                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 316856.371438                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 316039.472739                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 316039.472739                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 316039.472739                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 316039.472739                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        391077                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                28468                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    13.737424                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41523                       # number of writebacks
system.iocache.writebacks::total                41523                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          175                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          175                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41727                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41727                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41727                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41727                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12262133                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12262133                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  11002982450                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total  11002982450                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide  11015244583                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total  11015244583                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide  11015244583                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total  11015244583                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70069.331429                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70069.331429                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264800.309251                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 264800.309251                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263983.621708                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 263983.621708                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263983.621708                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 263983.621708                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               12197818                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         10301308                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           323625                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             8091894                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                5160475                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            63.773389                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 773216                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             29770                       # Number of incorrect RAS predictions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     8724392                       # DTB read hits
system.cpu0.dtb.read_misses                     30821                       # DTB read misses
system.cpu0.dtb.read_acv                          561                       # DTB read access violations
system.cpu0.dtb.read_accesses                  667825                       # DTB read accesses
system.cpu0.dtb.write_hits                    5867379                       # DTB write hits
system.cpu0.dtb.write_misses                     8333                       # DTB write misses
system.cpu0.dtb.write_acv                         362                       # DTB write access violations
system.cpu0.dtb.write_accesses                 233878                       # DTB write accesses
system.cpu0.dtb.data_hits                    14591771                       # DTB hits
system.cpu0.dtb.data_misses                     39154                       # DTB misses
system.cpu0.dtb.data_acv                          923                       # DTB access violations
system.cpu0.dtb.data_accesses                  901703                       # DTB accesses
system.cpu0.itb.fetch_hits                    1047253                       # ITB hits
system.cpu0.itb.fetch_misses                    31067                       # ITB misses
system.cpu0.itb.fetch_acv                         998                       # ITB acv
system.cpu0.itb.fetch_accesses                1078320                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       112262549                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          25337690                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      62232975                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   12197818                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           5933691                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     11660813                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1669062                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles              34963299                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles               31852                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       204835                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       245581                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          284                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  7519019                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               220862                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples          73507816                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.846617                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.186991                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                61847003     84.14%     84.14% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  769960      1.05%     85.18% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1463561      1.99%     87.18% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  676221      0.92%     88.10% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2490968      3.39%     91.48% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  505392      0.69%     92.17% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  543861      0.74%     92.91% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  933568      1.27%     94.18% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4277282      5.82%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            73507816                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.108654                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.554352                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                26369028                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             34601594                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 10599753                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               908827                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1028613                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              489342                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                35202                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              61098455                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               108348                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1028613                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                27370799                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               12650473                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      18559497                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  9975684                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              3922748                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              57686354                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 6807                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                465136                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1446625                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands           38461887                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             70023385                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        69867874                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           145011                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             33864047                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 4597832                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1504040                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        221397                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 10820518                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             9135753                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6149920                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1079808                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores          706714                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  51077926                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1853906                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 49994907                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           110749                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        5661802                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      2962344                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1252355                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     73507816                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.680130                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.328001                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           51188064     69.64%     69.64% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10233888     13.92%     83.56% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            4604901      6.26%     89.82% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2962380      4.03%     93.85% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2331848      3.17%     97.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1189595      1.62%     98.64% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             642601      0.87%     99.52% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             303208      0.41%     99.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              51331      0.07%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       73507816                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  67972     10.01%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                320913     47.27%     57.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               290070     42.72%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             3770      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             34052559     68.11%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               53588      0.11%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              16727      0.03%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.26% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9088781     18.18%     86.44% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5934753     11.87%     98.31% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            842846      1.69%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              49994907                       # Type of FU issued
system.cpu0.iq.rate                          0.445339                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     678955                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.013580                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         173664474                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         58303886                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     48932524                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             622859                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            301167                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       293964                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              50344041                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 326051                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          531595                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1104780                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2697                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        11676                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       443054                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        13921                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       147330                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1028613                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                8821962                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               743484                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           56052726                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           628552                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              9135753                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6149920                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1633160                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                601804                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 5465                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         11676                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        157790                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       354691                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              512481                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             49615767                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              8780349                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           379139                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      3120894                       # number of nop insts executed
system.cpu0.iew.exec_refs                    14670742                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 7826693                       # Number of branches executed
system.cpu0.iew.exec_stores                   5890393                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.441962                       # Inst execution rate
system.cpu0.iew.wb_sent                      49317778                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     49226488                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 24274382                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 32670143                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.438494                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.743014                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        6126865                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         601551                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           478401                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     72479203                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.687487                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.606917                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     53761554     74.18%     74.18% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      7891628     10.89%     85.06% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      4152119      5.73%     90.79% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2321486      3.20%     93.99% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1304265      1.80%     95.79% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       530677      0.73%     96.53% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       447192      0.62%     97.14% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       447640      0.62%     97.76% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1622642      2.24%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     72479203                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            49828537                       # Number of instructions committed
system.cpu0.commit.committedOps              49828537                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      13737839                       # Number of memory references committed
system.cpu0.commit.loads                      8030973                       # Number of loads committed
system.cpu0.commit.membars                     204358                       # Number of memory barriers committed
system.cpu0.commit.branches                   7461649                       # Number of branches committed
system.cpu0.commit.fp_insts                    291974                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 46136165                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              636945                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1622642                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   126610557                       # The number of ROB reads
system.cpu0.rob.rob_writes                  112939421                       # The number of ROB writes
system.cpu0.timesIdled                        1039659                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       38754733                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3698211471                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   46979170                       # Number of Instructions Simulated
system.cpu0.committedOps                     46979170                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             46979170                       # Number of Instructions Simulated
system.cpu0.cpi                              2.389624                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.389624                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.418476                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.418476                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                65113755                       # number of integer regfile reads
system.cpu0.int_regfile_writes               35503571                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   144629                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  146446                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1885764                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                851290                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.toL2Bus.throughput                   110236199                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2184890                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2184651                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             13044                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            13044                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           807199                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            9705                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq          5617                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          15322                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           337408                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          295861                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError          224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1805066                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3017885                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       369158                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       600045                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               5792154                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     57759168                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    115626954                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     11812096                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     23360753                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          208558971                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             208548411                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus         1477952                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4893610631                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.3                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           742500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4065813860                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        5358512161                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         831641640                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         971081953                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.1                       # Layer utilization (%)
system.iobus.throughput                       1435731                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq                 7377                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7377                       # Transaction distribution
system.iobus.trans_dist::WriteReq               54596                       # Transaction distribution
system.iobus.trans_dist::WriteResp              54596                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11886                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6674                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        40492                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83454                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83454                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  123946                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        47544                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4194                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total        73787                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661624                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661624                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              2735411                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 2735411                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             11236000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               359000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13505000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             2450000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5167000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           379995831                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            27448000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            43184752                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.cpu0.icache.tags.replacements           901902                       # number of replacements
system.cpu0.icache.tags.tagsinuse          509.676111                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs            6573395                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           902414                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs             7.284234                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      26905725250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.676111                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995461                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.995461                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          428                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses          8421597                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses         8421597                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst      6573395                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        6573395                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      6573395                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         6573395                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      6573395                       # number of overall hits
system.cpu0.icache.overall_hits::total        6573395                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       945623                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       945623                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       945623                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        945623                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       945623                       # number of overall misses
system.cpu0.icache.overall_misses::total       945623                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13224491137                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  13224491137                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  13224491137                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  13224491137                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  13224491137                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  13224491137                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      7519018                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      7519018                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      7519018                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      7519018                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      7519018                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      7519018                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.125764                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.125764                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.125764                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.125764                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.125764                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.125764                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13984.950807                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13984.950807                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13984.950807                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13984.950807                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13984.950807                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13984.950807                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         3461                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets          139                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              144                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    24.034722                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          139                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        43044                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        43044                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        43044                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        43044                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        43044                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        43044                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       902579                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       902579                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       902579                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       902579                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       902579                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       902579                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10909532635                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  10909532635                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10909532635                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  10909532635                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10909532635                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  10909532635                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.120039                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.120039                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.120039                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.120039                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.120039                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.120039                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12087.066766                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12087.066766                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12087.066766                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12087.066766                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12087.066766                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12087.066766                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements          1164537                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          498.695388                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           10555909                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1165049                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs             9.060485                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         26173000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   498.695388                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.974014                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.974014                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          238                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          222                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           52                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         56283368                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        56283368                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      6422745                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6422745                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3752316                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3752316                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       172180                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       172180                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       196241                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       196241                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10175061                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        10175061                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10175061                       # number of overall hits
system.cpu0.dcache.overall_hits::total       10175061                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1468970                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1468970                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1742020                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1742020                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20433                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        20433                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2875                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         2875                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3210990                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3210990                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3210990                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3210990                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  38326965830                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  38326965830                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  76755016444                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  76755016444                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    286872989                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    286872989                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     20380878                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     20380878                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 115081982274                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 115081982274                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 115081982274                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 115081982274                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7891715                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      7891715                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5494336                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5494336                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       192613                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       192613                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       199116                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       199116                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     13386051                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     13386051                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     13386051                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     13386051                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.186141                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.186141                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.317057                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.317057                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.106083                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.106083                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.014439                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.014439                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.239876                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.239876                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.239876                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.239876                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26091.047353                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 26091.047353                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44060.927225                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 44060.927225                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14039.690158                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14039.690158                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7089.001043                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7089.001043                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35840.031353                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 35840.031353                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35840.031353                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 35840.031353                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      2903843                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets          789                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            48428                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    59.962067                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   112.714286                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       644423                       # number of writebacks
system.cpu0.dcache.writebacks::total           644423                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       578811                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       578811                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1469624                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1469624                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4269                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4269                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      2048435                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      2048435                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      2048435                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      2048435                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       890159                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       890159                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       272396                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       272396                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        16164                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        16164                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2875                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         2875                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1162555                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1162555                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1162555                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1162555                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25660783347                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25660783347                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11256320137                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11256320137                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    175450760                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    175450760                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     14630122                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     14630122                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  36917103484                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  36917103484                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  36917103484                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  36917103484                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    999097000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    999097000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1765340999                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1765340999                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2764437999                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2764437999                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.112797                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.112797                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.049578                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.049578                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.083920                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.083920                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.014439                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.014439                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.086848                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.086848                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.086848                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.086848                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28827.190813                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28827.190813                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41323.367953                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41323.367953                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10854.414749                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10854.414749                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5088.738087                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5088.738087                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31755.145764                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31755.145764                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31755.145764                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31755.145764                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                2770041                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          2267711                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect            80921                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             1482926                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                 969002                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            65.343921                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 198874                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect              6522                       # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     2016743                       # DTB read hits
system.cpu1.dtb.read_misses                      9789                       # DTB read misses
system.cpu1.dtb.read_acv                            6                       # DTB read access violations
system.cpu1.dtb.read_accesses                  278621                       # DTB read accesses
system.cpu1.dtb.write_hits                    1132288                       # DTB write hits
system.cpu1.dtb.write_misses                     1938                       # DTB write misses
system.cpu1.dtb.write_acv                          37                       # DTB write access violations
system.cpu1.dtb.write_accesses                 105909                       # DTB write accesses
system.cpu1.dtb.data_hits                     3149031                       # DTB hits
system.cpu1.dtb.data_misses                     11727                       # DTB misses
system.cpu1.dtb.data_acv                           43                       # DTB access violations
system.cpu1.dtb.data_accesses                  384530                       # DTB accesses
system.cpu1.itb.fetch_hits                     369710                       # ITB hits
system.cpu1.itb.fetch_misses                     5636                       # ITB misses
system.cpu1.itb.fetch_acv                         119                       # ITB acv
system.cpu1.itb.fetch_accesses                 375346                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                        18798992                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles           5357256                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      13511342                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    2770041                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           1167876                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      2476292                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 427198                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles               8263333                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles               26082                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        54640                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       162618                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles           35                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  1630522                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                50477                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples          16624070                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.812758                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.170685                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                14147778     85.10%     85.10% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  131100      0.79%     85.89% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  332329      2.00%     87.89% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  198517      1.19%     89.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  395957      2.38%     91.47% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  132924      0.80%     92.27% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  159356      0.96%     93.23% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                   93423      0.56%     93.79% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 1032686      6.21%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            16624070                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.147351                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.718727                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 5556172                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles              8353280                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  2307081                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               131115                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                276421                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              130911                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                 7501                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              13245951                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                18855                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                276421                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 5775463                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                2664230                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       4961239                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  2147700                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles               799015                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              12421307                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                  241                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                220838                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents               145988                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands            8355946                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups             15113763                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        15073339                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            35607                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps              7070748                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 1285198                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            385003                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         30758                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  2314294                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             2123178                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            1208247                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           244787                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          150121                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  10996175                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             428151                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 10636944                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            28046                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        1617836                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined       831016                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        312637                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     16624070                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.639852                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.326685                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           12087523     72.71%     72.71% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            1967089     11.83%     84.54% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2             877391      5.28%     89.82% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             655455      3.94%     93.76% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             567827      3.42%     97.18% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             232884      1.40%     98.58% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             149324      0.90%     99.48% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7              75580      0.45%     99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              10997      0.07%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       16624070                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  16676      8.84%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                 99378     52.65%     61.49% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                72683     38.51%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             3518      0.03%      0.03% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              7118581     66.92%     66.96% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               18880      0.18%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd               9739      0.09%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1759      0.02%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.24% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             2093745     19.68%     86.93% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            1155572     10.86%     97.79% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            235150      2.21%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              10636944                       # Type of FU issued
system.cpu1.iq.rate                          0.565825                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     188737                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.017744                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          37986289                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         12982235                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     10383881                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads             128452                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes             62754                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses        61527                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              10755461                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                  66702                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          101929                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       306426                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          815                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         2923                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       138344                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads         4845                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        18286                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                276421                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                2089253                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                85247                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           12015910                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           137996                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              2123178                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             1208247                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            388932                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 10076                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 1666                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          2923                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         39900                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect        91880                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              131780                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             10541126                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              2031671                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts            95818                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       591584                       # number of nop insts executed
system.cpu1.iew.exec_refs                     3170643                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 1658996                       # Number of branches executed
system.cpu1.iew.exec_stores                   1138972                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.560728                       # Inst execution rate
system.cpu1.iew.wb_sent                      10475567                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     10445408                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  5214693                       # num instructions producing a value
system.cpu1.iew.wb_consumers                  7314185                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.555637                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.712956                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        1685534                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         115514                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           123376                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     16347649                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.627728                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.542862                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     12457643     76.20%     76.20% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      1697144     10.38%     86.59% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2       844179      5.16%     91.75% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       419187      2.56%     94.31% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       268727      1.64%     95.96% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       133453      0.82%     96.77% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       126834      0.78%     97.55% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7        88227      0.54%     98.09% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       312255      1.91%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     16347649                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            10261869                       # Number of instructions committed
system.cpu1.commit.committedOps              10261869                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       2886655                       # Number of memory references committed
system.cpu1.commit.loads                      1816752                       # Number of loads committed
system.cpu1.commit.membars                      36648                       # Number of memory barriers committed
system.cpu1.commit.branches                   1542101                       # Number of branches committed
system.cpu1.commit.fp_insts                     60269                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                  9518406                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              159983                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events               312255                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                    27899142                       # The number of ROB reads
system.cpu1.rob.rob_writes                   24169847                       # The number of ROB writes
system.cpu1.timesIdled                         181051                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        2174922                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3790987217                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                    9739356                       # Number of Instructions Simulated
system.cpu1.committedOps                      9739356                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total              9739356                       # Number of Instructions Simulated
system.cpu1.cpi                              1.930209                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.930209                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.518079                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.518079                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                13792462                       # number of integer regfile reads
system.cpu1.int_regfile_writes                7586165                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    35303                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   34737                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 829246                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                174995                       # number of misc regfile writes
system.cpu1.icache.tags.replacements           184023                       # number of replacements
system.cpu1.icache.tags.tagsinuse          502.144736                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            1436916                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           184535                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs             7.786685                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     1712232500000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   502.144736                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980751                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.980751                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          511                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses          1815116                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses         1815116                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      1436916                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        1436916                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      1436916                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         1436916                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      1436916                       # number of overall hits
system.cpu1.icache.overall_hits::total        1436916                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       193606                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       193606                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       193606                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        193606                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       193606                       # number of overall misses
system.cpu1.icache.overall_misses::total       193606                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   2794361223                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   2794361223                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   2794361223                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   2794361223                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   2794361223                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   2794361223                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      1630522                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      1630522                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      1630522                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      1630522                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      1630522                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      1630522                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.118739                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.118739                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.118739                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.118739                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.118739                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.118739                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14433.236692                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14433.236692                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14433.236692                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14433.236692                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14433.236692                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14433.236692                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs         1663                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               63                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    26.396825                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         9012                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total         9012                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst         9012                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total         9012                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst         9012                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total         9012                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       184594                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       184594                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       184594                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       184594                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       184594                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       184594                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   2304763360                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   2304763360                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   2304763360                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   2304763360                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   2304763360                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   2304763360                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.113212                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.113212                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.113212                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.113212                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.113212                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.113212                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12485.581113                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12485.581113                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12485.581113                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12485.581113                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12485.581113                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12485.581113                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           203792                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          491.930753                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            2483389                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           204116                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            12.166557                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      43808643250                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   491.930753                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.960802                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.960802                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          324                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          324                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.632812                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         12059624                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        12059624                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      1586410                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1586410                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data       857564                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        857564                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        22125                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        22125                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        21120                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        21120                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      2443974                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         2443974                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      2443974                       # number of overall hits
system.cpu1.dcache.overall_hits::total        2443974                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       285731                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       285731                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       181299                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       181299                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         4484                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         4484                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data         2742                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         2742                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       467030                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        467030                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       467030                       # number of overall misses
system.cpu1.dcache.overall_misses::total       467030                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   4578373047                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   4578373047                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  10436073649                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  10436073649                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     56388497                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     56388497                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     20553927                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     20553927                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  15014446696                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  15014446696                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  15014446696                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  15014446696                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      1872141                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      1872141                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      1038863                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1038863                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        26609                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        26609                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        23862                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        23862                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      2911004                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      2911004                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      2911004                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      2911004                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.152623                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.152623                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.174517                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.174517                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.168514                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.168514                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.114911                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.114911                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.160436                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.160436                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.160436                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.160436                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16023.368297                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16023.368297                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 57562.775575                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 57562.775575                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12575.489964                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12575.489964                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7495.961707                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7495.961707                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32148.784224                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 32148.784224                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32148.784224                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 32148.784224                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs       370227                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             6127                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    60.425494                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       162776                       # number of writebacks
system.cpu1.dcache.writebacks::total           162776                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       104604                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       104604                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       148843                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       148843                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          899                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total          899                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       253447                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       253447                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       253447                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       253447                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       181127                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       181127                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        32456                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        32456                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         3585                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         3585                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         2742                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total         2742                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       213583                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       213583                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       213583                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       213583                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2418933900                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2418933900                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1545787184                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1545787184                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     26756251                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     26756251                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     15069073                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     15069073                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3964721084                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   3964721084                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3964721084                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   3964721084                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    485705000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    485705000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    998872003                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    998872003                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1484577003                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1484577003                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.096749                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.096749                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.031242                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.031242                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.134729                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.134729                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.114911                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.114911                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.073371                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.073371                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.073371                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.073371                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13354.905122                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13354.905122                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47627.162435                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 47627.162435                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7463.389400                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7463.389400                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5495.650255                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5495.650255                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18562.905681                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18562.905681                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18562.905681                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18562.905681                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    5026                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    189626                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   66604     40.25%     40.25% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    133      0.08%     40.33% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1926      1.16%     41.49% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    191      0.12%     41.61% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  96634     58.39%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              165488                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    65244     49.22%     49.22% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     133      0.10%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1926      1.45%     50.78% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     191      0.14%     50.92% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   65055     49.08%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               132549                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1865394285500     97.91%     97.91% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               63356500      0.00%     97.91% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              573165000      0.03%     97.94% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30               85999500      0.00%     97.95% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            39121861000      2.05%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1905238667500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.979581                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.673210                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.800958                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.45%      3.45% # number of syscalls executed
system.cpu0.kern.syscall::3                        20      8.62%     12.07% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.72%     13.79% # number of syscalls executed
system.cpu0.kern.syscall::6                        33     14.22%     28.02% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.43%     28.45% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      3.88%     32.33% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.31%     36.64% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.59%     39.22% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.43%     39.66% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.29%     40.95% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.02%     43.97% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.86%     44.83% # number of syscalls executed
system.cpu0.kern.syscall::45                       39     16.81%     61.64% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.29%     62.93% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.31%     67.24% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.31%     71.55% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.43%     71.98% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.59%     74.57% # number of syscalls executed
system.cpu0.kern.syscall::71                       27     11.64%     86.21% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.29%     87.50% # number of syscalls executed
system.cpu0.kern.syscall::74                        7      3.02%     90.52% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.43%     90.95% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.29%     92.24% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      3.88%     96.12% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.86%     96.98% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.86%     97.84% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.43%     98.28% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.86%     99.14% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.86%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   232                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  273      0.16%      0.16% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.16% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.16% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.16% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3846      2.21%      2.37% # number of callpals executed
system.cpu0.kern.callpal::tbi                      50      0.03%      2.39% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.40% # number of callpals executed
system.cpu0.kern.callpal::swpipl               158278     90.80%     93.20% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6346      3.64%     96.84% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.84% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     96.84% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.01%     96.85% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.85% # number of callpals executed
system.cpu0.kern.callpal::rti                    4961      2.85%     99.70% # number of callpals executed
system.cpu0.kern.callpal::callsys                 391      0.22%     99.92% # number of callpals executed
system.cpu0.kern.callpal::imb                     138      0.08%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                174309                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             7462                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1354                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1353                      
system.cpu0.kern.mode_good::user                 1354                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.181319                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.307055                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1903211741000     99.89%     99.89% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          2026918500      0.11%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3847                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    3999                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     49848                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   15658     37.06%     37.06% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1924      4.55%     41.62% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    273      0.65%     42.26% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  24392     57.74%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               42247                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    15641     47.10%     47.10% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1924      5.79%     52.90% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     273      0.82%     53.72% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   15369     46.28%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                33207                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1871713408000     98.26%     98.26% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              533048500      0.03%     98.29% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              128777500      0.01%     98.29% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            32519855000      1.71%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1904895089000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.998914                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.630084                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.786020                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        10     10.64%     10.64% # number of syscalls executed
system.cpu1.kern.syscall::6                         9      9.57%     20.21% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      1.06%     21.28% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      6.38%     27.66% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      3.19%     30.85% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      3.19%     34.04% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      4.26%     38.30% # number of syscalls executed
system.cpu1.kern.syscall::45                       15     15.96%     54.26% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      3.19%     57.45% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      1.06%     58.51% # number of syscalls executed
system.cpu1.kern.syscall::71                       27     28.72%     87.23% # number of syscalls executed
system.cpu1.kern.syscall::74                        9      9.57%     96.81% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      3.19%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                    94                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  191      0.44%      0.44% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.44% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.45% # number of callpals executed
system.cpu1.kern.callpal::swpctx                  742      1.70%      2.15% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.01%      2.15% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.02%      2.17% # number of callpals executed
system.cpu1.kern.callpal::swpipl                37463     85.96%     88.13% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2409      5.53%     93.66% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.66% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     93.67% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     93.68% # number of callpals executed
system.cpu1.kern.callpal::rti                    2587      5.94%     99.62% # number of callpals executed
system.cpu1.kern.callpal::callsys                 124      0.28%     99.90% # number of callpals executed
system.cpu1.kern.callpal::imb                      42      0.10%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 43580                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel              937                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                383                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2395                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                617                      
system.cpu1.kern.mode_good::user                  383                      
system.cpu1.kern.mode_good::idle                  234                      
system.cpu1.kern.mode_switch_good::kernel     0.658485                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.097704                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.332167                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel       34875641000      1.83%      1.83% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           708299500      0.04%      1.87% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1868990228500     98.13%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                     743                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------