path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.897858                       # Number of seconds simulated
sim_ticks                                1897857556000                       # Number of ticks simulated
final_tick                               1897857556000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  54087                       # Simulator instruction rate (inst/s)
host_op_rate                                    54087                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1829896991                       # Simulator tick rate (ticks/s)
host_mem_usage                                 335972                       # Number of bytes of host memory used
host_seconds                                  1037.14                       # Real time elapsed on the host
sim_insts                                    56096024                       # Number of instructions simulated
sim_ops                                      56096024                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst           762816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24264832                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2650624                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           217920                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           955136                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28851328                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       762816                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       217920                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          980736                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7805952                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7805952                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             11919                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            379138                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41416                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              3405                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             14924                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                450802                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          121968                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               121968                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              401935                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12785381                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1396640                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              114824                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              503271                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15202051                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         401935                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         114824                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             516760                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4113034                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4113034                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4113034                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             401935                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12785381                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1396640                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             114824                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             503271                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19315085                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        450802                       # Total number of read requests seen
system.physmem.writeReqs                       121968                       # Total number of write requests seen
system.physmem.cpureqs                         580318                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     28851328                       # Total number of bytes read from memory
system.physmem.bytesWritten                   7805952                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               28851328                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7805952                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       52                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               3354                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 28275                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 28002                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 28406                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 28112                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 28525                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 28215                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 27879                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 27987                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 28286                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 28166                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                28504                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                28315                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                28066                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                28252                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                27946                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                27814                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  7745                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  7549                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  7802                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  7514                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  7914                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  7617                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  7286                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  7435                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  7648                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  7558                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 7984                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 7855                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 7634                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 7769                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 7378                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 7280                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                         525                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1897852967000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  450802                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                 122493                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                 3354                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                    322811                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     66355                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     31450                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      6565                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2903                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2442                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1811                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      2029                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1666                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1950                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1569                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1554                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1659                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1788                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1259                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1496                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      916                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      256                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      143                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      121                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4091                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5028                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      5125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      5174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      5249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5262                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5292                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5292                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5295                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5302                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1212                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      275                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                     6654880960                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat               13976960960                       # Sum of mem lat for all requests
system.physmem.totBusLat                   1803000000                       # Total cycles spent in databus access
system.physmem.totBankLat                  5519080000                       # Total cycles spent in bank access
system.physmem.avgQLat                       14764.02                       # Average queueing delay per request
system.physmem.avgBankLat                    12244.22                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  31008.23                       # Average memory access latency
system.physmem.avgRdBW                          15.20                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           4.11                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  15.20                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   4.11                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.12                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.01                       # Average read queue length over time
system.physmem.avgWrQLen                         7.39                       # Average write queue length over time
system.physmem.readRowHits                     429728                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     77127                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   95.34                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  63.24                       # Row buffer hit rate for writes
system.physmem.avgGap                      3313464.33                       # Average gap between requests
system.l2c.replacements                        343886                       # number of replacements
system.l2c.tagsinuse                     65330.449226                       # Cycle average of tags in use
system.l2c.total_refs                         2612992                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        408910                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          6.390140                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                    5415654002                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        53692.952391                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          4245.749457                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          5529.153379                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst          1310.829137                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data           551.764862                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.819289                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.064785                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.084368                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.020002                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.008419                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.996864                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst             779502                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             594261                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             294591                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             226328                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1894682                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          840085                       # number of Writeback hits
system.l2c.Writeback_hits::total               840085                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             143                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              80                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 223                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            34                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            29                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                63                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           147131                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            42889                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               190020                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              779502                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              741392                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              294591                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              269217                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2084702                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             779502                       # number of overall hits
system.l2c.overall_hits::cpu0.data             741392                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             294591                       # number of overall hits
system.l2c.overall_hits::cpu1.data             269217                       # number of overall hits
system.l2c.overall_hits::total                2084702                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            11921                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           272257                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             3421                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1751                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               289350                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2525                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           517                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3042                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           47                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           90                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             137                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         107281                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          13452                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             120733                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             11921                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            379538                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              3421                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             15203                       # number of demand (read+write) misses
system.l2c.demand_misses::total                410083                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            11921                       # number of overall misses
system.l2c.overall_misses::cpu0.data           379538                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             3421                       # number of overall misses
system.l2c.overall_misses::cpu1.data            15203                       # number of overall misses
system.l2c.overall_misses::total               410083                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst    712478500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  11719521500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    222220000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    113744499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    12767964499                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       468000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       936000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      1404000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       313000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       113500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       426500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   7724029500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1451007500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   9175037000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst    712478500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  19443551000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    222220000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1564751999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     21943001499                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst    712478500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  19443551000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    222220000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1564751999                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    21943001499                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         791423                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         866518                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         298012                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         228079                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2184032                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       840085                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           840085                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2668                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          597                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3265                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           81                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          119                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           200                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       254412                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        56341                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           310753                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          791423                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1120930                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          298012                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          284420                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2494785                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         791423                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1120930                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         298012                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         284420                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2494785                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015063                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.314197                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.011479                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.007677                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.132484                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.946402                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.865997                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.931700                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.580247                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.756303                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.685000                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.421682                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.238760                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.388518                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015063                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.338592                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.011479                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.053453                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.164376                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015063                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.338592                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.011479                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.053453                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.164376                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 59766.672259                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 43045.804148                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 64957.614733                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 64959.736722                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 44126.367717                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   185.346535                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1810.444874                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   461.538462                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6659.574468                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1261.111111                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3113.138686                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71998.112434                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 107865.559025                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 75994.442282                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 59766.672259                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 51229.523789                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 64957.614733                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 102923.896534                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 53508.683606                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 59766.672259                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 51229.523789                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 64957.614733                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 102923.896534                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 53508.683606                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               80445                       # number of writebacks
system.l2c.writebacks::total                    80445                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst            16                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             16                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            16                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        11920                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       272257                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         3405                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1750                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          289332                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2525                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          517                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3042                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           47                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           90                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          137                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       107281                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        13452                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        120733                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        11920                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       379538                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         3405                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        15202                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           410065                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        11920                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       379538                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         3405                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        15202                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          410065                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    561911095                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data   8192955588                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    178565558                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    113324293                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   9046756534                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     25301493                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      5294512                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     30596005                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       516543                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       904088                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      1420631                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   6410159669                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1283732505                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   7693892174                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    561911095                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  14603115257                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    178565558                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1397056798                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16740648708                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    561911095                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  14603115257                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    178565558                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1397056798                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16740648708                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    936053000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    455620500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1391673500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1587348000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    874199500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2461547500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2523401000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1329820000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   3853221000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015061                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.314197                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.011426                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.007673                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.132476                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.946402                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.865997                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.931700                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.580247                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.756303                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.685000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.421682                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.238760                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.388518                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015061                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.338592                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011426                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.053449                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.164369                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015061                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.338592                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011426                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.053449                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.164369                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 47140.192534                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.727048                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 52442.160940                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64756.738857                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 31267.735798                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10020.393267                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10240.835590                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10057.858317                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10990.276596                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10045.422222                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10369.569343                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59751.117803                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 95430.605486                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 63726.505380                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 47140.192534                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38476.029428                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52442.160940                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 91899.539403                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40824.378350                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 47140.192534                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38476.029428                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52442.160940                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 91899.539403                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40824.378350                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41695                       # number of replacements
system.iocache.tagsinuse                     0.486173                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41711                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1705465376000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       0.486173                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.030386                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.030386                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          172                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              172                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41724                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41724                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41724                       # number of overall misses
system.iocache.overall_misses::total            41724                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     20816998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     20816998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide   9540304806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   9540304806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide   9561121804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   9561121804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide   9561121804                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   9561121804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          172                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            172                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41724                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41724                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41724                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41724                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121029.058140                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 121029.058140                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229599.172266                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 229599.172266                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 229151.610680                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 229151.610680                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 229151.610680                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 229151.610680                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        192730                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                23021                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.371921                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41523                       # number of writebacks
system.iocache.writebacks::total                41523                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          172                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          172                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41724                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41724                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41724                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41724                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11872000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     11872000                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   7377518046                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   7377518046                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   7389390046                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   7389390046                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   7389390046                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   7389390046                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69023.255814                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 69023.255814                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177549.048084                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 177549.048084                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 177101.669207                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 177101.669207                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 177101.669207                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 177101.669207                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     7996955                       # DTB read hits
system.cpu0.dtb.read_misses                     29938                       # DTB read misses
system.cpu0.dtb.read_acv                          553                       # DTB read access violations
system.cpu0.dtb.read_accesses                  624438                       # DTB read accesses
system.cpu0.dtb.write_hits                    5309744                       # DTB write hits
system.cpu0.dtb.write_misses                     7955                       # DTB write misses
system.cpu0.dtb.write_acv                         319                       # DTB write access violations
system.cpu0.dtb.write_accesses                 207916                       # DTB write accesses
system.cpu0.dtb.data_hits                    13306699                       # DTB hits
system.cpu0.dtb.data_misses                     37893                       # DTB misses
system.cpu0.dtb.data_acv                          872                       # DTB access violations
system.cpu0.dtb.data_accesses                  832354                       # DTB accesses
system.cpu0.itb.fetch_hits                     944692                       # ITB hits
system.cpu0.itb.fetch_misses                    28693                       # ITB misses
system.cpu0.itb.fetch_acv                         988                       # ITB acv
system.cpu0.itb.fetch_accesses                 973385                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                        92901317                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                11220993                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted           9498823                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect            301088                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups              7731310                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                 4807164                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                  696053                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect              31347                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles          22682478                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      57580156                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   11220993                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           5503217                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     10836671                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1573403                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles              32658351                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles               28974                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       198560                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       186652                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          190                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  6976582                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               207142                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples          67595352                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.851836                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.189286                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                56758681     83.97%     83.97% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  707820      1.05%     85.02% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1385949      2.05%     87.07% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  615643      0.91%     87.98% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2401218      3.55%     91.53% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  457628      0.68%     92.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  501258      0.74%     92.95% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  784291      1.16%     94.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 3982864      5.89%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            67595352                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.120784                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.619799                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                23783356                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             32156359                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  9819480                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               864593                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                971563                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              447466                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                32236                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              56434658                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts                99123                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                971563                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                24717335                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               12372612                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      16597679                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  9220139                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              3716022                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              53261468                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 6752                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                462341                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1402867                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands           35633564                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             64862965                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        64519168                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           343797                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             31292257                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 4341299                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1345733                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        201778                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 10181749                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             8375667                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5571987                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1008121                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores          649590                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  47223004                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1661663                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 46145441                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            96356                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        5312296                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      2839377                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1124463                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     67595352                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.682672                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.326673                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           46917740     69.41%     69.41% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            9524699     14.09%     83.50% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            4257234      6.30%     89.80% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2757377      4.08%     93.88% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2128651      3.15%     97.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1105682      1.64%     98.66% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             579516      0.86%     99.52% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             281591      0.42%     99.94% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              42862      0.06%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       67595352                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  67879     11.08%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     11.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                286167     46.73%     57.81% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               258352     42.19%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             3762      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             31627354     68.54%     68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               48263      0.10%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              14877      0.03%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1879      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             8323640     18.04%     86.73% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5371898     11.64%     98.37% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            753768      1.63%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              46145441                       # Type of FU issued
system.cpu0.iq.rate                          0.496715                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     612398                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.013271                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         160102230                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         53968976                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     45199549                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             492757                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            238910                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       232575                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              46496253                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 257824                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          502915                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1032397                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2215                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        11166                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       416538                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        13927                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       141497                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                971563                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                8614462                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               715502                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           51740003                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           598208                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              8375667                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5571987                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1467274                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                578076                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 5429                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         11166                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        147373                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       320873                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              468246                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             45797277                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              8048095                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           348163                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      2855336                       # number of nop insts executed
system.cpu0.iew.exec_refs                    13377753                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 7249094                       # Number of branches executed
system.cpu0.iew.exec_stores                   5329658                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.492967                       # Inst execution rate
system.cpu0.iew.wb_sent                      45516467                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     45432124                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 22555336                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 30242853                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.489036                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.745807                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        5732411                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         537200                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           438547                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     66623789                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.689159                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.608194                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     49353923     74.08%     74.08% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      7278183     10.92%     85.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      3860099      5.79%     90.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2143933      3.22%     94.01% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1188584      1.78%     95.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       481737      0.72%     96.52% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       414393      0.62%     97.14% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       388678      0.58%     97.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1514259      2.27%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     66623789                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            45914377                       # Number of instructions committed
system.cpu0.commit.committedOps              45914377                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      12498719                       # Number of memory references committed
system.cpu0.commit.loads                      7343270                       # Number of loads committed
system.cpu0.commit.membars                     179286                       # Number of memory barriers committed
system.cpu0.commit.branches                   6902899                       # Number of branches committed
system.cpu0.commit.fp_insts                    230540                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 42546523                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              573621                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1514259                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   116563585                       # The number of ROB reads
system.cpu0.rob.rob_writes                  104266102                       # The number of ROB writes
system.cpu0.timesIdled                         937015                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       25305965                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3702808960                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   43304295                       # Number of Instructions Simulated
system.cpu0.committedOps                     43304295                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             43304295                       # Number of Instructions Simulated
system.cpu0.cpi                              2.145314                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.145314                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.466132                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.466132                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                60234005                       # number of integer regfile reads
system.cpu0.int_regfile_writes               32862786                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   114240                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  115409                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1567878                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                765605                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.icache.replacements                790851                       # number of replacements
system.cpu0.icache.tagsinuse               510.328171                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 6144778                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                791359                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  7.764843                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           20315369000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   510.328171                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.996735                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.996735                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      6144778                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        6144778                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      6144778                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         6144778                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      6144778                       # number of overall hits
system.cpu0.icache.overall_hits::total        6144778                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       831804                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       831804                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       831804                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        831804                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       831804                       # number of overall misses
system.cpu0.icache.overall_misses::total       831804                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11563264492                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  11563264492                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  11563264492                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  11563264492                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  11563264492                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  11563264492                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      6976582                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      6976582                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      6976582                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      6976582                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      6976582                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      6976582                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.119228                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.119228                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.119228                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.119228                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.119228                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.119228                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13901.429293                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13901.429293                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13901.429293                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13901.429293                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13901.429293                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13901.429293                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         2068                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets         1976                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              129                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              2                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.031008                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          988                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        40285                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        40285                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        40285                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        40285                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        40285                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        40285                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       791519                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       791519                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       791519                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       791519                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       791519                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       791519                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9521125993                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   9521125993                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9521125993                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   9521125993                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9521125993                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   9521125993                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.113454                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.113454                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.113454                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.113454                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.113454                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.113454                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12028.929177                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12028.929177                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12028.929177                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12028.929177                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12028.929177                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12028.929177                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1122816                       # number of replacements
system.cpu0.dcache.tagsinuse               467.302243                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                 9451134                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1123328                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                  8.413512                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              21802000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   467.302243                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.912700                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.912700                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      5816576                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5816576                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3291002                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3291002                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       156681                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       156681                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       180603                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       180603                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      9107578                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         9107578                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      9107578                       # number of overall hits
system.cpu0.dcache.overall_hits::total        9107578                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1395487                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1395487                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1670757                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1670757                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        17192                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        17192                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data          672                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total          672                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3066244                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3066244                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3066244                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3066244                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  31388896500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  31388896500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  67591367114                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  67591367114                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    251807000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    251807000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      4104500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      4104500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  98980263614                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  98980263614                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  98980263614                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  98980263614                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7212063                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      7212063                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4961759                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4961759                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       173873                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       173873                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       181275                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       181275                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     12173822                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     12173822                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     12173822                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     12173822                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.193493                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.193493                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.336727                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.336727                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.098877                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.098877                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.003707                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.003707                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.251872                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.251872                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.251872                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.251872                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22493.148628                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 22493.148628                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.534296                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.534296                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.754304                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.754304                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6107.886905                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6107.886905                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.622029                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 32280.622029                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.622029                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 32280.622029                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      2359081                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets          919                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            46623                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    50.599082                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   131.285714                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       614637                       # number of writebacks
system.cpu0.dcache.writebacks::total           614637                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       536909                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       536909                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1412908                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1412908                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         3986                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         3986                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1949817                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1949817                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1949817                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1949817                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       858578                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       858578                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       257849                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       257849                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13206                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13206                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          672                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total          672                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1116427                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1116427                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1116427                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1116427                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  19432503500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  19432503500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9843225787                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9843225787                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    161840000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    161840000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      2760500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      2760500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  29275729287                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  29275729287                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  29275729287                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  29275729287                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    998479000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    998479000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1684532498                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1684532498                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2683011498                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2683011498                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.119047                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.119047                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051967                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051967                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.075952                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.075952                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.003707                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.003707                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.091707                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.091707                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.091707                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.091707                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22633.358297                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22633.358297                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.380304                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.380304                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12255.035590                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12255.035590                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4107.886905                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4107.886905                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.699099                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.699099                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.699099                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.699099                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     2657978                       # DTB read hits
system.cpu1.dtb.read_misses                     12789                       # DTB read misses
system.cpu1.dtb.read_acv                           27                       # DTB read access violations
system.cpu1.dtb.read_accesses                  325192                       # DTB read accesses
system.cpu1.dtb.write_hits                    1642917                       # DTB write hits
system.cpu1.dtb.write_misses                     2443                       # DTB write misses
system.cpu1.dtb.write_acv                          63                       # DTB write access violations
system.cpu1.dtb.write_accesses                 132832                       # DTB write accesses
system.cpu1.dtb.data_hits                     4300895                       # DTB hits
system.cpu1.dtb.data_misses                     15232                       # DTB misses
system.cpu1.dtb.data_acv                           90                       # DTB access violations
system.cpu1.dtb.data_accesses                  458024                       # DTB accesses
system.cpu1.itb.fetch_hits                     468004                       # ITB hits
system.cpu1.itb.fetch_misses                     6860                       # ITB misses
system.cpu1.itb.fetch_acv                         223                       # ITB acv
system.cpu1.itb.fetch_accesses                 474864                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                        24425153                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                 3729082                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted           3054181                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect            119454                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups              2320080                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                 1316503                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                  271618                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect              12328                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles           8114039                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      17895150                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    3729082                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           1588121                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      3257695                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 589472                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles               9888414                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles               24413                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        65338                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       153630                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          457                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  2125845                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                78173                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples          21892478                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.817411                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.179159                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                18634783     85.12%     85.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  188286      0.86%     85.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  405463      1.85%     87.83% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  257415      1.18%     89.01% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  494264      2.26%     91.27% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  174627      0.80%     92.06% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  196879      0.90%     92.96% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  233860      1.07%     94.03% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 1306901      5.97%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            21892478                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.152674                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.732653                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 8206589                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             10101487                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  3024410                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               183126                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                376865                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              172901                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                11788                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              17533822                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                34638                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                376865                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 8509918                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                2827280                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       6300792                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  2835388                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              1042233                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              16406070                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                  208                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                240400                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents               230284                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands           10874634                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups             19629751                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        19484062                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           145689                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps              9164172                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 1710462                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            526024                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         52355                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  3079996                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             2820928                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            1739172                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           303279                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          178063                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  14428831                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             617828                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 13962547                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            36109                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        2150385                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined      1081456                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        443630                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     21892478                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.637778                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.318020                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           15854245     72.42%     72.42% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            2672796     12.21%     84.63% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            1184242      5.41%     90.04% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             847687      3.87%     93.91% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             726248      3.32%     97.23% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             300582      1.37%     98.60% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             191038      0.87%     99.47% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             101044      0.46%     99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              14596      0.07%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       21892478                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  17685      7.13%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      7.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                130361     52.59%     59.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                99827     40.27%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             3526      0.03%      0.03% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              9165178     65.64%     65.67% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               22201      0.16%     65.83% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     65.83% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd              10896      0.08%     65.90% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     65.90% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     65.90% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     65.90% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1763      0.01%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     65.92% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             2775695     19.88%     85.80% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            1670228     11.96%     97.76% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            313060      2.24%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              13962547                       # Type of FU issued
system.cpu1.iq.rate                          0.571646                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     247873                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.017753                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          49890568                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         17097827                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     13608739                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads             210986                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            102380                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses        99816                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              14096605                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 110289                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          133191                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       414475                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          850                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         3253                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       172072                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads         4939                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        13663                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                376865                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                2193721                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               124101                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           15871795                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           185761                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              2820928                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             1739172                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            554609                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 45814                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 2212                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          3253                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         57900                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       130435                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              188335                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             13825969                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              2678414                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           136578                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       825136                       # number of nop insts executed
system.cpu1.iew.exec_refs                     4329493                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 2168898                       # Number of branches executed
system.cpu1.iew.exec_stores                   1651079                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.566055                       # Inst execution rate
system.cpu1.iew.wb_sent                      13745874                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     13708555                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  6651311                       # num instructions producing a value
system.cpu1.iew.wb_consumers                  9340604                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.561247                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.712086                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        2293261                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         174198                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           176022                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     21515613                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.628195                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.562431                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     16491806     76.65%     76.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      2174989     10.11%     86.76% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      1058158      4.92%     91.68% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       548223      2.55%     94.23% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       352308      1.64%     95.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       166690      0.77%     96.64% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       160522      0.75%     97.38% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       129128      0.60%     97.98% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       433789      2.02%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     21515613                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            13515996                       # Number of instructions committed
system.cpu1.commit.committedOps              13515996                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       3973553                       # Number of memory references committed
system.cpu1.commit.loads                      2406453                       # Number of loads committed
system.cpu1.commit.membars                      57533                       # Number of memory barriers committed
system.cpu1.commit.branches                   2017672                       # Number of branches committed
system.cpu1.commit.fp_insts                     98521                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 12496541                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              216490                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events               433789                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                    36803153                       # The number of ROB reads
system.cpu1.rob.rob_writes                   31994561                       # The number of ROB writes
system.cpu1.timesIdled                         237566                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        2532675                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3770663279                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   12791729                       # Number of Instructions Simulated
system.cpu1.committedOps                     12791729                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             12791729                       # Number of Instructions Simulated
system.cpu1.cpi                              1.909449                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.909449                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.523711                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.523711                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                17892474                       # number of integer regfile reads
system.cpu1.int_regfile_writes                9829261                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    54188                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   54153                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 592079                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                255780                       # number of misc regfile writes
system.cpu1.icache.replacements                297472                       # number of replacements
system.cpu1.icache.tagsinuse               505.689996                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 1814153                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                297984                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                  6.088089                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle           42534295000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   505.689996                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.987676                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.987676                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      1814153                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        1814153                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      1814153                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         1814153                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      1814153                       # number of overall hits
system.cpu1.icache.overall_hits::total        1814153                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       311692                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       311692                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       311692                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        311692                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       311692                       # number of overall misses
system.cpu1.icache.overall_misses::total       311692                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4307826496                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4307826496                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4307826496                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4307826496                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4307826496                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4307826496                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      2125845                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      2125845                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      2125845                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      2125845                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      2125845                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      2125845                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.146620                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.146620                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.146620                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.146620                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.146620                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.146620                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13820.779795                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13820.779795                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13820.779795                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13820.779795                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13820.779795                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13820.779795                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs          806                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets          423                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               43                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    18.744186                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          423                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        13650                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        13650                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        13650                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        13650                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        13650                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        13650                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       298042                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       298042                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       298042                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       298042                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       298042                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       298042                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3567181997                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   3567181997                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3567181997                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   3567181997                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3567181997                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   3567181997                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.140199                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.140199                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.140199                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.140199                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.140199                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.140199                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11968.722519                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11968.722519                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11968.722519                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11968.722519                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11968.722519                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11968.722519                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                296647                       # number of replacements
system.cpu1.dcache.tagsinuse               497.527759                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 3293413                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                297044                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 11.087290                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           36352469000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   497.527759                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.971734                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.971734                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      2035773                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        2035773                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      1175370                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       1175370                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        40064                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        40064                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        42523                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        42523                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      3211143                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         3211143                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      3211143                       # number of overall hits
system.cpu1.dcache.overall_hits::total        3211143                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       433262                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       433262                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       341345                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       341345                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         7035                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         7035                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data          718                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total          718                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       774607                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        774607                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       774607                       # number of overall misses
system.cpu1.dcache.overall_misses::total       774607                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6736455500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   6736455500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  13519924674                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  13519924674                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    102051000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    102051000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      5076000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total      5076000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  20256380174                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  20256380174                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  20256380174                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  20256380174                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      2469035                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      2469035                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      1516715                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1516715                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        47099                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        47099                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        43241                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        43241                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      3985750                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      3985750                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      3985750                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      3985750                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.175478                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.175478                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.225055                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.225055                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.149366                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.149366                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.016605                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.016605                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.194344                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.194344                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.194344                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.194344                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.226016                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.226016                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39607.800536                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 39607.800536                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14506.183369                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14506.183369                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7069.637883                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7069.637883                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.525588                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 26150.525588                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.525588                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 26150.525588                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs       473544                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            3                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             7013                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    67.523742                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets            3                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       225448                       # number of writebacks
system.cpu1.dcache.writebacks::total           225448                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       193837                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       193837                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       283225                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       283225                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1368                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1368                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       477062                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       477062                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       477062                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       477062                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       239425                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       239425                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        58120                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        58120                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5667                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5667                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          718                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total          718                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       297545                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       297545                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       297545                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       297545                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   3123299000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   3123299000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2029112304                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2029112304                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     67015000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     67015000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      3640000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      3640000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   5152411304                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   5152411304                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5152411304                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   5152411304                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    486888000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    486888000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    925465000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    925465000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1412353000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1412353000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.096971                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.096971                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.038320                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.038320                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.120321                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.120321                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.016605                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.016605                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.074652                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.074652                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.074652                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.074652                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.999478                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.999478                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34912.462216                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34912.462216                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11825.480854                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11825.480854                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5069.637883                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5069.637883                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.410304                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.410304                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.410304                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.410304                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    4836                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    169372                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   58506     39.88%     39.88% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    135      0.09%     39.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1925      1.31%     41.28% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                     16      0.01%     41.29% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  86127     58.71%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              146709                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    57513     49.12%     49.12% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     135      0.12%     49.23% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1925      1.64%     50.88% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                      16      0.01%     50.89% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   57499     49.11%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               117088                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1866028984500     98.32%     98.32% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               63917500      0.00%     98.33% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              571228500      0.03%     98.36% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30                8802500      0.00%     98.36% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            31183758000      1.64%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1897856691000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.983027                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.667607                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.798097                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         7      3.35%      3.35% # number of syscalls executed
system.cpu0.kern.syscall::3                        17      8.13%     11.48% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.91%     13.40% # number of syscalls executed
system.cpu0.kern.syscall::6                        29     13.88%     27.27% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.48%     27.75% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      4.31%     32.06% # number of syscalls executed
system.cpu0.kern.syscall::19                        7      3.35%     35.41% # number of syscalls executed
system.cpu0.kern.syscall::20                        4      1.91%     37.32% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.48%     37.80% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.44%     39.23% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.35%     42.58% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.96%     43.54% # number of syscalls executed
system.cpu0.kern.syscall::45                       37     17.70%     61.24% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.44%     62.68% # number of syscalls executed
system.cpu0.kern.syscall::48                        8      3.83%     66.51% # number of syscalls executed
system.cpu0.kern.syscall::54                        9      4.31%     70.81% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.48%     71.29% # number of syscalls executed
system.cpu0.kern.syscall::59                        5      2.39%     73.68% # number of syscalls executed
system.cpu0.kern.syscall::71                       27     12.92%     86.60% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.44%     88.04% # number of syscalls executed
system.cpu0.kern.syscall::74                        7      3.35%     91.39% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.48%     91.87% # number of syscalls executed
system.cpu0.kern.syscall::90                        2      0.96%     92.82% # number of syscalls executed
system.cpu0.kern.syscall::92                        7      3.35%     96.17% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.96%     97.13% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.96%     98.09% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.48%     98.56% # number of syscalls executed
system.cpu0.kern.syscall::144                       1      0.48%     99.04% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.96%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   209                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  100      0.06%      0.07% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.07% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.07% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.07% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3082      1.99%      2.06% # number of callpals executed
system.cpu0.kern.callpal::tbi                      48      0.03%      2.09% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.09% # number of callpals executed
system.cpu0.kern.callpal::swpipl               140299     90.69%     92.78% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6336      4.10%     96.88% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.88% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     96.88% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     8      0.01%     96.89% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.89% # number of callpals executed
system.cpu0.kern.callpal::rti                    4335      2.80%     99.69% # number of callpals executed
system.cpu0.kern.callpal::callsys                 342      0.22%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     137      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                154704                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             6439                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1272                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1271                      
system.cpu0.kern.mode_good::user                 1272                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.197391                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.329789                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1895973773500     99.90%     99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          1882909500      0.10%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3083                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    3800                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     68195                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   23112     38.67%     38.67% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1924      3.22%     41.89% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    100      0.17%     42.06% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  34629     57.94%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               59765                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    22728     47.97%     47.97% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1924      4.06%     52.03% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     100      0.21%     52.24% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   22629     47.76%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                47381                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1870052426500     98.55%     98.55% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              533448500      0.03%     98.58% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30               47034500      0.00%     98.58% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            26913191500      1.42%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1897546101000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.983385                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.653470                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.792788                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2                         1      0.85%      0.85% # number of syscalls executed
system.cpu1.kern.syscall::3                        13     11.11%     11.97% # number of syscalls executed
system.cpu1.kern.syscall::6                        13     11.11%     23.08% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.85%     23.93% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      5.13%     29.06% # number of syscalls executed
system.cpu1.kern.syscall::19                        3      2.56%     31.62% # number of syscalls executed
system.cpu1.kern.syscall::20                        2      1.71%     33.33% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.56%     35.90% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.56%     38.46% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      3.42%     41.88% # number of syscalls executed
system.cpu1.kern.syscall::45                       17     14.53%     56.41% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.56%     58.97% # number of syscalls executed
system.cpu1.kern.syscall::48                        2      1.71%     60.68% # number of syscalls executed
system.cpu1.kern.syscall::54                        1      0.85%     61.54% # number of syscalls executed
system.cpu1.kern.syscall::59                        2      1.71%     63.25% # number of syscalls executed
system.cpu1.kern.syscall::71                       27     23.08%     86.32% # number of syscalls executed
system.cpu1.kern.syscall::74                        9      7.69%     94.02% # number of syscalls executed
system.cpu1.kern.syscall::90                        1      0.85%     94.87% # number of syscalls executed
system.cpu1.kern.syscall::92                        2      1.71%     96.58% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.56%     99.15% # number of syscalls executed
system.cpu1.kern.syscall::144                       1      0.85%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   117                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                   16      0.03%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 1165      1.89%      1.92% # number of callpals executed
system.cpu1.kern.callpal::tbi                       6      0.01%      1.93% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      1.94% # number of callpals executed
system.cpu1.kern.callpal::swpipl                54867     89.09%     91.04% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2419      3.93%     94.96% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.96% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     94.97% # number of callpals executed
system.cpu1.kern.callpal::rdusp                     1      0.00%     94.97% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.00%     94.98% # number of callpals executed
system.cpu1.kern.callpal::rti                    2874      4.67%     99.64% # number of callpals executed
system.cpu1.kern.callpal::callsys                 175      0.28%     99.93% # number of callpals executed
system.cpu1.kern.callpal::imb                      43      0.07%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 61585                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             1629                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                476                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2046                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                537                      
system.cpu1.kern.mode_good::user                  476                      
system.cpu1.kern.mode_good::idle                   61                      
system.cpu1.kern.mode_switch_good::kernel     0.329650                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.029814                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.258733                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel       37752222500      1.99%      1.99% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           817466500      0.04%      2.03% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1858966004500     97.97%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    1166                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------