path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.903124                       # Number of seconds simulated
sim_ticks                                1903123778500                       # Number of ticks simulated
final_tick                               1903123778500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 103415                       # Simulator instruction rate (inst/s)
host_op_rate                                   103415                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3505224116                       # Simulator tick rate (ticks/s)
host_mem_usage                                 322696                       # Number of bytes of host memory used
host_seconds                                   542.94                       # Real time elapsed on the host
sim_insts                                    56148221                       # Number of instructions simulated
sim_ops                                      56148221                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst           744192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24296448                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           238144                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          1067328                       # Number of bytes read from this memory
system.physmem.bytes_read::total             26347072                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       744192                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       238144                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          982336                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      5275328                       # Number of bytes written to this memory
system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7934656                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             11628                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            379632                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              3721                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             16677                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                411673                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           82427                       # Number of write requests responded to by this memory
system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               123979                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              391037                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12766615                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               504                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              125133                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              560830                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13844119                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         391037                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         125133                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             516170                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2771931                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::tsunami.ide          1397349                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4169280                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2771931                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             391037                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12766615                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1397853                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             125133                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             560830                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               18013399                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        411673                       # Number of read requests accepted
system.physmem.writeReqs                       123979                       # Number of write requests accepted
system.physmem.readBursts                      411673                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     123979                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 26335040                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     12032                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7932928                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  26347072                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7934656                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      188                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           3444                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               25632                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25720                       # Per bank write bursts
system.physmem.perBankRdBursts::2               26346                       # Per bank write bursts
system.physmem.perBankRdBursts::3               25660                       # Per bank write bursts
system.physmem.perBankRdBursts::4               25672                       # Per bank write bursts
system.physmem.perBankRdBursts::5               25150                       # Per bank write bursts
system.physmem.perBankRdBursts::6               25568                       # Per bank write bursts
system.physmem.perBankRdBursts::7               25491                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25973                       # Per bank write bursts
system.physmem.perBankRdBursts::9               26167                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25812                       # Per bank write bursts
system.physmem.perBankRdBursts::11              25687                       # Per bank write bursts
system.physmem.perBankRdBursts::12              26023                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25844                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25108                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25632                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8431                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7989                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8275                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7382                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7684                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7400                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7193                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7021                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7374                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7755                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7777                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7454                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8052                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8097                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7762                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8306                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
system.physmem.totGap                    1903119235000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  411673                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 123979                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    317912                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     40920                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     43295                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9256                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        77                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        14                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1682                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2373                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3331                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4398                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5849                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     7355                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     8902                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     9229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     9378                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9073                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8320                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6563                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6410                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6317                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6098                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      278                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      171                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      186                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       70                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       16                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        64910                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      527.930488                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     320.008348                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     417.202697                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          14944     23.02%     23.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        11454     17.65%     40.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5213      8.03%     48.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2920      4.50%     53.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2279      3.51%     56.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1787      2.75%     59.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1551      2.39%     61.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1716      2.64%     64.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        23046     35.50%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          64910                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5635                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        73.021650                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2812.727565                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           5632     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5635                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5635                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        21.996806                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.958563                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       19.289473                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            4843     85.94%     85.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             143      2.54%     88.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              10      0.18%     88.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             227      4.03%     92.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              45      0.80%     93.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39               4      0.07%     93.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              10      0.18%     93.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              10      0.18%     93.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              34      0.60%     94.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               6      0.11%     94.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               5      0.09%     94.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               2      0.04%     94.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67               9      0.16%     94.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               2      0.04%     94.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.07%     95.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               1      0.02%     95.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              41      0.73%     95.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87              13      0.23%     95.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.04%     96.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99             176      3.12%     99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             5      0.09%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             3      0.05%     99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             3      0.05%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.02%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             6      0.11%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             3      0.05%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             6      0.11%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143            10      0.18%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             6      0.11%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5635                       # Writes before turning the bus around for reads
system.physmem.totQLat                     3887945250                       # Total ticks spent queuing
system.physmem.totMemAccLat               11603289000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2057425000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9448.57                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28198.57                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.84                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           4.17                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.84                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        4.17                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.66                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.85                       # Average write queue length when enqueuing
system.physmem.readRowHits                     371100                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     99427                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.19                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.20                       # Row buffer hit rate for writes
system.physmem.avgGap                      3552902.32                       # Average gap between requests
system.physmem.pageHitRate                      87.87                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     1802319562500                       # Time in different power states
system.physmem.memoryStateTime::REF       63549460000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       37254262500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                     18054612                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              296849                       # Transaction distribution
system.membus.trans_dist::ReadResp             296569                       # Transaction distribution
system.membus.trans_dist::WriteReq              12351                       # Transaction distribution
system.membus.trans_dist::WriteResp             12351                       # Transaction distribution
system.membus.trans_dist::Writeback             82427                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             5284                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq           1479                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            3444                       # Transaction distribution
system.membus.trans_dist::ReadExReq            122594                       # Transaction distribution
system.membus.trans_dist::ReadExResp           122459                       # Transaction distribution
system.membus.trans_dist::BadAddressError          280                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        39092                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       916085                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          560                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       955737                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83294                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        83294                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1039031                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        68194                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31621440                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     31689634                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2660288                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      2660288                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            34349922                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               34349922                       # Total data (bytes)
system.membus.snoop_data_through_bus            10240                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            35504996                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1560042750                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer2.occupancy              374000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3834491323                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy           43141738                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                   345839                       # number of replacements
system.l2c.tags.tagsinuse                65302.356632                       # Cycle average of tags in use
system.l2c.tags.total_refs                    2646364                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   411006                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     6.438748                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               7093732750                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   53566.898021                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4193.415796                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     5564.276304                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1386.450480                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      591.316031                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.817366                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.063986                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.084904                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.021156                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.009023                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.996435                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        65167                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          225                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1         2289                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         6029                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6100                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        50524                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.994370                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 27707761                       # Number of tag accesses
system.l2c.tags.data_accesses                27707761                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst             751132                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             546267                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             350558                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             278844                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1926801                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          841911                       # number of Writeback hits
system.l2c.Writeback_hits::total               841911                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             128                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              75                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 203                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            36                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            37                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                73                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           140399                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            48308                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               188707                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              751132                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              686666                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              350558                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              327152                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2115508                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             751132                       # number of overall hits
system.l2c.overall_hits::cpu0.data             686666                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             350558                       # number of overall hits
system.l2c.overall_hits::cpu1.data             327152                       # number of overall hits
system.l2c.overall_hits::total                2115508                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            11641                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           272205                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             3725                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1926                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               289497                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2575                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           542                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3117                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           63                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          103                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             166                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         107603                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          15017                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             122620                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             11641                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            379808                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              3725                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             16943                       # number of demand (read+write) misses
system.l2c.demand_misses::total                412117                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            11641                       # number of overall misses
system.l2c.overall_misses::cpu0.data           379808                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             3725                       # number of overall misses
system.l2c.overall_misses::cpu1.data            16943                       # number of overall misses
system.l2c.overall_misses::total               412117                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst    889120500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  17862600250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    290708250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    148179250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    19190608250                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       882962                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      1281445                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      2164407                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       245491                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       187992                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       433483                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   8878273882                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1456523709                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  10334797591                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst    889120500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  26740874132                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    290708250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1604702959                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     29525405841                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst    889120500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  26740874132                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    290708250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1604702959                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    29525405841                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         762773                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         818472                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         354283                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         280770                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2216298                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       841911                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           841911                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2703                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          617                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3320                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           99                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          140                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           239                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       248002                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        63325                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           311327                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          762773                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1066474                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          354283                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          344095                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2527625                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         762773                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1066474                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         354283                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         344095                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2527625                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015261                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.332577                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010514                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.006860                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.130622                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.952645                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.878444                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.938855                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.636364                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.735714                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.694561                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.433880                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.237142                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.393862                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015261                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.356134                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010514                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.049239                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.163045                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015261                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.356134                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010514                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.049239                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.163045                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76378.360966                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 65621.866792                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78042.483221                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 76936.266874                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 66289.489183                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   342.897864                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2364.289668                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   694.387873                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3896.682540                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1825.165049                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  2611.343373                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82509.538600                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 96991.656722                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 84283.131553                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 76378.360966                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 70406.295107                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 78042.483221                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 94711.854984                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 71643.261115                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 76378.360966                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 70406.295107                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 78042.483221                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 94711.854984                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 71643.261115                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               82427                       # number of writebacks
system.l2c.writebacks::total                    82427                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst            13                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst             13                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst            13                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        11628                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       272204                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         3721                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1926                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          289479                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2575                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          542                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3117                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           63                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          103                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          166                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       107603                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        15017                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        122620                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        11628                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       379807                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         3721                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        16943                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           412099                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        11628                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       379807                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         3721                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        16943                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          412099                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    741621000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  14467164750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    243575500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    151890250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  15604251500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     25805570                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      5431039                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     31236609                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       646561                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      1036098                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      1682659                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7566064618                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1272103789                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   8838168407                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    741621000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  22033229368                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    243575500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1423994039                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  24442419907                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    741621000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  22033229368                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    243575500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1423994039                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  24442419907                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    930400500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    458814500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1389215000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1575945000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    887867500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2463812500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2506345500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1346682000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   3853027500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015244                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.332576                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010503                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.006860                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.130614                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.952645                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.878444                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.938855                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.636364                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.735714                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.694561                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.433880                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.237142                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.393862                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015244                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.356133                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010503                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.049239                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.163038                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015244                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.356133                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010503                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.049239                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.163038                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63778.895769                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53148.244515                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65459.688256                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78863.058152                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 53904.606206                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.580583                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.367159                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10021.369586                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10262.873016                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10059.203883                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10136.500000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70314.625224                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84710.913565                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 72077.706793                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63778.895769                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58011.646357                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65459.688256                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84046.157056                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 59312.009753                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63778.895769                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58011.646357                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65459.688256                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84046.157056                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 59312.009753                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                41695                       # number of replacements
system.iocache.tags.tagsinuse                0.219567                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41711                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1710336549000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     0.219567                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.013723                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.013723                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375543                       # Number of tag accesses
system.iocache.tags.data_accesses              375543                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::tsunami.ide          175                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
system.iocache.demand_misses::tsunami.ide          175                       # number of demand (read+write) misses
system.iocache.demand_misses::total               175                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide          175                       # number of overall misses
system.iocache.overall_misses::total              175                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21364383                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21364383                       # number of ReadReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide     21364383                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     21364383                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide     21364383                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     21364383                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          175                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide          175                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             175                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide          175                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            175                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122082.188571                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122082.188571                       # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 122082.188571                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 122082.188571                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 122082.188571                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 122082.188571                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                      41552                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_misses::tsunami.ide          175                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          175                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide          175                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          175                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide          175                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          175                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12263383                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12263383                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   2507056568                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2507056568                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide     12263383                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     12263383                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide     12263383                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     12263383                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70076.474286                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70076.474286                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60335.400655                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60335.400655                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70076.474286                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70076.474286                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70076.474286                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70076.474286                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               13702956                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         11991857                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           276088                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             8588922                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                4683455                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            54.529020                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 677984                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             15448                       # Number of incorrect RAS predictions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     7950804                       # DTB read hits
system.cpu0.dtb.read_misses                     30543                       # DTB read misses
system.cpu0.dtb.read_acv                          546                       # DTB read access violations
system.cpu0.dtb.read_accesses                  683229                       # DTB read accesses
system.cpu0.dtb.write_hits                    5159026                       # DTB write hits
system.cpu0.dtb.write_misses                     6845                       # DTB write misses
system.cpu0.dtb.write_acv                         353                       # DTB write access violations
system.cpu0.dtb.write_accesses                 234573                       # DTB write accesses
system.cpu0.dtb.data_hits                    13109830                       # DTB hits
system.cpu0.dtb.data_misses                     37388                       # DTB misses
system.cpu0.dtb.data_acv                          899                       # DTB access violations
system.cpu0.dtb.data_accesses                  917802                       # DTB accesses
system.cpu0.itb.fetch_hits                    1312718                       # ITB hits
system.cpu0.itb.fetch_misses                    29261                       # ITB misses
system.cpu0.itb.fetch_acv                         629                       # ITB acv
system.cpu0.itb.fetch_accesses                1341979                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                        99665250                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          22511576                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      60582407                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   13702956                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           5361439                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     70984108                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                 933480                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                       621                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               27412                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles      1463366                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       292819                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          216                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  7109889                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               200075                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples          95746858                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.632735                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.928110                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                84335489     88.08%     88.08% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  757900      0.79%     88.87% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1598110      1.67%     90.54% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  658612      0.69%     91.23% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2290747      2.39%     93.62% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  510807      0.53%     94.16% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  540667      0.56%     94.72% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  744782      0.78%     95.50% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4309744      4.50%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            95746858                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.137490                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.607859                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                18154184                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             68366814                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  7221268                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1568077                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                436514                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              432928                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                30567                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              53177978                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts                98719                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                436514                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                18925396                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               44877173                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      16564638                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  7942906                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              7000229                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              51314401                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents               200370                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               1702156                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                121650                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               3596195                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           34369689                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             62476617                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        62360377                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           107565                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             30276917                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 4092764                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1298231                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        191875                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 11393500                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             8037568                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5366781                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1135735                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores          800748                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  45795204                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1644687                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 45103865                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            41971                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        5328763                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      2477826                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1134880                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     95746858                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.471074                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.201865                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           76985468     80.41%     80.41% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            8252195      8.62%     89.02% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3430688      3.58%     92.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2350675      2.46%     95.06% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2374207      2.48%     97.54% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1175968      1.23%     98.77% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             779493      0.81%     99.58% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             300669      0.31%     99.90% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              97495      0.10%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       95746858                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                 143906     17.61%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     17.61% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                398143     48.73%     66.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               274956     33.65%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             3780      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             30829458     68.35%     68.36% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               46395      0.10%     68.46% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.46% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              26948      0.06%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.53% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             8252345     18.30%     86.82% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5217820     11.57%     98.39% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            725236      1.61%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              45103865                       # Type of FU issued
system.cpu0.iq.rate                          0.452554                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     817005                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.018114                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         186342910                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         52562719                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     43916640                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             470653                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            221373                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       216432                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              45663938                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 253152                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          522094                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads       946690                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         4799                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        15752                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       387148                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        13610                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       357638                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                436514                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               41413967                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              1424350                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           50298451                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           103444                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              8037568                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             5366781                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1456887                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 31578                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              1238658                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         15752                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        134081                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       309122                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              443203                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             44677716                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              8001376                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           426148                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      2858560                       # number of nop insts executed
system.cpu0.iew.exec_refs                    13178604                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 7039370                       # Number of branches executed
system.cpu0.iew.exec_stores                   5177228                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.448278                       # Inst execution rate
system.cpu0.iew.wb_sent                      44227196                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     44133072                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 22691402                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 31140086                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.442813                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.728688                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        5846321                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         509807                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           407712                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     94708833                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.468364                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.405169                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     79035549     83.45%     83.45% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      6314508      6.67%     90.12% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      3292930      3.48%     93.60% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      1802282      1.90%     95.50% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1366338      1.44%     96.94% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       489382      0.52%     97.46% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       366889      0.39%     97.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       390234      0.41%     98.26% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1650721      1.74%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     94708833                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            44358216                       # Number of instructions committed
system.cpu0.commit.committedOps              44358216                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      12070511                       # Number of memory references committed
system.cpu0.commit.loads                      7090878                       # Number of loads committed
system.cpu0.commit.membars                     170277                       # Number of memory barriers committed
system.cpu0.commit.branches                   6663650                       # Number of branches committed
system.cpu0.commit.fp_insts                    213529                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 41141903                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              549728                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass      2498518      5.63%      5.63% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        28814427     64.96%     70.59% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          45393      0.10%     70.69% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     70.69% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd         26477      0.06%     70.75% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     70.75% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     70.75% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     70.75% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv          1883      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.76% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead        7261155     16.37%     87.13% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite       4985127     11.24%     98.37% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess       725236      1.63%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         44358216                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1650721                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   143064224                       # The number of ROB reads
system.cpu0.rob.rob_writes                  101447849                       # The number of ROB writes
system.cpu0.timesIdled                         414726                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        3918392                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3706577488                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   41863465                       # Number of Instructions Simulated
system.cpu0.committedOps                     41863465                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              2.380721                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.380721                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.420041                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.420041                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                58777310                       # number of integer regfile reads
system.cpu0.int_regfile_writes               31962259                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   106639                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  106808                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1588469                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                729535                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.toL2Bus.throughput                   115690704                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2250904                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2250609                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             12351                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            12351                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           841911                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        41559                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            5326                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq          1552                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           6878                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           312265                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          312265                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError          280                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1525692                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2740000                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       708608                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      1000724                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               5975024                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     48817472                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    104660497                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     22674112                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     39558737                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          215710818                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             215700578                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus         4473152                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         5085967365                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.3                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           720000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        3437989936                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4906988127                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy        1597018302                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy        1654443775                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.1                       # Layer utilization (%)
system.iobus.throughput                       1434388                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq                 7370                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7370                       # Transaction distribution
system.iobus.trans_dist::WriteReq               53903                       # Transaction distribution
system.iobus.trans_dist::WriteResp              53903                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        10492                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          476                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        39092                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83454                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83454                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  122546                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        41968                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1904                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total        68194                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661624                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661624                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              2729818                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 2729818                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              9847000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               356000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13505000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             2450000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           374411689                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            26741000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            42019262                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.cpu0.icache.tags.replacements           762211                       # number of replacements
system.cpu0.icache.tags.tagsinuse          508.848890                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs            6309809                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           762721                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs             8.272762                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      26485928250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.848890                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.993845                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.993845                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1           13                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          418                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses          7872808                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses         7872808                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst      6309809                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        6309809                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      6309809                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         6309809                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      6309809                       # number of overall hits
system.cpu0.icache.overall_hits::total        6309809                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       800080                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       800080                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       800080                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        800080                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       800080                       # number of overall misses
system.cpu0.icache.overall_misses::total       800080                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11341096711                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  11341096711                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  11341096711                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  11341096711                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  11341096711                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  11341096711                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      7109889                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      7109889                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      7109889                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      7109889                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      7109889                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      7109889                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.112531                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.112531                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.112531                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.112531                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.112531                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.112531                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14174.953393                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14174.953393                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14174.953393                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14174.953393                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14174.953393                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14174.953393                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         3387                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              162                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    20.907407                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        37161                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        37161                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        37161                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        37161                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        37161                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        37161                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       762919                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       762919                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       762919                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       762919                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       762919                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       762919                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9350852559                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   9350852559                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9350852559                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   9350852559                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9350852559                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   9350852559                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.107304                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.107304                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.107304                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.107304                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.107304                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.107304                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12256.678047                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12256.678047                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12256.678047                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12256.678047                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12256.678047                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12256.678047                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements          1069035                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          482.779727                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs            9141371                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1069547                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs             8.546956                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         25151000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   482.779727                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.942929                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.942929                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          229                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          233                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         49546788                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        49546788                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      5665393                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5665393                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3152024                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3152024                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       147109                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       147109                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       170256                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       170256                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      8817417                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         8817417                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      8817417                       # number of overall hits
system.cpu0.dcache.overall_hits::total        8817417                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1322171                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1322171                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1644281                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1644281                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        16610                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        16610                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data          766                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total          766                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2966452                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2966452                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2966452                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2966452                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  36169344894                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  36169344894                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  74324803897                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  74324803897                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    267182493                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    267182493                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      4788059                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      4788059                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 110494148791                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 110494148791                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 110494148791                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 110494148791                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6987564                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6987564                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4796305                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4796305                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       163719                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       163719                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       171022                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       171022                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     11783869                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     11783869                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     11783869                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     11783869                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.189218                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.189218                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.342822                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.342822                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.101454                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.101454                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.004479                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.004479                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.251738                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.251738                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.251738                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.251738                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27356.026485                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 27356.026485                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45202.008596                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 45202.008596                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16085.640759                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16085.640759                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6250.729765                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6250.729765                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37247.913936                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 37247.913936                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37247.913936                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 37247.913936                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      3702426                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         3454                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           160595                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets             88                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.054429                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    39.250000                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       568073                       # number of writebacks
system.cpu0.dcache.writebacks::total           568073                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       499697                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       499697                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1402831                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1402831                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4326                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4326                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1902528                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1902528                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1902528                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1902528                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       822474                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       822474                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       241450                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       241450                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        12284                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        12284                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          766                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total          766                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1063924                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1063924                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1063924                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1063924                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  24909734008                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  24909734008                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10782476086                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10782476086                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    145144507                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    145144507                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      3254941                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      3254941                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  35692210094                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  35692210094                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  35692210094                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  35692210094                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    992378000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    992378000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1672126998                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1672126998                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2664504998                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2664504998                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.117705                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.117705                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.050341                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.050341                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.075031                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.075031                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.004479                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.004479                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.090286                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.090286                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.090286                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.090286                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30286.348271                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30286.348271                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44657.179896                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44657.179896                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.736486                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.736486                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4249.270235                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4249.270235                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33547.706503                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33547.706503                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33547.706503                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33547.706503                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                5770916                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          5004196                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           122577                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             3556553                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                1526133                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            42.910453                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 301064                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect              7748                       # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     3015540                       # DTB read hits
system.cpu1.dtb.read_misses                     12269                       # DTB read misses
system.cpu1.dtb.read_acv                            5                       # DTB read access violations
system.cpu1.dtb.read_accesses                  293761                       # DTB read accesses
system.cpu1.dtb.write_hits                    1836726                       # DTB write hits
system.cpu1.dtb.write_misses                     2353                       # DTB write misses
system.cpu1.dtb.write_acv                          39                       # DTB write access violations
system.cpu1.dtb.write_accesses                 109652                       # DTB write accesses
system.cpu1.dtb.data_hits                     4852266                       # DTB hits
system.cpu1.dtb.data_misses                     14622                       # DTB misses
system.cpu1.dtb.data_acv                           44                       # DTB access violations
system.cpu1.dtb.data_accesses                  403413                       # DTB accesses
system.cpu1.itb.fetch_hits                     632341                       # ITB hits
system.cpu1.itb.fetch_misses                     5352                       # ITB misses
system.cpu1.itb.fetch_acv                          51                       # ITB acv
system.cpu1.itb.fetch_accesses                 637693                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                        26335588                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles           9800268                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      22981944                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    5770916                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           1827197                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     14019681                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 419510                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                       307                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles               23776                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles       208449                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       196331                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles           53                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  2522136                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                89875                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples          24458620                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.939626                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.331670                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                20375648     83.31%     83.31% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  230665      0.94%     84.25% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  464859      1.90%     86.15% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  295118      1.21%     87.36% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  600413      2.45%     89.81% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  204861      0.84%     90.65% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  257669      1.05%     91.70% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  270860      1.11%     92.81% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 1758527      7.19%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            24458620                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.219130                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.872657                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 8213195                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             12716086                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  2925937                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               406668                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                196733                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              189397                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                13167                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              19294426                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                40930                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                196733                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 8443455                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                3954170                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       7253500                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  3074788                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              1535972                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              18421784                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 5378                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                385976                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                 36959                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents                551165                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           12165906                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups             21959681                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        21890085                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            63650                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             10221482                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 1944424                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            582778                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         59316                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  3316426                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             3128488                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            1940399                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           395849                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          259099                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  16224994                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             722304                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 15758531                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            26415                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        2553169                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined      1203962                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        524576                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     24458620                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.644294                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.366216                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           17964380     73.45%     73.45% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            2773024     11.34%     84.79% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            1191873      4.87%     89.66% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             895755      3.66%     93.32% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             840464      3.44%     96.76% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             400907      1.64%     98.40% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             238226      0.97%     99.37% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             113179      0.46%     99.83% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              40812      0.17%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       24458620                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  56470     15.54%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     15.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                184321     50.72%     66.26% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               122598     33.74%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             3518      0.02%      0.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             10371294     65.81%     65.84% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               24284      0.15%     65.99% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     65.99% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd              11773      0.07%     66.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     66.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     66.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     66.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1759      0.01%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.08% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             3139820     19.92%     86.00% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            1865147     11.84%     97.84% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            340936      2.16%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              15758531                       # Type of FU issued
system.cpu1.iq.rate                          0.598374                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     363389                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.023060                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          56111313                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         19387392                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     15262127                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads             254173                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            119441                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       117263                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              15982004                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 136398                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          157695                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       453605                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         1302                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         6552                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       197079                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads         5589                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        74646                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                196733                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                3102898                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               407577                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           17959821                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts            47400                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              3128488                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             1940399                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            647154                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 24325                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents               312873                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          6552                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         58721                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       143362                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              202083                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             15559963                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              3035862                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           198568                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                      1012523                       # number of nop insts executed
system.cpu1.iew.exec_refs                     4881099                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 2446532                       # Number of branches executed
system.cpu1.iew.exec_stores                   1845237                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.590834                       # Inst execution rate
system.cpu1.iew.wb_sent                      15420680                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     15379390                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  7566791                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 10761562                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.583977                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.703131                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        2776166                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         197728                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           185190                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     23976589                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.630910                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.597118                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     18550941     77.37%     77.37% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      2272481      9.48%     86.85% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      1151381      4.80%     91.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       578443      2.41%     94.06% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       385291      1.61%     95.67% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       189866      0.79%     96.46% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       157998      0.66%     97.12% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       143488      0.60%     97.72% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       546700      2.28%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     23976589                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            15127070                       # Number of instructions committed
system.cpu1.commit.committedOps              15127070                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       4418203                       # Number of memory references committed
system.cpu1.commit.loads                      2674883                       # Number of loads committed
system.cpu1.commit.membars                      66521                       # Number of memory barriers committed
system.cpu1.commit.branches                   2263870                       # Number of branches committed
system.cpu1.commit.fp_insts                    115331                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 13957396                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              240978                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass       845832      5.59%      5.59% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu         9417463     62.26%     67.85% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          23911      0.16%     68.01% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     68.01% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd         11769      0.08%     68.08% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     68.08% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     68.08% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     68.08% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv          1759      0.01%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     68.09% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead        2741404     18.12%     86.22% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite       1743996     11.53%     97.75% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess       340936      2.25%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         15127070                       # Class of committed instruction
system.cpu1.commit.bw_lim_events               546700                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                    41251186                       # The number of ROB reads
system.cpu1.rob.rob_writes                   36287802                       # The number of ROB writes
system.cpu1.timesIdled                         194891                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        1876968                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3779240330                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   14284756                       # Number of Instructions Simulated
system.cpu1.committedOps                     14284756                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.843615                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.843615                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.542413                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.542413                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                20099122                       # number of integer regfile reads
system.cpu1.int_regfile_writes               11015819                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    63024                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   62672                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                1065455                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                283847                       # number of misc regfile writes
system.cpu1.icache.tags.replacements           353746                       # number of replacements
system.cpu1.icache.tags.tagsinuse          504.553851                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            2153244                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           354258                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs             6.078180                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      47615844250                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   504.553851                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.985457                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.985457                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          508                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses          2876460                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses         2876460                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      2153244                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        2153244                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      2153244                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         2153244                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      2153244                       # number of overall hits
system.cpu1.icache.overall_hits::total        2153244                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       368891                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       368891                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       368891                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        368891                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       368891                       # number of overall misses
system.cpu1.icache.overall_misses::total       368891                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5137931940                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   5137931940                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   5137931940                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   5137931940                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   5137931940                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   5137931940                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      2522135                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      2522135                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      2522135                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      2522135                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      2522135                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      2522135                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.146261                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.146261                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.146261                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.146261                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.146261                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.146261                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13928.049044                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13928.049044                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13928.049044                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13928.049044                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13928.049044                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13928.049044                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs         1327                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               55                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    24.127273                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        14566                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        14566                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        14566                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        14566                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        14566                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        14566                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       354325                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       354325                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       354325                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       354325                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       354325                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       354325                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4259071697                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   4259071697                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4259071697                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   4259071697                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4259071697                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   4259071697                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.140486                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.140486                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.140486                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.140486                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.140486                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.140486                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12020.240449                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12020.240449                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12020.240449                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12020.240449                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12020.240449                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12020.240449                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           360788                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          496.086183                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            3613456                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           361109                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            10.006552                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      40126349500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   496.086183                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.968918                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.968918                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          321                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          321                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.626953                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         18510307                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        18510307                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      2220866                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        2220866                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      1307515                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       1307515                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        45364                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        45364                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        48883                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        48883                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      3528381                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         3528381                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      3528381                       # number of overall hits
system.cpu1.dcache.overall_hits::total        3528381                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       524895                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       524895                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       378889                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       378889                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8897                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         8897                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data          786                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total          786                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       903784                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        903784                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       903784                       # number of overall misses
system.cpu1.dcache.overall_misses::total       903784                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   8191623763                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   8191623763                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  14087810149                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  14087810149                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    135761491                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    135761491                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      5726098                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total      5726098                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  22279433912                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  22279433912                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  22279433912                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  22279433912                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      2745761                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      2745761                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      1686404                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1686404                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        54261                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        54261                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        49669                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        49669                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      4432165                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      4432165                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      4432165                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      4432165                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.191166                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.191166                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.224673                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.224673                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.163967                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.163967                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.015825                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.015825                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.203915                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.203915                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.203915                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.203915                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15606.214125                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.214125                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37181.892715                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 37181.892715                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15259.243678                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15259.243678                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7285.111959                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7285.111959                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24651.281625                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 24651.281625                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24651.281625                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 24651.281625                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs       560522                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets          381                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs            27149                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets             19                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    20.646138                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    20.052632                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       273838                       # number of writebacks
system.cpu1.dcache.writebacks::total           273838                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       229504                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       229504                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       313811                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       313811                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1705                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1705                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       543315                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       543315                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       543315                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       543315                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       295391                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       295391                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        65078                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        65078                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         7192                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         7192                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          786                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total          786                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       360469                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       360469                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       360469                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       360469                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   3818838154                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   3818838154                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2138006676                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2138006676                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     81043507                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     81043507                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      4153902                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      4153902                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   5956844830                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   5956844830                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5956844830                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   5956844830                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    490391500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    490391500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    941927000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    941927000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1432318500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1432318500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.107581                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.107581                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.038590                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.038590                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.132545                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.132545                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.015825                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.015825                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.081330                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.081330                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.081330                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.081330                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12928.078899                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12928.078899                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32852.986816                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32852.986816                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11268.563265                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11268.563265                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5284.862595                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5284.862595                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16525.262450                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16525.262450                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16525.262450                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16525.262450                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    4820                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    161850                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   55184     39.67%     39.67% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.09%     39.77% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1924      1.38%     41.15% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                     16      0.01%     41.16% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  81844     58.84%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              139099                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    54289     49.07%     49.07% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.12%     49.19% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1924      1.74%     50.93% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                      16      0.01%     50.94% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   54273     49.06%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               110633                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1865924468000     98.05%     98.05% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               60967000      0.00%     98.05% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              531593000      0.03%     98.08% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30                8367000      0.00%     98.08% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            36597541500      1.92%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1903122936500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.983782                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.663127                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.795354                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.56%      3.56% # number of syscalls executed
system.cpu0.kern.syscall::3                        19      8.44%     12.00% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.78%     13.78% # number of syscalls executed
system.cpu0.kern.syscall::6                        33     14.67%     28.44% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.44%     28.89% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      4.00%     32.89% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.44%     37.33% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.67%     40.00% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.44%     40.44% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.33%     41.78% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.11%     44.89% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.89%     45.78% # number of syscalls executed
system.cpu0.kern.syscall::45                       36     16.00%     61.78% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.33%     63.11% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.44%     67.56% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.44%     72.00% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.44%     72.44% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.67%     75.11% # number of syscalls executed
system.cpu0.kern.syscall::71                       25     11.11%     86.22% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.33%     87.56% # number of syscalls executed
system.cpu0.kern.syscall::74                        6      2.67%     90.22% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.44%     90.67% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.33%     92.00% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      4.00%     96.00% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.89%     96.89% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.89%     97.78% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.44%     98.22% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.89%     99.11% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.89%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   225                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  105      0.07%      0.07% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.07% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.07% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.07% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 2905      1.98%      2.05% # number of callpals executed
system.cpu0.kern.callpal::tbi                      50      0.03%      2.09% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.09% # number of callpals executed
system.cpu0.kern.callpal::swpipl               132721     90.43%     92.52% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6135      4.18%     96.70% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.70% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     96.70% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.01%     96.71% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.71% # number of callpals executed
system.cpu0.kern.callpal::rti                    4306      2.93%     99.65% # number of callpals executed
system.cpu0.kern.callpal::callsys                 382      0.26%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     138      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                146768                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             6331                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1342                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1341                      
system.cpu0.kern.mode_good::user                 1342                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.211815                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.349668                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1901148119000     99.90%     99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          1974809500      0.10%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    2906                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    3853                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     75635                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   26441     39.26%     39.26% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1922      2.85%     42.12% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    105      0.16%     42.27% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  38878     57.73%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               67346                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    25959     48.22%     48.22% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1922      3.57%     51.78% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     105      0.20%     51.98% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   25854     48.02%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                53840                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1868834322000     98.22%     98.22% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              532397000      0.03%     98.24% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30               48831000      0.00%     98.25% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            33374320500      1.75%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1902789870500                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.981771                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.665003                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.799454                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        11     10.89%     10.89% # number of syscalls executed
system.cpu1.kern.syscall::6                         9      8.91%     19.80% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.99%     20.79% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      5.94%     26.73% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.97%     29.70% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.97%     32.67% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      3.96%     36.63% # number of syscalls executed
system.cpu1.kern.syscall::45                       18     17.82%     54.46% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.97%     57.43% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      0.99%     58.42% # number of syscalls executed
system.cpu1.kern.syscall::71                       29     28.71%     87.13% # number of syscalls executed
system.cpu1.kern.syscall::74                       10      9.90%     97.03% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.97%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   101                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                   16      0.02%      0.02% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 1334      1.92%      1.95% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.00%      1.95% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      1.96% # number of callpals executed
system.cpu1.kern.callpal::swpipl                62422     89.83%     91.80% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2621      3.77%     95.57% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     95.57% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     95.57% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.00%     95.58% # number of callpals executed
system.cpu1.kern.callpal::rti                    2896      4.17%     99.75% # number of callpals executed
system.cpu1.kern.callpal::callsys                 133      0.19%     99.94% # number of callpals executed
system.cpu1.kern.callpal::imb                      42      0.06%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 69486                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             1712                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                395                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2056                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                462                      
system.cpu1.kern.mode_good::user                  395                      
system.cpu1.kern.mode_good::idle                   67                      
system.cpu1.kern.mode_switch_good::kernel     0.269860                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.032588                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.221955                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel       38841912000      2.04%      2.04% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           712477500      0.04%      2.08% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1862932175500     97.92%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    1335                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------