path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.922762                       # Number of seconds simulated
sim_ticks                                1922761887500                       # Number of ticks simulated
final_tick                               1922761887500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 132982                       # Simulator instruction rate (inst/s)
host_op_rate                                   132982                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4507220686                       # Simulator tick rate (ticks/s)
host_mem_usage                                 384024                       # Number of bytes of host memory used
host_seconds                                   426.60                       # Real time elapsed on the host
sim_insts                                    56729467                       # Number of instructions simulated
sim_ops                                      56729467                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst           869760                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24778624                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           103040                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           515712                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             26268096                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       869760                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       103040                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          972800                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7882944                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7882944                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             13590                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            387166                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1610                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              8058                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                410439                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          123171                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               123171                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              452349                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12886996                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               53590                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              268214                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               499                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13661648                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         452349                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          53590                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             505939                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4099803                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4099803                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4099803                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             452349                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12886996                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              53590                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             268214                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide              499                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               17761450                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        410439                       # Number of read requests accepted
system.physmem.writeReqs                       123171                       # Number of write requests accepted
system.physmem.readBursts                      410439                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     123171                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 26260800                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7296                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7881088                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  26268096                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7882944                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      114                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         309493                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               25497                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25956                       # Per bank write bursts
system.physmem.perBankRdBursts::2               26004                       # Per bank write bursts
system.physmem.perBankRdBursts::3               25724                       # Per bank write bursts
system.physmem.perBankRdBursts::4               25504                       # Per bank write bursts
system.physmem.perBankRdBursts::5               25939                       # Per bank write bursts
system.physmem.perBankRdBursts::6               25634                       # Per bank write bursts
system.physmem.perBankRdBursts::7               25247                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25446                       # Per bank write bursts
system.physmem.perBankRdBursts::9               25836                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25660                       # Per bank write bursts
system.physmem.perBankRdBursts::11              25037                       # Per bank write bursts
system.physmem.perBankRdBursts::12              26054                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25864                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25329                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25594                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8072                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8040                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8032                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7672                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7388                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7843                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7702                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7083                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7329                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7600                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7538                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7420                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7961                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8153                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7615                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7694                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          14                       # Number of times write queue was full causing retry
system.physmem.totGap                    1922757529500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  410439                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 123171                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    317968                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     37909                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     29466                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     24871                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        87                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1967                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3612                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4413                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5831                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6890                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6805                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8579                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9709                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8954                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8272                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8747                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6829                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6926                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6098                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      325                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      196                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      230                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       45                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65327                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      522.630582                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     319.337054                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     410.684018                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          14917     22.83%     22.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        11339     17.36%     40.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5448      8.34%     48.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2879      4.41%     52.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2603      3.98%     56.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1650      2.53%     59.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         3828      5.86%     65.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1203      1.84%     67.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        21460     32.85%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65327                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5559                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        73.810757                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2831.423020                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           5556     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5559                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5559                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.151826                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.921629                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       20.873132                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            4760     85.63%     85.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             185      3.33%     88.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              26      0.47%     89.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             178      3.20%     92.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35               6      0.11%     92.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              17      0.31%     93.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              45      0.81%     93.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               4      0.07%     93.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              15      0.27%     94.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              20      0.36%     94.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               1      0.02%     94.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               5      0.09%     94.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67               9      0.16%     94.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               5      0.09%     94.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              23      0.41%     95.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              22      0.40%     95.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87              34      0.61%     96.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.02%     96.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103           160      2.88%     99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.04%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             3      0.05%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.02%     99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.02%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.02%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             2      0.04%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.04%     99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             3      0.05%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             3      0.05%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             3      0.05%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             3      0.05%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             2      0.04%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.02%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183            11      0.20%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             2      0.04%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::220-223             1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::252-255             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5559                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4492977750                       # Total ticks spent queuing
system.physmem.totMemAccLat               12186571500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2051625000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10949.80                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29699.80                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.66                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           4.10                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.66                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        4.10                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         2.26                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.48                       # Average write queue length when enqueuing
system.physmem.readRowHits                     369433                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     98707                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.03                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.14                       # Row buffer hit rate for writes
system.physmem.avgGap                      3603301.16                       # Average gap between requests
system.physmem.pageHitRate                      87.75                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  247242240                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  134904000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1602939000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                400671360                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           125585332080                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            63449600445                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1097998572000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1289419261125                       # Total energy per rank (pJ)
system.physmem_0.averagePower              670.608464                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   1826410636250                       # Time in different power states
system.physmem_0.memoryStateTime::REF     64205180000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     32144391250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  246629880                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  134569875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1597596000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                397288800                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           125585332080                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            62800369875                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1098568064250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1289329850760                       # Total energy per rank (pJ)
system.physmem_1.averagePower              670.561968                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   1827364141250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     64205180000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     31190872500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu0.branchPred.lookups               16164803                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         14134057                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           313974                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            10204663                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                5324382                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            52.175971                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 806868                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             17359                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     9175640                       # DTB read hits
system.cpu0.dtb.read_misses                     32141                       # DTB read misses
system.cpu0.dtb.read_acv                          535                       # DTB read access violations
system.cpu0.dtb.read_accesses                  683139                       # DTB read accesses
system.cpu0.dtb.write_hits                    5880520                       # DTB write hits
system.cpu0.dtb.write_misses                     7287                       # DTB write misses
system.cpu0.dtb.write_acv                         388                       # DTB write access violations
system.cpu0.dtb.write_accesses                 235457                       # DTB write accesses
system.cpu0.dtb.data_hits                    15056160                       # DTB hits
system.cpu0.dtb.data_misses                     39428                       # DTB misses
system.cpu0.dtb.data_acv                          923                       # DTB access violations
system.cpu0.dtb.data_accesses                  918596                       # DTB accesses
system.cpu0.itb.fetch_hits                    1432352                       # ITB hits
system.cpu0.itb.fetch_misses                    20066                       # ITB misses
system.cpu0.itb.fetch_acv                         603                       # ITB acv
system.cpu0.itb.fetch_accesses                1452418                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       147492353                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          26474453                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      70295181                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   16164803                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           6131250                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    112661982                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1056864                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                       660                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               29689                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       929577                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       461648                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          350                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  8123308                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               229144                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples         141086791                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.498241                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.734215                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               127943316     90.68%     90.68% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  834789      0.59%     91.28% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1813592      1.29%     92.56% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  779670      0.55%     93.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2595829      1.84%     94.95% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  572321      0.41%     95.36% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  651682      0.46%     95.82% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  825551      0.59%     96.41% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 5070041      3.59%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           141086791                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.109598                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.476602                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                21397284                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            108971969                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  8457985                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1766417                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                493135                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              516601                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                35757                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              61523411                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               108836                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                493135                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                22231623                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               77943277                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      19950150                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  9304003                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             11164601                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              59421423                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents               199471                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               2023547                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                224739                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               7186522                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           39708138                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             72284773                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        72145342                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           129802                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             34979364                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 4728766                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1463848                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        211077                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 12544775                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             9257817                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6153108                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1360057                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1005705                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  53010072                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1876155                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 52220775                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            51551                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6501427                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      2875305                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1291728                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    141086791                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.370132                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.087511                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          119618317     84.78%     84.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            9300566      6.59%     91.38% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3865351      2.74%     94.12% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2730572      1.94%     96.05% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2821391      2.00%     98.05% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1375833      0.98%     99.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             902269      0.64%     99.67% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             360488      0.26%     99.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             112004      0.08%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      141086791                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                 182068     18.38%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     2      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                471621     47.60%     65.98% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               337015     34.02%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             3780      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             35835166     68.62%     68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               56519      0.11%     68.74% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.74% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              28571      0.05%     68.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9523186     18.24%     87.03% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5952100     11.40%     98.43% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            819570      1.57%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              52220775                       # Type of FU issued
system.cpu0.iq.rate                          0.354058                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     990706                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.018971                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         245999962                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         61137242                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     50831283                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             570635                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            267757                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       262095                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              52900144                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 307557                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          581308                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1065241                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         3900                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        17685                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       500436                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        18736                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       408208                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                493135                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               74418027                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              1058724                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           58259516                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           116557                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              9257817                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6153108                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1657861                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 39988                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents               817674                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         17685                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        153306                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       351909                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              505215                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             51717296                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9230924                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           503478                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      3373289                       # number of nop insts executed
system.cpu0.iew.exec_refs                    15132335                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 8216790                       # Number of branches executed
system.cpu0.iew.exec_stores                   5901411                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.350644                       # Inst execution rate
system.cpu0.iew.wb_sent                      51207379                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     51093378                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 26334207                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 36473944                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.346414                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.722001                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        6824839                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         584427                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           463110                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    139882457                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.366962                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.256012                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    121750983     87.04%     87.04% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      7187616      5.14%     92.18% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      3944064      2.82%     95.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2051217      1.47%     96.46% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1611428      1.15%     97.61% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       577022      0.41%     98.03% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       437359      0.31%     98.34% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       434985      0.31%     98.65% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1887783      1.35%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    139882457                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            51331530                       # Number of instructions committed
system.cpu0.commit.committedOps              51331530                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      13845248                       # Number of memory references committed
system.cpu0.commit.loads                      8192576                       # Number of loads committed
system.cpu0.commit.membars                     198790                       # Number of memory barriers committed
system.cpu0.commit.branches                   7761926                       # Number of branches committed
system.cpu0.commit.fp_insts                    259003                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 47542487                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              656882                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass      2950502      5.75%      5.75% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        33426097     65.12%     70.87% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          55327      0.11%     70.97% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     70.97% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd         28109      0.05%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv          1883      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.03% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead        8391366     16.35%     87.38% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite       5658677     11.02%     98.40% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess       819569      1.60%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         51331530                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1887783                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                   195950193                       # The number of ROB reads
system.cpu0.rob.rob_writes                  117511428                       # The number of ROB writes
system.cpu0.timesIdled                         525574                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        6405562                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3698031423                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   48384795                       # Number of Instructions Simulated
system.cpu0.committedOps                     48384795                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              3.048320                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        3.048320                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.328050                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.328050                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                67995096                       # number of integer regfile reads
system.cpu0.int_regfile_writes               36974255                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   128760                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  130249                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1711265                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                819270                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements          1282737                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          506.160384                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           10524244                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1283249                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs             8.201249                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         36569500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.160384                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988595                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.988595                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          218                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          245                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         56891628                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        56891628                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      6483780                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6483780                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3678701                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3678701                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       162607                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       162607                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       187520                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       187520                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10162481                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        10162481                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10162481                       # number of overall hits
system.cpu0.dcache.overall_hits::total       10162481                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1594725                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1594725                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1768883                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1768883                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21044                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21044                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2856                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         2856                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3363608                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3363608                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3363608                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3363608                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  54837998000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  54837998000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114303059042                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 114303059042                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    389087500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    389087500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     45510000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     45510000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 169141057042                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 169141057042                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 169141057042                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 169141057042                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      8078505                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8078505                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5447584                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5447584                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       183651                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       183651                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       190376                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       190376                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     13526089                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     13526089                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     13526089                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     13526089                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.197403                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.197403                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.324710                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.324710                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.114587                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.114587                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.015002                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.015002                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.248676                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.248676                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.248676                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.248676                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34387.118782                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 34387.118782                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64618.778654                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 64618.778654                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18489.236837                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18489.236837                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15934.873950                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15934.873950                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50285.603151                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 50285.603151                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50285.603151                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 50285.603151                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      6995611                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        14546                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           119540                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            103                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    58.521089                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   141.223301                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       756067                       # number of writebacks
system.cpu0.dcache.writebacks::total           756067                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       579442                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       579442                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1502906                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1502906                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         5209                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         5209                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      2082348                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      2082348                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      2082348                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      2082348                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1015283                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      1015283                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       265977                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       265977                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        15835                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        15835                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2856                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         2856                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1281260                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1281260                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1281260                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1281260                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7045                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7045                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10126                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10126                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17171                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17171                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43466083500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  43466083500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  18236016784                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  18236016784                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    187455000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    187455000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     42654000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     42654000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  61702100284                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  61702100284                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  61702100284                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  61702100284                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1563410000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1563410000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2299016000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2299016000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3862426000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3862426000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.125677                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.125677                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048825                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048825                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.086223                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.086223                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.015002                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.015002                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.094725                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.094725                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.094725                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.094725                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42811.790900                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42811.790900                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68562.382401                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68562.382401                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11838.017051                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11838.017051                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14934.873950                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14934.873950                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48157.360945                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48157.360945                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48157.360945                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48157.360945                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221917.672108                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221917.672108                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227040.884851                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227040.884851                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224938.908625                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224938.908625                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements           908501                       # number of replacements
system.cpu0.icache.tags.tagsinuse          508.069795                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs            7168696                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           909010                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs             7.886267                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      42372449500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.069795                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992324                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.992324                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          418                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses          9032627                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses         9032627                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst      7168696                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        7168696                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      7168696                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         7168696                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      7168696                       # number of overall hits
system.cpu0.icache.overall_hits::total        7168696                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       954611                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       954611                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       954611                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        954611                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       954611                       # number of overall misses
system.cpu0.icache.overall_misses::total       954611                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14636609987                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  14636609987                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  14636609987                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  14636609987                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  14636609987                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  14636609987                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      8123307                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      8123307                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      8123307                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      8123307                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      8123307                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      8123307                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.117515                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.117515                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.117515                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.117515                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.117515                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.117515                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15332.538581                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 15332.538581                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15332.538581                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 15332.538581                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15332.538581                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 15332.538581                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         8572                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              278                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    30.834532                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks       908501                       # number of writebacks
system.cpu0.icache.writebacks::total           908501                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        45291                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        45291                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        45291                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        45291                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        45291                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        45291                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       909320                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       909320                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       909320                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       909320                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       909320                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       909320                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12934939493                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  12934939493                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12934939493                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  12934939493                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12934939493                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  12934939493                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.111940                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.111940                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.111940                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.111940                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.111940                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.111940                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14224.848780                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14224.848780                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14224.848780                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 14224.848780                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14224.848780                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 14224.848780                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                3578846                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          3133511                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect            63586                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             2063930                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                 845641                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            40.972368                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 169933                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect              4992                       # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1885255                       # DTB read hits
system.cpu1.dtb.read_misses                      9531                       # DTB read misses
system.cpu1.dtb.read_acv                            5                       # DTB read access violations
system.cpu1.dtb.read_accesses                  285831                       # DTB read accesses
system.cpu1.dtb.write_hits                    1175917                       # DTB write hits
system.cpu1.dtb.write_misses                     2028                       # DTB write misses
system.cpu1.dtb.write_acv                          35                       # DTB write access violations
system.cpu1.dtb.write_accesses                 108552                       # DTB write accesses
system.cpu1.dtb.data_hits                     3061172                       # DTB hits
system.cpu1.dtb.data_misses                     11559                       # DTB misses
system.cpu1.dtb.data_acv                           40                       # DTB access violations
system.cpu1.dtb.data_accesses                  394383                       # DTB accesses
system.cpu1.itb.fetch_hits                     516958                       # ITB hits
system.cpu1.itb.fetch_misses                     4674                       # ITB misses
system.cpu1.itb.fetch_acv                          66                       # ITB acv
system.cpu1.itb.fetch_accesses                 521632                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                        15151136                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles           6180932                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      13745317                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    3578846                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           1015574                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      7699604                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 257606                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                        14                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles               25107                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles       173727                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        62622                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles           18                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  1537985                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                51060                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples          14270827                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.963176                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.372632                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                11867377     83.16%     83.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  153441      1.08%     84.23% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  242213      1.70%     85.93% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  178756      1.25%     87.18% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  307848      2.16%     89.34% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  121777      0.85%     90.19% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  138851      0.97%     91.17% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  186713      1.31%     92.48% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 1073851      7.52%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            14270827                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.236210                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.907214                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 5071818                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles              7138589                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  1741534                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               196274                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                122611                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              106199                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                 6268                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              11163667                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                19967                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                122611                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 5211151                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                 520290                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       5613443                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  1798962                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              1004368                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              10604371                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 4257                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 67823                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                 18974                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents                511038                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands            6965041                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups             12634725                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        12576141                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            52884                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps              5956129                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 1008912                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            437815                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         40748                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  1803693                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             1932664                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            1246799                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           224198                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          128085                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                   9340268                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             503829                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                  9138713                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            20420                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        1499424                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined       677663                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        370337                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     14270827                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.640377                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.363961                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           10455091     73.26%     73.26% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            1683189     11.79%     85.06% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2             712225      4.99%     90.05% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             493511      3.46%     93.51% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             444759      3.12%     96.62% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             238311      1.67%     98.29% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             152079      1.07%     99.36% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7              65820      0.46%     99.82% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              25842      0.18%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       14270827                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  22910      9.24%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                135436     54.62%     63.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                89607     36.14%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             3518      0.04%      0.04% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              5683316     62.19%     62.23% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               16216      0.18%     62.41% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.41% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd              10845      0.12%     62.52% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.52% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.52% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.52% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1759      0.02%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.54% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             1965659     21.51%     84.05% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            1197875     13.11%     97.16% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            259525      2.84%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total               9138713                       # Type of FU issued
system.cpu1.iq.rate                          0.603170                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     247953                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.027132                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          32611679                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         11249940                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses      8808383                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads             204947                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes             97488                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses        94992                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses               9273516                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 109632                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           94173                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       262201                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          474                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         4003                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       124065                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads          413                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        65383                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                122611                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 306675                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               177978                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           10362316                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts            27137                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              1932664                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             1246799                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            457137                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                  4115                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents               173001                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          4003                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         29001                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect        94231                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              123232                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts              9024161                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              1901420                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           114552                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       518219                       # number of nop insts executed
system.cpu1.iew.exec_refs                     3085060                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 1341299                       # Number of branches executed
system.cpu1.iew.exec_stores                   1183640                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.595610                       # Inst execution rate
system.cpu1.iew.wb_sent                       8932335                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                      8903375                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  4245423                       # num instructions producing a value
system.cpu1.iew.wb_consumers                  6036438                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.587637                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.703299                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        1526496                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         133492                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           112683                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     13989586                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.626917                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.604217                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     10816267     77.32%     77.32% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      1467149     10.49%     87.80% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2       531154      3.80%     91.60% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       320114      2.29%     93.89% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       241905      1.73%     95.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       101551      0.73%     96.34% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6        91287      0.65%     97.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       103861      0.74%     97.74% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       316298      2.26%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     13989586                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts             8770307                       # Number of instructions committed
system.cpu1.commit.committedOps               8770307                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       2793197                       # Number of memory references committed
system.cpu1.commit.loads                      1670463                       # Number of loads committed
system.cpu1.commit.membars                      42427                       # Number of memory barriers committed
system.cpu1.commit.branches                   1252873                       # Number of branches committed
system.cpu1.commit.fp_insts                     93374                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                  8120952                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              139980                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass       429153      4.89%      4.89% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu         5216835     59.48%     64.38% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          16050      0.18%     64.56% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.56% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd         10839      0.12%     64.68% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.68% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.68% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.68% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv          1759      0.02%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.70% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead        1712890     19.53%     84.23% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite       1123256     12.81%     97.04% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess       259525      2.96%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total          8770307                       # Class of committed instruction
system.cpu1.commit.bw_lim_events               316298                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                    23885701                       # The number of ROB reads
system.cpu1.rob.rob_writes                   20870962                       # The number of ROB writes
system.cpu1.timesIdled                         125875                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                         880309                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3829642661                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                    8344672                       # Number of Instructions Simulated
system.cpu1.committedOps                      8344672                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.815666                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.815666                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.550762                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.550762                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                11618114                       # number of integer regfile reads
system.cpu1.int_regfile_writes                6343189                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    52190                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   51516                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 503472                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                210349                       # number of misc regfile writes
system.cpu1.dcache.tags.replacements            98962                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          486.970751                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            2466427                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs            99271                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            24.845393                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     1048837181500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   486.970751                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.951115                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.951115                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          309                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          309                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.603516                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         11541624                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        11541624                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      1517477                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1517477                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data       889696                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        889696                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        32286                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        32286                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        29965                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        29965                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      2407173                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         2407173                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      2407173                       # number of overall hits
system.cpu1.dcache.overall_hits::total        2407173                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       186675                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       186675                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       194181                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       194181                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         4996                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         4996                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data         2988                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         2988                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       380856                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        380856                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       380856                       # number of overall misses
system.cpu1.dcache.overall_misses::total       380856                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2524860000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2524860000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   9140210329                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   9140210329                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     47601500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     47601500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     47681500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     47681500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  11665070329                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  11665070329                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  11665070329                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  11665070329                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      1704152                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      1704152                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      1083877                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1083877                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        37282                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        37282                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        32953                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        32953                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      2788029                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      2788029                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      2788029                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      2788029                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.109541                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.109541                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.179154                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.179154                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.134006                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.134006                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.090675                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.090675                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.136604                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.136604                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.136604                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.136604                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13525.431900                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13525.431900                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 47070.569876                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 47070.569876                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9527.922338                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9527.922338                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15957.663989                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15957.663989                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30628.558639                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 30628.558639                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30628.558639                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 30628.558639                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs       543818                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets         1735                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs            16052                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets             10                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    33.878520                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets   173.500000                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks        64059                       # number of writebacks
system.cpu1.dcache.writebacks::total            64059                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       113306                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       113306                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       159042                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       159042                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          473                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total          473                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       272348                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       272348                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       272348                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       272348                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        73369                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total        73369                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        35139                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        35139                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4523                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4523                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         2988                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total         2988                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       108508                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       108508                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       108508                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       108508                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          150                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total          150                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2931                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2931                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3081                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3081                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    931066500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total    931066500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1566203053                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1566203053                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     38495000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     38495000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     44693500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     44693500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2497269553                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   2497269553                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2497269553                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   2497269553                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     30161500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     30161500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    685230000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    685230000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    715391500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    715391500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.043053                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.043053                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032420                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.032420                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.121319                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.121319                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.090675                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.090675                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.038919                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.038919                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.038919                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.038919                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12690.189317                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12690.189317                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44571.645551                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44571.645551                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8510.944064                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8510.944064                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14957.663989                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14957.663989                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23014.612314                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23014.612314                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23014.612314                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23014.612314                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201076.666667                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201076.666667                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 233787.103378                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 233787.103378                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 232194.579682                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 232194.579682                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           223833                       # number of replacements
system.cpu1.icache.tags.tagsinuse          467.351638                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            1306354                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           224343                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs             5.823021                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     1896743746500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   467.351638                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.912796                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.912796                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          510                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses          1762389                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses         1762389                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      1306354                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        1306354                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      1306354                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         1306354                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      1306354                       # number of overall hits
system.cpu1.icache.overall_hits::total        1306354                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       231631                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       231631                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       231631                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        231631                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       231631                       # number of overall misses
system.cpu1.icache.overall_misses::total       231631                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   3331435000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   3331435000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   3331435000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   3331435000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   3331435000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   3331435000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      1537985                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      1537985                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      1537985                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      1537985                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      1537985                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      1537985                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.150607                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.150607                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.150607                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.150607                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.150607                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.150607                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14382.509250                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14382.509250                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14382.509250                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14382.509250                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14382.509250                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14382.509250                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs          764                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               38                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    20.105263                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks       223833                       # number of writebacks
system.cpu1.icache.writebacks::total           223833                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         7227                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total         7227                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst         7227                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total         7227                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst         7227                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total         7227                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       224404                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       224404                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       224404                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       224404                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       224404                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       224404                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   2997413500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   2997413500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   2997413500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   2997413500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   2997413500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   2997413500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.145908                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.145908                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.145908                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.145908                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.145908                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.145908                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13357.219568                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13357.219568                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13357.219568                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13357.219568                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13357.219568                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13357.219568                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq                 7371                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7371                       # Transaction distribution
system.iobus.trans_dist::WriteReq               54609                       # Transaction distribution
system.iobus.trans_dist::WriteResp              54609                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          476                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        40504                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83456                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83456                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  123960                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        47616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1904                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total        73842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661632                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total      2661632                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2735474                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             12353500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               448000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              177000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            14420500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             2829000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5954500                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              217500                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               87000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              131500                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           215061495                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30500                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            27447000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            41952000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41696                       # number of replacements
system.iocache.tags.tagsinuse                0.507724                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41712                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1726981783000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     0.507724                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.031733                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.031733                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375552                       # Number of tag accesses
system.iocache.tags.data_accesses              375552                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          176                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              176                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
system.iocache.demand_misses::tsunami.ide          176                       # number of demand (read+write) misses
system.iocache.demand_misses::total               176                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide          176                       # number of overall misses
system.iocache.overall_misses::total              176                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     22155383                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     22155383                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide   5431231112                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   5431231112                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide     22155383                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     22155383                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide     22155383                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     22155383                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          176                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            176                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide          176                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             176                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide          176                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            176                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125882.857955                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125882.857955                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130709.258568                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130709.258568                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 125882.857955                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125882.857955                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 125882.857955                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125882.857955                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           126                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   17                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.411765                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          176                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          176                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide          176                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          176                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide          176                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          176                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13355383                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     13355383                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3353631112                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3353631112                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide     13355383                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     13355383                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide     13355383                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     13355383                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75882.857955                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 75882.857955                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80709.258568                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80709.258568                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75882.857955                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75882.857955                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75882.857955                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75882.857955                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   345304                       # number of replacements
system.l2c.tags.tagsinuse                65190.216948                       # Cycle average of tags in use
system.l2c.tags.total_refs                    3990482                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   410468                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     9.721786                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              11177481000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   53120.456427                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5260.305215                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     6531.960123                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      208.754945                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data       68.740237                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.810554                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.080266                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.099670                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.003185                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.001049                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.994724                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        65164                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          216                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1         1730                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         6285                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6556                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        50377                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.994324                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 38372212                       # Number of tag accesses
system.l2c.tags.data_accesses                38372212                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks       820126                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          820126                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks       859282                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total          859282                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data             172                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             249                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 421                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            51                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            25                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                76                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           155330                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            22838                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               178168                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        895446                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        222750                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1118196                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       736882                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data        66420                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           803302                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst              895446                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              892212                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              222750                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               89258                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2099666                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             895446                       # number of overall hits
system.l2c.overall_hits::cpu0.data             892212                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             222750                       # number of overall hits
system.l2c.overall_hits::cpu1.data              89258                       # number of overall hits
system.l2c.overall_hits::total                2099666                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          2766                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1119                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3885                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          420                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          441                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             861                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         114874                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           7330                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             122204                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        13592                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst         1628                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           15220                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       272976                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data          829                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         273805                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst             13592                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            387850                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1628                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              8159                       # number of demand (read+write) misses
system.l2c.demand_misses::total                411229                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            13592                       # number of overall misses
system.l2c.overall_misses::cpu0.data           387850                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1628                       # number of overall misses
system.l2c.overall_misses::cpu1.data             8159                       # number of overall misses
system.l2c.overall_misses::total               411229                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data      3922000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     17449000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     21371000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      2842500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       568500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3411000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  16040827500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1166717500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  17207545000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1816563500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    219865000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   2036428500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  33893464500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    116817000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  34010281500                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1816563500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  49934292000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    219865000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1283534500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     53254255000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1816563500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  49934292000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    219865000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1283534500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    53254255000                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       820126                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       820126                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks       859282                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total       859282                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2938                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1368                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            4306                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          471                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          466                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           937                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       270204                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        30168                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           300372                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       909038                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       224378                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1133416                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      1009858                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        67249                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      1077107                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          909038                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1280062                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          224378                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           97417                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2510895                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         909038                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1280062                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         224378                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          97417                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2510895                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.941457                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.817982                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.902229                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.891720                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.946352                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.918890                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.425138                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.242973                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.406842                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.014952                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.007256                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.013428                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.270311                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.012327                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.254204                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.014952                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.302993                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.007256                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.083753                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.163778                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.014952                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.302993                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.007256                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.083753                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.163778                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1417.932032                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15593.386953                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  5500.900901                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6767.857143                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1289.115646                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3961.672474                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139638.451695                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 159170.190996                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 140809.998036                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133649.462919                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135052.211302                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 133799.507227                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 124162.800026                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140913.148372                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 124213.515093                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 133649.462919                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 128746.401960                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 135052.211302                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 157315.173428                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 129500.241958                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 133649.462919                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 128746.401960                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 135052.211302                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 157315.173428                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 129500.241958                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               81651                       # number of writebacks
system.l2c.writebacks::total                    81651                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst           18                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           19                       # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             18                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 19                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            18                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                19                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks           11                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total           11                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2766                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1119                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3885                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          420                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          441                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          861                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       114874                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         7330                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        122204                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        13591                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1610                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        15201                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       272976                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data          829                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       273805                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        13591                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       387850                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1610                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         8159                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           411210                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        13591                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       387850                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1610                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         8159                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          411210                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.data         7045                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data          150                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total         7195                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        10126                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2931                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        13057                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        17171                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         3081                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        20252                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    198395000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     80293500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    278688500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     29951500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     31656500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     61608000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  14892087500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1093417500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  15985505000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1680522000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    201578500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   1882100500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  31173569000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    108527000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  31282096000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1680522000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  46065656500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    201578500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1201944500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  49149701500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1680522000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  46065656500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    201578500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1201944500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  49149701500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1475287500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     28274500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1503562000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2182363000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    649671500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2832034500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3657650500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    677946000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   4335596500                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941457                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.817982                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.902229                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.891720                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.946352                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.918890                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.425138                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.242973                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.406842                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.014951                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.007175                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013412                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.270311                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.012327                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.254204                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014951                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.302993                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007175                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.083753                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.163770                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014951                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.302993                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007175                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.083753                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.163770                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71726.319595                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71754.691689                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71734.491634                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71313.095238                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71783.446712                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71554.006969                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129638.451695                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 149170.190996                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 130809.998036                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123649.621073                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125204.037267                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123814.255641                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114198.936903                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130913.148372                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114249.542558                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123649.621073                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118771.835761                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125204.037267                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 147315.173428                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 119524.577467                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123649.621073                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118771.835761                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125204.037267                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 147315.173428                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 119524.577467                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209409.155429                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188496.666667                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208973.175817                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215520.738692                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221655.237120                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216897.794287                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213013.249083                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 220040.895813                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 214082.386925                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq                7195                       # Transaction distribution
system.membus.trans_dist::ReadResp             296301                       # Transaction distribution
system.membus.trans_dist::WriteReq              13057                       # Transaction distribution
system.membus.trans_dist::WriteResp             13057                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       123171                       # Transaction distribution
system.membus.trans_dist::CleanEvict           262771                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            10335                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq           5768                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            5173                       # Transaction distribution
system.membus.trans_dist::ReadExReq            122191                       # Transaction distribution
system.membus.trans_dist::ReadExResp           121777                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        289182                       # Transaction distribution
system.membus.trans_dist::BadAddressError           76                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40504                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1187227                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          152                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      1227883                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124828                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       124828                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1352711                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        73842                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31492800                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     31566642                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658240                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2658240                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                34224882                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            11791                       # Total snoops (count)
system.membus.snoop_fanout::samples            875399                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  875399    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              875399                       # Request fanout histogram
system.membus.reqLayer0.occupancy            36670000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1357207403                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer2.occupancy               98500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2187694355                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy           69834733                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests      5063738                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2531809                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       339719                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           1340                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         1272                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops           68                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq               7195                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2239104                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             13057                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            13057                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       943311                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean       859282                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          775827                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           10329                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq          5844                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          16173                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           301707                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          301707                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1133724                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      1098277                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError           76                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2546826                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3860959                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       579596                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       310532                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7297913                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    104800384                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    130368640                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     22732288                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     10357298                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              268258610                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          462469                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          2998699                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.119628                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.324813                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                2640250     88.05%     88.05% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 358173     11.94%     99.99% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    274      0.01%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                      2      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            2998699                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         4501023919                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           297385                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1365634171                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1954807358                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         338746615                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         168528157                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6529                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    184433                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   65060     40.50%     40.50% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.08%     40.58% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1928      1.20%     41.78% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    186      0.12%     41.90% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  93335     58.10%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              160640                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    64056     49.21%     49.21% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.10%     49.31% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1928      1.48%     50.79% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     186      0.14%     50.93% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   63870     49.07%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               130171                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1865607975500     97.03%     97.03% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               63996500      0.00%     97.03% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              577908500      0.03%     97.06% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30               88293000      0.00%     97.07% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            56422873000      2.93%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1922761046500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.984568                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.684309                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.810327                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.51%      3.51% # number of syscalls executed
system.cpu0.kern.syscall::3                        19      8.33%     11.84% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.75%     13.60% # number of syscalls executed
system.cpu0.kern.syscall::6                        33     14.47%     28.07% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.44%     28.51% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      3.95%     32.46% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.39%     36.84% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.63%     39.47% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.44%     39.91% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.32%     41.23% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.07%     44.30% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.88%     45.18% # number of syscalls executed
system.cpu0.kern.syscall::45                       36     15.79%     60.96% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.32%     62.28% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.39%     66.67% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.39%     71.05% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.44%     71.49% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.63%     74.12% # number of syscalls executed
system.cpu0.kern.syscall::71                       27     11.84%     85.96% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.32%     87.28% # number of syscalls executed
system.cpu0.kern.syscall::74                        7      3.07%     90.35% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.44%     90.79% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.32%     92.11% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      3.95%     96.05% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.88%     96.93% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.88%     97.81% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.44%     98.25% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.88%     99.12% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.88%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   228                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  284      0.17%      0.17% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.17% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.17% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.17% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3530      2.09%      2.26% # number of callpals executed
system.cpu0.kern.callpal::tbi                      50      0.03%      2.29% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.29% # number of callpals executed
system.cpu0.kern.callpal::swpipl               153808     90.93%     93.22% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6346      3.75%     96.97% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.97% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     96.97% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.01%     96.98% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.98% # number of callpals executed
system.cpu0.kern.callpal::rti                    4586      2.71%     99.69% # number of callpals executed
system.cpu0.kern.callpal::callsys                 386      0.23%     99.92% # number of callpals executed
system.cpu0.kern.callpal::imb                     138      0.08%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                169154                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             7135                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1348                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1347                      
system.cpu0.kern.mode_good::user                 1348                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.188788                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.317694                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1920558467500     99.89%     99.89% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          2202571000      0.11%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3531                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2548                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     55289                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   17293     36.54%     36.54% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1926      4.07%     40.61% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    284      0.60%     41.21% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  27821     58.79%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               47324                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    16920     47.31%     47.31% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1926      5.39%     52.69% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     284      0.79%     53.49% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   16636     46.51%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                35766                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1875921374000     97.58%     97.58% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              562894500      0.03%     97.61% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              139598000      0.01%     97.62% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            45773010000      2.38%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1922396876500                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.978431                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.597966                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.755769                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        11     11.22%     11.22% # number of syscalls executed
system.cpu1.kern.syscall::6                         9      9.18%     20.41% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      1.02%     21.43% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      6.12%     27.55% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      3.06%     30.61% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      3.06%     33.67% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      4.08%     37.76% # number of syscalls executed
system.cpu1.kern.syscall::45                       18     18.37%     56.12% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      3.06%     59.18% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      1.02%     60.20% # number of syscalls executed
system.cpu1.kern.syscall::71                       27     27.55%     87.76% # number of syscalls executed
system.cpu1.kern.syscall::74                        9      9.18%     96.94% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      3.06%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                    98                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  186      0.38%      0.38% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.38% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.39% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 1060      2.16%      2.55% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.01%      2.56% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      2.57% # number of callpals executed
system.cpu1.kern.callpal::swpipl                42140     86.06%     88.63% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2415      4.93%     93.56% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.56% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     93.57% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     93.58% # number of callpals executed
system.cpu1.kern.callpal::rti                    2973      6.07%     99.65% # number of callpals executed
system.cpu1.kern.callpal::callsys                 129      0.26%     99.91% # number of callpals executed
system.cpu1.kern.callpal::imb                      42      0.09%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 48967                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             1257                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                391                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2415                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                600                      
system.cpu1.kern.mode_good::user                  391                      
system.cpu1.kern.mode_good::idle                  209                      
system.cpu1.kern.mode_switch_good::kernel     0.477327                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.086542                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.295348                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        4412319000      0.23%      0.23% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           702202000      0.04%      0.27% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1916962357500     99.73%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    1061                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------