path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.901175                       # Number of seconds simulated
sim_ticks                                1901175003500                       # Number of ticks simulated
final_tick                               1901175003500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 154934                       # Simulator instruction rate (inst/s)
host_op_rate                                   154934                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5197600055                       # Simulator tick rate (ticks/s)
host_mem_usage                                 378544                       # Number of bytes of host memory used
host_seconds                                   365.78                       # Real time elapsed on the host
sim_insts                                    56671579                       # Number of instructions simulated
sim_ops                                      56671579                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst           885824                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24795264                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            95808                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           496320                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             26274176                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       885824                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        95808                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          981632                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7885056                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7885056                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             13841                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            387426                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1497                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              7755                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                410534                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          123204                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               123204                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              465935                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            13042073                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               50394                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              261060                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               505                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13819967                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         465935                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          50394                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             516329                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4147465                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4147465                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4147465                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             465935                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           13042073                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              50394                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             261060                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide              505                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               17967432                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        410534                       # Number of read requests accepted
system.physmem.writeReqs                       164756                       # Number of write requests accepted
system.physmem.readBursts                      410534                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     164756                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 26267904                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6272                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  10393408                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  26274176                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               10544384                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       98                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2335                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4921                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               25742                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25822                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25939                       # Per bank write bursts
system.physmem.perBankRdBursts::3               25643                       # Per bank write bursts
system.physmem.perBankRdBursts::4               25873                       # Per bank write bursts
system.physmem.perBankRdBursts::5               25657                       # Per bank write bursts
system.physmem.perBankRdBursts::6               25709                       # Per bank write bursts
system.physmem.perBankRdBursts::7               25201                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25222                       # Per bank write bursts
system.physmem.perBankRdBursts::9               26115                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25677                       # Per bank write bursts
system.physmem.perBankRdBursts::11              25575                       # Per bank write bursts
system.physmem.perBankRdBursts::12              25800                       # Per bank write bursts
system.physmem.perBankRdBursts::13              26085                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25301                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25075                       # Per bank write bursts
system.physmem.perBankWrBursts::0               10194                       # Per bank write bursts
system.physmem.perBankWrBursts::1               10103                       # Per bank write bursts
system.physmem.perBankWrBursts::2               10030                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9736                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9490                       # Per bank write bursts
system.physmem.perBankWrBursts::5               10167                       # Per bank write bursts
system.physmem.perBankWrBursts::6               10200                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9338                       # Per bank write bursts
system.physmem.perBankWrBursts::8                9741                       # Per bank write bursts
system.physmem.perBankWrBursts::9               10459                       # Per bank write bursts
system.physmem.perBankWrBursts::10              10157                       # Per bank write bursts
system.physmem.perBankWrBursts::11              10688                       # Per bank write bursts
system.physmem.perBankWrBursts::12              11170                       # Per bank write bursts
system.physmem.perBankWrBursts::13              11200                       # Per bank write bursts
system.physmem.perBankWrBursts::14              10147                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9577                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
system.physmem.totGap                    1901170614000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  410534                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 164756                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    317401                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     40588                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     43093                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9265                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        68                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        12                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2028                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4043                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5585                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     7574                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     9416                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    10988                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    11539                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    12489                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    12109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    12331                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    11277                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10599                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9498                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9695                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7582                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7282                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7090                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6622                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      448                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      388                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      346                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      309                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      292                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      276                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      253                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      259                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      234                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      228                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      206                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       32                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        5                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        67203                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      545.527075                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     333.566914                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     419.530844                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          14928     22.21%     22.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        11337     16.87%     39.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5205      7.75%     46.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2937      4.37%     51.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2377      3.54%     54.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1798      2.68%     57.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1602      2.38%     59.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1684      2.51%     62.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        25335     37.70%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          67203                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6020                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        68.178073                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2721.311016                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           6017     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6020                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6020                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        26.976246                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       20.646869                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       33.117275                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23            4955     82.31%     82.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31             186      3.09%     85.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39             316      5.25%     90.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47              58      0.96%     91.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55              93      1.54%     93.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63              41      0.68%     93.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71              21      0.35%     94.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79              11      0.18%     94.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87              26      0.43%     94.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95               4      0.07%     94.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103             17      0.28%     95.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111             4      0.07%     95.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119             7      0.12%     95.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127             2      0.03%     95.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135            20      0.33%     95.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143            42      0.70%     96.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151            17      0.28%     96.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159             7      0.12%     96.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167            80      1.33%     98.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175            45      0.75%     98.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183            12      0.20%     99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191            27      0.45%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199             6      0.10%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207             5      0.08%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             4      0.07%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223             2      0.03%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             4      0.07%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247             4      0.07%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255             2      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-295             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6020                       # Writes before turning the bus around for reads
system.physmem.totQLat                     3885054500                       # Total ticks spent queuing
system.physmem.totMemAccLat               11580729500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2052180000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9465.68                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28215.68                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.82                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           5.47                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.82                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        5.55                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.04                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         2.07                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.77                       # Average write queue length when enqueuing
system.physmem.readRowHits                     370181                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    135448                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.19                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  83.39                       # Row buffer hit rate for writes
system.physmem.avgGap                      3304716.95                       # Average gap between requests
system.physmem.pageHitRate                      88.26                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  253260000                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  138187500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1603570800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                513591840                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           124175095200                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            57090888495                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1090621618500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1274396212335                       # Total energy per rank (pJ)
system.physmem_0.averagePower              670.322456                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   1814181645000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     63484200000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     23503077500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  254688840                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  138967125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1597455600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                538429680                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           124175095200                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            57028143465                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1090676670000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1274409449910                       # Total energy per rank (pJ)
system.physmem_1.averagePower              670.329412                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   1814277217000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     63484200000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     23408681000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu0.branchPred.lookups               16131633                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         14074847                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           326763                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             9526803                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                5411642                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            56.804387                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 814199                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             17678                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     9231009                       # DTB read hits
system.cpu0.dtb.read_misses                     34580                       # DTB read misses
system.cpu0.dtb.read_acv                          535                       # DTB read access violations
system.cpu0.dtb.read_accesses                  687791                       # DTB read accesses
system.cpu0.dtb.write_hits                    5940395                       # DTB write hits
system.cpu0.dtb.write_misses                     7538                       # DTB write misses
system.cpu0.dtb.write_acv                         382                       # DTB write access violations
system.cpu0.dtb.write_accesses                 237219                       # DTB write accesses
system.cpu0.dtb.data_hits                    15171404                       # DTB hits
system.cpu0.dtb.data_misses                     42118                       # DTB misses
system.cpu0.dtb.data_acv                          917                       # DTB access violations
system.cpu0.dtb.data_accesses                  925010                       # DTB accesses
system.cpu0.itb.fetch_hits                    1435355                       # ITB hits
system.cpu0.itb.fetch_misses                    29386                       # ITB misses
system.cpu0.itb.fetch_acv                         625                       # ITB acv
system.cpu0.itb.fetch_accesses                1464741                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       112944275                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          26734623                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      70871158                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   16131633                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           6225841                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     78572167                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1087344                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                       938                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               28136                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles      1452901                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       461019                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          278                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  8195583                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               233790                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples         107793734                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.657470                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.965319                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                94531257     87.70%     87.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  858509      0.80%     88.49% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1823492      1.69%     90.18% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  785861      0.73%     90.91% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2602190      2.41%     93.33% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  590625      0.55%     93.88% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  664328      0.62%     94.49% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  839547      0.78%     95.27% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 5097925      4.73%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           107793734                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.142828                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.627488                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                21731474                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             75223274                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  8544304                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1787077                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                507604                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              524648                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                36495                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              62167212                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               115754                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                507604                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                22589385                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               48401768                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      19164228                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  9376952                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              7753795                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              60013920                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents               204923                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               2024034                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                144343                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               3822558                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           40119139                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             72975711                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        72834321                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           131688                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             35221894                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 4897237                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1480119                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        216056                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 12920416                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             9368350                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6206352                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1340557                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores          962340                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  53512619                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1895957                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 52599778                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            52230                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6392747                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      3006442                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1305426                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    107793734                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.487967                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.221871                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           86044446     79.82%     79.82% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            9475309      8.79%     88.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3928815      3.64%     92.26% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2790586      2.59%     94.85% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2836372      2.63%     97.48% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1349941      1.25%     98.73% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             893970      0.83%     99.56% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             358292      0.33%     99.89% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             116003      0.11%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      107793734                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                 177733     18.25%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     18.25% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                467063     47.95%     66.19% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               329340     33.81%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             3770      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             36087462     68.61%     68.61% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               57222      0.11%     68.72% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.72% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              28709      0.05%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9582527     18.22%     87.00% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            6011046     11.43%     98.43% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            827159      1.57%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              52599778                       # Type of FU issued
system.cpu0.iq.rate                          0.465714                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     974136                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.018520                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         213441030                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         61548330                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     51220095                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             578625                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            270952                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       265721                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              53258517                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 311627                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          583786                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1112279                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         5019                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        18330                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       503254                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        18853                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       369989                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                507604                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               44339596                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              1604348                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           58817574                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           124782                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              9368350                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6206352                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1675353                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 48473                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              1332642                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         18330                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        164161                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       356822                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              520983                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             52091421                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9288991                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           508356                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      3408998                       # number of nop insts executed
system.cpu0.iew.exec_refs                    15250639                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 8273174                       # Number of branches executed
system.cpu0.iew.exec_stores                   5961648                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.461213                       # Inst execution rate
system.cpu0.iew.wb_sent                      51600991                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     51485816                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 26436063                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 36546981                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.455851                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.723345                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        7016261                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         590531                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           476969                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    106554717                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.485172                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.424408                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     88252662     82.82%     82.82% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      7298996      6.85%     89.67% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      3974083      3.73%     93.40% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2090799      1.96%     95.37% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1561874      1.47%     96.83% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       585444      0.55%     97.38% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       439090      0.41%     97.79% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       445608      0.42%     98.21% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1906161      1.79%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    106554717                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            51697359                       # Number of instructions committed
system.cpu0.commit.committedOps              51697359                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      13959169                       # Number of memory references committed
system.cpu0.commit.loads                      8256071                       # Number of loads committed
system.cpu0.commit.membars                     200989                       # Number of memory barriers committed
system.cpu0.commit.branches                   7816314                       # Number of branches committed
system.cpu0.commit.fp_insts                    262681                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 47879291                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              663768                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass      2971590      5.75%      5.75% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        33646334     65.08%     70.83% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          55999      0.11%     70.94% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     70.94% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd         28236      0.05%     70.99% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     70.99% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     70.99% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     70.99% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv          1883      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.00% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead        8457060     16.36%     87.36% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite       5709098     11.04%     98.40% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess       827159      1.60%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         51697359                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1906161                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   163161097                       # The number of ROB reads
system.cpu0.rob.rob_writes                  118660594                       # The number of ROB writes
system.cpu0.timesIdled                         501791                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        5150541                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3689405733                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   48729536                       # Number of Instructions Simulated
system.cpu0.committedOps                     48729536                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              2.317779                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.317779                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.431448                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.431448                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                68466406                       # number of integer regfile reads
system.cpu0.int_regfile_writes               37249066                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   130692                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  131766                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1811017                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                827352                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements          1291740                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          505.889209                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           10636670                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1292252                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs             8.231111                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         25151000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.889209                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988065                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.988065                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          217                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          245                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         57483025                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        57483025                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      6556019                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6556019                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3715997                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3715997                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       164872                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       164872                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       189733                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       189733                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10272016                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        10272016                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10272016                       # number of overall hits
system.cpu0.dcache.overall_hits::total       10272016                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1615331                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1615331                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1779982                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1779982                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21282                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21282                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2627                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         2627                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3395313                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3395313                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3395313                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3395313                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  40801843239                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  40801843239                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  80191363617                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  80191363617                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    336613990                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    336613990                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     19436381                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     19436381                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 120993206856                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 120993206856                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 120993206856                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 120993206856                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      8171350                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8171350                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5495979                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5495979                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       186154                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       186154                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       192360                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       192360                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     13667329                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     13667329                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     13667329                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     13667329                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.197682                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.197682                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.323870                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.323870                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.114325                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.114325                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.013657                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.013657                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.248425                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.248425                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.248425                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.248425                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25259.122272                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 25259.122272                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45051.783455                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 45051.783455                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15816.840053                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15816.840053                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7398.698515                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7398.698515                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35635.361705                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 35635.361705                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35635.361705                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 35635.361705                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      3895440                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         3799                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           167914                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets             94                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.199019                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    40.414894                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       762456                       # number of writebacks
system.cpu0.dcache.writebacks::total           762456                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       593909                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       593909                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1512221                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1512221                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         5168                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         5168                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      2106130                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      2106130                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      2106130                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      2106130                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1021422                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      1021422                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       267761                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       267761                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        16114                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        16114                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2626                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         2626                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1289183                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1289183                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1289183                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1289183                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  27591103326                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  27591103326                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11693886534                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11693886534                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    178834256                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    178834256                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     14183619                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     14183619                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  39284989860                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  39284989860                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  39284989860                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  39284989860                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1458359000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1458359000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2137811998                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2137811998                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3596170998                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3596170998                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.125000                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.125000                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048719                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048719                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.086563                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.086563                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.013651                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.013651                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.094326                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.094326                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.094326                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.094326                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27012.442777                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27012.442777                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43672.852036                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43672.852036                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11098.067271                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11098.067271                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5401.225819                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5401.225819                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30472.779939                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30472.779939                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30472.779939                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30472.779939                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements           914535                       # number of replacements
system.cpu0.icache.tags.tagsinuse          509.589702                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs            7236389                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           915045                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs             7.908233                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      26485919250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.589702                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995292                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.995292                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          427                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses          9110810                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses         9110810                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst      7236389                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        7236389                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      7236389                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         7236389                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      7236389                       # number of overall hits
system.cpu0.icache.overall_hits::total        7236389                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       959193                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       959193                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       959193                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        959193                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       959193                       # number of overall misses
system.cpu0.icache.overall_misses::total       959193                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13598697683                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  13598697683                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  13598697683                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  13598697683                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  13598697683                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  13598697683                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      8195582                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      8195582                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      8195582                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      8195582                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      8195582                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      8195582                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.117038                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.117038                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.117038                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.117038                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.117038                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.117038                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14177.227819                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14177.227819                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14177.227819                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14177.227819                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14177.227819                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14177.227819                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         4960                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              197                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    25.177665                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        43965                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        43965                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        43965                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        43965                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        43965                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        43965                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       915228                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       915228                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       915228                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       915228                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       915228                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       915228                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11221708315                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11221708315                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11221708315                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11221708315                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11221708315                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11221708315                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.111673                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.111673                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.111673                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.111673                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.111673                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.111673                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12261.106866                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12261.106866                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12261.106866                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12261.106866                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12261.106866                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12261.106866                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                3410499                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          2981782                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect            63006                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             1861186                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                 813170                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            43.690958                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 161954                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect              4822                       # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1800297                       # DTB read hits
system.cpu1.dtb.read_misses                      9623                       # DTB read misses
system.cpu1.dtb.read_acv                            4                       # DTB read access violations
system.cpu1.dtb.read_accesses                  290908                       # DTB read accesses
system.cpu1.dtb.write_hits                    1120103                       # DTB write hits
system.cpu1.dtb.write_misses                     2035                       # DTB write misses
system.cpu1.dtb.write_acv                          37                       # DTB write access violations
system.cpu1.dtb.write_accesses                 109629                       # DTB write accesses
system.cpu1.dtb.data_hits                     2920400                       # DTB hits
system.cpu1.dtb.data_misses                     11658                       # DTB misses
system.cpu1.dtb.data_acv                           41                       # DTB access violations
system.cpu1.dtb.data_accesses                  400537                       # DTB accesses
system.cpu1.itb.fetch_hits                     513208                       # ITB hits
system.cpu1.itb.fetch_misses                     5417                       # ITB misses
system.cpu1.itb.fetch_acv                          59                       # ITB acv
system.cpu1.itb.fetch_accesses                 518625                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                        13834996                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles           5742756                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      13201278                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    3410499                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches            975124                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      7052078                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 251690                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.MiscStallCycles               24829                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles       212437                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        51117                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles           24                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  1482208                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                50416                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples          13209086                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.999409                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.408470                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                10898169     82.51%     82.51% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  144102      1.09%     83.60% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  239022      1.81%     85.41% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  173764      1.32%     86.72% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  293834      2.22%     88.95% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  119928      0.91%     89.85% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  132080      1.00%     90.85% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  175112      1.33%     92.18% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 1033075      7.82%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            13209086                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.246512                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.954195                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 4781490                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles              6446001                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  1665086                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               196515                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                119993                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              102189                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                 5928                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              10739248                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                19374                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                119993                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 4918512                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                 544557                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       5139003                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  1724887                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles               762132                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              10178184                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 4877                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 68265                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                 13199                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents                289695                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands            6692544                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups             12133960                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        12078154                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            50250                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps              5671659                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 1020885                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            419664                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         38232                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  1772644                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             1865226                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            1191683                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           210655                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          119712                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                   8963290                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             478811                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                  8726606                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            20522                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        1437541                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined       698510                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        352654                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     13209086                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.660652                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.378469                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0            9547804     72.28%     72.28% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            1625741     12.31%     84.59% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2             686242      5.20%     89.79% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             474957      3.60%     93.38% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             417301      3.16%     96.54% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             221804      1.68%     98.22% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             145793      1.10%     99.32% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7              65024      0.49%     99.82% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              24420      0.18%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       13209086                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  22353      9.61%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.61% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                126163     54.23%     63.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                84116     36.16%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             3518      0.04%      0.04% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              5425627     62.17%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               15090      0.17%     62.39% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.39% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd              10661      0.12%     62.51% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.51% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.51% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.51% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1759      0.02%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.53% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             1878240     21.52%     84.05% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            1141614     13.08%     97.13% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            250097      2.87%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total               8726606                       # Type of FU issued
system.cpu1.iq.rate                          0.630763                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     232632                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.026658                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          30722514                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         10791679                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses      8409842                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads             192938                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes             91772                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses        89511                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses               8852667                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 103053                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           90033                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       271460                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          498                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         3940                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       125337                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads          380                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        50736                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                119993                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 268498                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               245239                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts            9936241                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts            29107                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              1865226                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             1191683                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            435120                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                  4465                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents               239666                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          3940                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         28286                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect        93108                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              121394                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts              8606074                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              1816179                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           120532                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       494140                       # number of nop insts executed
system.cpu1.iew.exec_refs                     2943760                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 1279494                       # Number of branches executed
system.cpu1.iew.exec_stores                   1127581                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.622051                       # Inst execution rate
system.cpu1.iew.wb_sent                       8526125                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                      8499353                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  4051784                       # num instructions producing a value
system.cpu1.iew.wb_consumers                  5752933                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.614337                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.704299                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        1506985                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         126157                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           110245                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     12932417                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.645119                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.622232                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0      9905025     76.59%     76.59% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      1407731     10.89%     87.48% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2       501740      3.88%     91.36% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       308618      2.39%     93.74% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       224670      1.74%     95.48% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        96970      0.75%     96.23% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6        89070      0.69%     96.92% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       100805      0.78%     97.70% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       297788      2.30%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     12932417                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts             8342954                       # Number of instructions committed
system.cpu1.commit.committedOps               8342954                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       2660112                       # Number of memory references committed
system.cpu1.commit.loads                      1593766                       # Number of loads committed
system.cpu1.commit.membars                      39768                       # Number of memory barriers committed
system.cpu1.commit.branches                   1189273                       # Number of branches committed
system.cpu1.commit.fp_insts                     87820                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                  7729091                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              132492                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass       404429      4.85%      4.85% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu         4960733     59.46%     64.31% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          14917      0.18%     64.49% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.49% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd         10656      0.13%     64.61% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.61% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.61% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.61% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv          1759      0.02%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.64% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead        1633534     19.58%     84.22% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite       1066829     12.79%     97.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess       250097      3.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total          8342954                       # Class of committed instruction
system.cpu1.commit.bw_lim_events               297788                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                    22401053                       # The number of ROB reads
system.cpu1.rob.rob_writes                   19972727                       # The number of ROB writes
system.cpu1.timesIdled                         110858                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                         625910                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3787862669                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                    7942043                       # Number of Instructions Simulated
system.cpu1.committedOps                      7942043                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.741995                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.741995                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.574055                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.574055                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                11080172                       # number of integer regfile reads
system.cpu1.int_regfile_writes                6056867                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    49492                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   48750                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 911686                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                198554                       # number of misc regfile writes
system.cpu1.dcache.tags.replacements            93396                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          491.127271                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            2362095                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs            93708                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            25.206973                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     1032235519500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   491.127271                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.959233                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.959233                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          312                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          312                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.609375                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         11044469                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        11044469                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      1462423                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1462423                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data       846221                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        846221                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        29364                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        29364                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        27945                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        27945                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      2308644                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         2308644                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      2308644                       # number of overall hits
system.cpu1.dcache.overall_hits::total        2308644                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       178507                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       178507                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       183677                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       183677                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         4603                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         4603                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data         2762                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         2762                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       362184                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        362184                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       362184                       # number of overall misses
system.cpu1.dcache.overall_misses::total       362184                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2741731463                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2741731463                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   7132330313                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   7132330313                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     45481992                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     45481992                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     20461911                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     20461911                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   9874061776                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   9874061776                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   9874061776                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   9874061776                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      1640930                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      1640930                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      1029898                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1029898                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        33967                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        33967                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        30707                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        30707                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      2670828                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      2670828                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      2670828                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      2670828                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.108784                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.108784                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.178345                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.178345                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.135514                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.135514                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.089947                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.089947                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.135607                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.135607                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.135607                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.135607                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15359.237806                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15359.237806                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38830.829734                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 38830.829734                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9880.945470                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9880.945470                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7408.367487                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7408.367487                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27262.556535                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 27262.556535                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27262.556535                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 27262.556535                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs       351094                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets          268                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs            15302                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets             15                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs    22.944321                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    17.866667                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks        60059                       # number of writebacks
system.cpu1.dcache.writebacks::total            60059                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       108966                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       108966                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       150714                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       150714                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          427                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total          427                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       259680                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       259680                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       259680                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       259680                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        69541                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total        69541                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        32963                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        32963                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4176                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4176                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         2762                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total         2762                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       102504                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       102504                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       102504                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       102504                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    829052502                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total    829052502                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1081287205                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1081287205                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     31817008                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     31817008                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     14937089                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     14937089                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   1910339707                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   1910339707                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   1910339707                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   1910339707                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     24846500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     24846500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    618764500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    618764500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    643611000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    643611000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.042379                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.042379                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032006                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.032006                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.122943                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.122943                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.089947                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.089947                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.038379                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.038379                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.038379                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.038379                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.779986                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11921.779986                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32803.058126                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32803.058126                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7619.015326                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7619.015326                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5408.069877                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5408.069877                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18636.733269                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18636.733269                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18636.733269                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18636.733269                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           205003                       # number of replacements
system.cpu1.icache.tags.tagsinuse          470.613699                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            1269898                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           205514                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs             6.179131                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     1878408675250                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   470.613699                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.919167                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.919167                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          510                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses          1687783                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses         1687783                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      1269898                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        1269898                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      1269898                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         1269898                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      1269898                       # number of overall hits
system.cpu1.icache.overall_hits::total        1269898                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       212310                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       212310                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       212310                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        212310                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       212310                       # number of overall misses
system.cpu1.icache.overall_misses::total       212310                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   2888653039                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   2888653039                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   2888653039                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   2888653039                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   2888653039                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   2888653039                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      1482208                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      1482208                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      1482208                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      1482208                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      1482208                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      1482208                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.143239                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.143239                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.143239                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.143239                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.143239                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.143239                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13605.826570                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13605.826570                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13605.826570                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13605.826570                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13605.826570                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13605.826570                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs          412                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               26                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    15.846154                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         6735                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total         6735                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst         6735                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total         6735                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst         6735                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total         6735                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       205575                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       205575                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       205575                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       205575                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       205575                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       205575                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   2403236890                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   2403236890                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   2403236890                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   2403236890                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   2403236890                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   2403236890                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.138695                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.138695                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.138695                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.138695                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.138695                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.138695                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11690.316867                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11690.316867                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11690.316867                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11690.316867                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11690.316867                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11690.316867                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq                 7377                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7377                       # Transaction distribution
system.iobus.trans_dist::WriteReq               54536                       # Transaction distribution
system.iobus.trans_dist::WriteResp              12984                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11756                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        40360                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83466                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83466                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  123826                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        47024                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total        73266                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661672                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total      2661672                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2734938                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             11111000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               359000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13505000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             2450000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           406222784                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            27376000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            42026793                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41701                       # number of replacements
system.iocache.tags.tagsinuse                0.465228                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41717                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1710337218000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     0.465228                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.029077                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.029077                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375597                       # Number of tag accesses
system.iocache.tags.data_accesses              375597                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          181                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              181                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::tsunami.ide          181                       # number of demand (read+write) misses
system.iocache.demand_misses::total               181                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide          181                       # number of overall misses
system.iocache.overall_misses::total              181                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     22038383                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     22038383                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide  13652440608                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  13652440608                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide     22038383                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     22038383                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide     22038383                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     22038383                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          181                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            181                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide          181                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             181                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide          181                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            181                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121759.022099                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 121759.022099                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328562.779361                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 328562.779361                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 121759.022099                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 121759.022099                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 121759.022099                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 121759.022099                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        206720                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                23552                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.777174                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          181                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          181                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide          181                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          181                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide          181                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          181                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12625383                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12625383                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide  11491649194                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total  11491649194                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide     12625383                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     12625383                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide     12625383                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     12625383                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69753.497238                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 69753.497238                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276560.675635                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276560.675635                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69753.497238                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 69753.497238                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69753.497238                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 69753.497238                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   345072                       # number of replacements
system.l2c.tags.tagsinuse                65237.196274                       # Cycle average of tags in use
system.l2c.tags.total_refs                    2611817                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   410198                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     6.367210                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               7093665750                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   53609.898857                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5305.766317                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     6049.152476                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      209.737010                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data       62.641613                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.818022                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.080960                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.092303                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.003200                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000956                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.995441                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        65126                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          216                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1         2602                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         5798                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5210                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        51300                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.993744                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 27343076                       # Number of tag accesses
system.l2c.tags.data_accesses                27343076                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst             901250                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             743094                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             204045                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              62863                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1911252                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          822515                       # number of Writeback hits
system.l2c.Writeback_hits::total               822515                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             174                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             236                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 410                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            50                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            28                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                78                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           157590                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            21227                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               178817                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              901250                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              900684                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              204045                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               84090                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2090069                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             901250                       # number of overall hits
system.l2c.overall_hits::cpu0.data             900684                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             204045                       # number of overall hits
system.l2c.overall_hits::cpu1.data              84090                       # number of overall hits
system.l2c.overall_hits::total                2090069                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            13855                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           273150                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             1501                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data              784                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               289290                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2701                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1143                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3844                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          381                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          416                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             797                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         114840                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           7053                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             121893                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             13855                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            387990                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1501                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              7837                       # number of demand (read+write) misses
system.l2c.demand_misses::total                411183                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            13855                       # number of overall misses
system.l2c.overall_misses::cpu0.data           387990                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1501                       # number of overall misses
system.l2c.overall_misses::cpu1.data             7837                       # number of overall misses
system.l2c.overall_misses::total               411183                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst   1053790500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  17926629500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    116949250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     69771500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    19167140750                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      1289954                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      4510297                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      5800251                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       801966                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        70497                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       872463                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   9554653251                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    752768967                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  10307422218                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1053790500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  27481282751                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    116949250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    822540467                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     29474562968                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1053790500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  27481282751                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    116949250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    822540467                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    29474562968                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         915105                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data        1016244                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         205546                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          63647                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2200542                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       822515                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           822515                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2875                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1379                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            4254                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          431                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          444                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           875                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       272430                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        28280                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           300710                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          915105                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1288674                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          205546                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           91927                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2501252                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         915105                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1288674                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         205546                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          91927                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2501252                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015140                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.268784                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.007303                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.012318                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.131463                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.939478                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.828861                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.903620                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.883991                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.936937                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.910857                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.421539                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.249399                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.405351                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015140                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.301077                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.007303                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.085252                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.164391                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015140                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.301077                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.007303                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.085252                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.164391                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76058.498737                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 65629.249497                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77914.223851                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 88994.260204                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 66255.801272                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   477.583858                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3946.016623                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1508.910250                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2104.897638                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   169.463942                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1094.683814                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83199.697414                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 106730.322841                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 84561.231720                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 76058.498737                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 70829.873840                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 77914.223851                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 104956.037642                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 71682.348171                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 76058.498737                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 70829.873840                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 77914.223851                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 104956.037642                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 71682.348171                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               81684                       # number of writebacks
system.l2c.writebacks::total                    81684                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst            13                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst             13                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst            13                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        13842                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       273149                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         1497                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data          784                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          289272                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2701                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1143                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3844                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          381                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          416                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          797                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       114840                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         7053                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        121893                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        13842                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       387989                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1497                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         7837                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           411165                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        13842                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       387989                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1497                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         7837                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          411165                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    878413500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  14522738500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     97828500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     60106500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  15559087000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     27191193                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     11450632                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     38641825                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      3833377                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4164911                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      7998288                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   8153414747                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    665986031                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   8819400778                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    878413500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  22676153247                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     97828500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    726092531                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  24378487778                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    878413500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  22676153247                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     97828500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    726092531                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  24378487778                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1366462500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     23156500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1389619000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2015759500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    582978000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2598737500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3382222000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    606134500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   3988356500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015126                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.268783                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.007283                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.012318                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.131455                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.939478                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.828861                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.903620                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.883991                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.936937                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.910857                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.421539                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.249399                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.405351                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015126                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.301076                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007283                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.085252                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.164384                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015126                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.301076                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007283                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.085252                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.164384                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63460.013004                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53167.825985                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65349.699399                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76666.454082                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 53787.048176                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10067.083673                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.050744                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.503902                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10061.356955                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.805288                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.493099                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70998.038549                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 94425.922444                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 72353.628002                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63460.013004                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58445.350891                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65349.699399                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 92649.295776                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 59291.252363                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63460.013004                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58445.350891                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65349.699399                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 92649.295776                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 59291.252363                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              296649                       # Transaction distribution
system.membus.trans_dist::ReadResp             296568                       # Transaction distribution
system.membus.trans_dist::WriteReq              12984                       # Transaction distribution
system.membus.trans_dist::WriteResp             12984                       # Transaction distribution
system.membus.trans_dist::Writeback            123204                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             9668                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq           5310                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4924                       # Transaction distribution
system.membus.trans_dist::ReadExReq            121989                       # Transaction distribution
system.membus.trans_dist::ReadExResp           121610                       # Transaction distribution
system.membus.trans_dist::BadAddressError           81                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40360                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       923282                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          162                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       963804                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124820                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       124820                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1088624                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        73266                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31500992                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     31574258                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5317568                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      5317568                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                36891826                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            10884                       # Total snoops (count)
system.membus.snoop_fanout::samples            591178                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  591178    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              591178                       # Request fanout histogram
system.membus.reqLayer0.occupancy            38973998                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1927807998                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer2.occupancy              100000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3829664091                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy           43225207                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.trans_dist::ReadReq            2228449                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2228352                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             12984                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            12984                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           822515                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        41553                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            9795                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq          5388                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          15183                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           301926                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          301926                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError           81                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1830333                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3396960                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       411121                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       269188                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               5907602                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     58566720                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    131328844                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     13154944                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side      9749222                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              212799730                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                           73699                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          3402430                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            3.012266                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.110070                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                3360696     98.77%     98.77% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                  41734      1.23%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            3402430                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         4987291538                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.3                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           742500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4124247177                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        5936070669                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         925874109                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         467054772                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6564                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    186274                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   65832     40.54%     40.54% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.08%     40.62% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1922      1.18%     41.81% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    173      0.11%     41.91% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  94323     58.09%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              162381                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    64799     49.22%     49.22% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.10%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1922      1.46%     50.78% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     173      0.13%     50.91% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   64626     49.09%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               131651                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1859979639500     97.83%     97.83% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               61305500      0.00%     97.84% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              538798500      0.03%     97.86% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30               78674500      0.00%     97.87% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            40515747500      2.13%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1901174165500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.984309                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.685156                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.810754                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.45%      3.45% # number of syscalls executed
system.cpu0.kern.syscall::3                        20      8.62%     12.07% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.72%     13.79% # number of syscalls executed
system.cpu0.kern.syscall::6                        33     14.22%     28.02% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.43%     28.45% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      3.88%     32.33% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.31%     36.64% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.59%     39.22% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.43%     39.66% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.29%     40.95% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.02%     43.97% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.86%     44.83% # number of syscalls executed
system.cpu0.kern.syscall::45                       39     16.81%     61.64% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.29%     62.93% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.31%     67.24% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.31%     71.55% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.43%     71.98% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.59%     74.57% # number of syscalls executed
system.cpu0.kern.syscall::71                       27     11.64%     86.21% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.29%     87.50% # number of syscalls executed
system.cpu0.kern.syscall::74                        7      3.02%     90.52% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.43%     90.95% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.29%     92.24% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      3.88%     96.12% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.86%     96.98% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.86%     97.84% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.43%     98.28% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.86%     99.14% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.86%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   232                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  266      0.16%      0.16% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.16% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.16% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.16% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3573      2.09%      2.25% # number of callpals executed
system.cpu0.kern.callpal::tbi                      50      0.03%      2.28% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.28% # number of callpals executed
system.cpu0.kern.callpal::swpipl               155550     90.98%     93.26% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6382      3.73%     96.99% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.99% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     96.99% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.01%     97.00% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     97.00% # number of callpals executed
system.cpu0.kern.callpal::rti                    4604      2.69%     99.69% # number of callpals executed
system.cpu0.kern.callpal::callsys                 391      0.23%     99.92% # number of callpals executed
system.cpu0.kern.callpal::imb                     138      0.08%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                170980                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             7167                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1355                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1354                      
system.cpu0.kern.mode_good::user                 1355                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.188921                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.317883                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1899194834000     99.90%     99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          1979323500      0.10%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3574                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2428                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     53091                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   16423     36.25%     36.25% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1920      4.24%     40.49% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    266      0.59%     41.08% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  26695     58.92%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               45304                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    16079     47.18%     47.18% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1920      5.63%     52.82% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     266      0.78%     53.60% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   15813     46.40%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                34078                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1870417466500     98.40%     98.40% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              530332500      0.03%     98.43% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              120265000      0.01%     98.43% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            29780754000      1.57%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1900848818000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.979054                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.592358                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.752207                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        10     10.64%     10.64% # number of syscalls executed
system.cpu1.kern.syscall::6                         9      9.57%     20.21% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      1.06%     21.28% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      6.38%     27.66% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      3.19%     30.85% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      3.19%     34.04% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      4.26%     38.30% # number of syscalls executed
system.cpu1.kern.syscall::45                       15     15.96%     54.26% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      3.19%     57.45% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      1.06%     58.51% # number of syscalls executed
system.cpu1.kern.syscall::71                       27     28.72%     87.23% # number of syscalls executed
system.cpu1.kern.syscall::74                        9      9.57%     96.81% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      3.19%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                    94                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  173      0.37%      0.37% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.37% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.38% # number of callpals executed
system.cpu1.kern.callpal::swpctx                  989      2.11%      2.49% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.01%      2.49% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      2.51% # number of callpals executed
system.cpu1.kern.callpal::swpipl                40205     85.85%     88.36% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2366      5.05%     93.41% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.41% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     93.42% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     93.43% # number of callpals executed
system.cpu1.kern.callpal::rti                    2912      6.22%     99.64% # number of callpals executed
system.cpu1.kern.callpal::callsys                 124      0.26%     99.91% # number of callpals executed
system.cpu1.kern.callpal::imb                      42      0.09%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 46833                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             1197                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                384                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2372                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                574                      
system.cpu1.kern.mode_good::user                  384                      
system.cpu1.kern.mode_good::idle                  190                      
system.cpu1.kern.mode_switch_good::kernel     0.479532                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.080101                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.290412                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        3852720500      0.20%      0.20% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           690217500      0.04%      0.24% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1895996394000     99.76%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                     990                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------