path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.867374                       # Number of seconds simulated
sim_ticks                                1867373908500                       # Number of ticks simulated
final_tick                               1867373908500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 123272                       # Simulator instruction rate (inst/s)
host_op_rate                                   123272                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4349339718                       # Simulator tick rate (ticks/s)
host_mem_usage                                 299108                       # Number of bytes of host memory used
host_seconds                                   429.35                       # Real time elapsed on the host
sim_insts                                    52926469                       # Number of instructions simulated
sim_ops                                      52926469                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            969792                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24879488                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28501568                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       969792                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          969792                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7518720                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7518720                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              15153                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388742                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                445337                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          117480                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               117480                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               519335                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13323249                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1420330                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15262914                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          519335                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             519335                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4026360                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4026360                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4026360                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              519335                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13323249                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1420330                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19289275                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.l2cache.replacements                        338398                       # number of replacements
system.cpu.l2cache.tagsinuse                     65348.140689                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                         2559915                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                        403567                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                          6.343222                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                    4870006000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks        53844.889123                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst           5363.726417                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data           6139.525149                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks           0.821608                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst             0.081844                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data             0.093682                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total                0.997133                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst             1007783                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data              827771                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total                1835554                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks          841020                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total               841020                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data               31                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total                  31                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data              3                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total                 3                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data            185546                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total               185546                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst              1007783                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data              1013317                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total                 2021100                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst             1007783                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data             1013317                       # number of overall hits
system.cpu.l2cache.overall_hits::total                2021100                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst             15155                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data            273854                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total               289009                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data             54                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total                54                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data          115395                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total             115395                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst              15155                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data             389249                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total                404404                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst             15155                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data            389249                       # number of overall misses
system.cpu.l2cache.overall_misses::total               404404                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    807128998                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  14259763500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    15066892498                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       376500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       376500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6225363497                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   6225363497                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    807128998                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  20485126997                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     21292255995                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    807128998                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  20485126997                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    21292255995                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         1022938                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data         1101625                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total            2124563                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       841020                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total           841020                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           85                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total              85                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total             5                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        300941                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           300941                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          1022938                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          1402566                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total             2425504                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         1022938                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         1402566                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total            2425504                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst       0.014815                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data       0.248591                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total          0.136032                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.635294                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total       0.635294                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.400000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.400000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383447                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total        0.383447                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst        0.014815                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data        0.277526                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total           0.166730                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst       0.014815                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data       0.277526                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total          0.166730                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53258.264467                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52070.678172                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52132.952600                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  6972.222222                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  6972.222222                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53948.294961                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53948.294961                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53258.264467                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52627.307962                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52650.952995                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53258.264467                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52627.307962                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52650.952995                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets                      0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                              0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                             0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks               75968                       # number of writebacks
system.cpu.l2cache.writebacks::total                    75968                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst              1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst               1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst              1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total                 1                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15154                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273854                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          289008                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           54                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           54                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115395                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        115395                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         15154                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        389249                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total           404403                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        15154                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       389249                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          404403                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    621904998                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  10983272500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  11605177498                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      2245000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      2245000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        80000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        80000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4831334497                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4831334497                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    621904998                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15814606997                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  16436511995                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    621904998                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15814606997                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  16436511995                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1333882500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333882500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1884635500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1884635500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3218518000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3218518000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014814                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248591                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.136032                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.635294                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.635294                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383447                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383447                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014814                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277526                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total      0.166729                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014814                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277526                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.166729                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41038.999472                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40106.306645                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40155.211960                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 41574.074074                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 41574.074074                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41867.797539                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41867.797539                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41038.999472                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40628.510277                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40643.892343                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41038.999472                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40628.510277                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40643.892343                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41685                       # number of replacements
system.iocache.tagsinuse                     1.309507                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1711308479000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       1.309507                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.081844                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.081844                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     20672998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     20672998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  11464497806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  11464497806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  11485170804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  11485170804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  11485170804                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  11485170804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119497.098266                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275907.244080                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 275907.244080                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 275258.737064                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 275258.737064                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 275258.737064                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 275258.737064                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs     199587000                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                24660                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  8093.552311                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11676000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     11676000                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   9303643992                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   9303643992                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   9315319992                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9315319992                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   9315319992                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9315319992                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223903.638621                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 223903.638621                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223255.122636                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 223255.122636                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223255.122636                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 223255.122636                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9950205                       # DTB read hits
system.cpu.dtb.read_misses                      43861                       # DTB read misses
system.cpu.dtb.read_acv                           493                       # DTB read access violations
system.cpu.dtb.read_accesses                   957335                       # DTB read accesses
system.cpu.dtb.write_hits                     6626699                       # DTB write hits
system.cpu.dtb.write_misses                      9966                       # DTB write misses
system.cpu.dtb.write_acv                          395                       # DTB write access violations
system.cpu.dtb.write_accesses                  340478                       # DTB write accesses
system.cpu.dtb.data_hits                     16576904                       # DTB hits
system.cpu.dtb.data_misses                      53827                       # DTB misses
system.cpu.dtb.data_acv                           888                       # DTB access violations
system.cpu.dtb.data_accesses                  1297813                       # DTB accesses
system.cpu.itb.fetch_hits                     1339762                       # ITB hits
system.cpu.itb.fetch_misses                     37185                       # ITB misses
system.cpu.itb.fetch_acv                         1122                       # ITB acv
system.cpu.itb.fetch_accesses                 1376947                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                        124800831                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 14048431                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           11726244                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect             450741                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              10120037                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                  5916610                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                   938783                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect               45408                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           31451408                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       71430724                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    14048431                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            6855393                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      13459712                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 2155244                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               43163669                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                32124                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        276321                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       306226                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          194                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8835796                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                303984                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           90109445                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.792711                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.123252                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 76649733     85.06%     85.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                   882120      0.98%     86.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1758761      1.95%     87.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   855148      0.95%     88.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2774809      3.08%     92.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                   597111      0.66%     92.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   671452      0.75%     93.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1010353      1.12%     94.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  4909958      5.45%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             90109445                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.112567                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.572358                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 32486072                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              42966960                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  12232972                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1046401                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1377039                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved               612715                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 43176                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts               70146735                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                131924                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1377039                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 33631618                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                17301504                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       21458473                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  11517889                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               4822920                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               66414787                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  7289                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 750703                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               1791896                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands            44375645                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups              80516952                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups         80027527                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            489425                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              38131021                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  6244616                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1698641                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         251106                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12735763                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             10548926                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             6961519                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1298320                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           905557                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   58829539                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2094293                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  57137234                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            128634                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         7593303                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined      3942261                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved        1428853                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      90109445                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.634087                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.284474                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            64286768     71.34%     71.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            11995743     13.31%     84.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             5355125      5.94%     90.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             3438365      3.82%     94.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2611846      2.90%     97.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             1326020      1.47%     98.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6              685055      0.76%     99.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              355852      0.39%     99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8               54671      0.06%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        90109445                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   75508      9.96%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.96% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 363265     47.93%     57.90% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                319103     42.10%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              7291      0.01%      0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              38991069     68.24%     68.25% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                61859      0.11%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd               25608      0.04%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.41% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             10392240     18.19%     86.60% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             6705676     11.74%     98.34% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess             949855      1.66%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               57137234                       # Type of FU issued
system.cpu.iq.rate                           0.457827                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                      757876                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.013264                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          204573341                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes          68190814                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     55847999                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads              697081                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             339930                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       327759                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               57523312                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  364507                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           597966                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1464590                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         2710                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        13959                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       585881                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        18028                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        111488                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1377039                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                12355921                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                868580                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            64490760                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            689025                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              10548926                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              6961519                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1842879                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 620807                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 12564                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          13959                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         241262                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       422502                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               663764                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              56606739                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              10022317                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            530494                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       3566928                       # number of nop insts executed
system.cpu.iew.exec_refs                     16674247                       # number of memory reference insts executed
system.cpu.iew.exec_branches                  8979744                       # Number of branches executed
system.cpu.iew.exec_stores                    6651930                       # Number of stores executed
system.cpu.iew.exec_rate                     0.453577                       # Inst execution rate
system.cpu.iew.wb_sent                       56287349                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      56175758                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  27690548                       # num instructions producing a value
system.cpu.iew.wb_consumers                  37534692                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.450123                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.737732                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts         8267625                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls          665440                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            619184                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     88732406                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.632394                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.547937                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     67542246     76.12%     76.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      8923750     10.06%     86.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4811841      5.42%     91.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2594320      2.92%     94.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1447946      1.63%     96.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       597901      0.67%     96.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       519027      0.58%     97.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       475014      0.54%     97.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      1820361      2.05%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     88732406                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             56113829                       # Number of instructions committed
system.cpu.commit.committedOps               56113829                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       15459974                       # Number of memory references committed
system.cpu.commit.loads                       9084336                       # Number of loads committed
system.cpu.commit.membars                      226495                       # Number of memory barriers committed
system.cpu.commit.branches                    8440914                       # Number of branches committed
system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  51962143                       # Number of committed integer instructions.
system.cpu.commit.function_calls               739769                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               1820361                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    151043798                       # The number of ROB reads
system.cpu.rob.rob_writes                   130140767                       # The number of ROB writes
system.cpu.timesIdled                         1385278                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        34691386                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   3609940555                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    52926469                       # Number of Instructions Simulated
system.cpu.committedOps                      52926469                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              52926469                       # Number of Instructions Simulated
system.cpu.cpi                               2.358004                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.358004                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.424087                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.424087                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                 74197467                       # number of integer regfile reads
system.cpu.int_regfile_writes                40518410                       # number of integer regfile writes
system.cpu.fp_regfile_reads                    166390                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   166940                       # number of floating regfile writes
system.cpu.misc_regfile_reads                 1995246                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 947641                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu.icache.replacements                1022327                       # number of replacements
system.cpu.icache.tagsinuse                509.956829                       # Cycle average of tags in use
system.cpu.icache.total_refs                  7752117                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1022838                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   7.579027                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            23896694000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     509.956829                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.996009                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.996009                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      7752118                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7752118                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7752118                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7752118                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7752118                       # number of overall hits
system.cpu.icache.overall_hits::total         7752118                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1083676                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1083676                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1083676                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1083676                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1083676                       # number of overall misses
system.cpu.icache.overall_misses::total       1083676                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  17473525489                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  17473525489                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  17473525489                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  17473525489                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  17473525489                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  17473525489                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8835794                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8835794                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8835794                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8835794                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8835794                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8835794                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.122646                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.122646                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.122646                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.122646                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.122646                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.122646                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16124.307901                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16124.307901                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16124.307901                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16124.307901                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16124.307901                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16124.307901                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs      1701496                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               187                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs  9098.909091                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        60589                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        60589                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        60589                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        60589                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        60589                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        60589                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1023087                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1023087                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1023087                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1023087                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1023087                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1023087                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13469506496                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  13469506496                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13469506496                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  13469506496                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13469506496                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  13469506496                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.115789                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.115789                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.115789                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.115789                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.115789                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.115789                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13165.553365                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13165.553365                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13165.553365                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13165.553365                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13165.553365                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13165.553365                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1401959                       # number of replacements
system.cpu.dcache.tagsinuse                511.994863                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 11836105                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1402471                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                   8.439465                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               23767000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.994863                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999990                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999990                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data      7252868                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7252868                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      4173229                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4173229                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       190095                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       190095                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       219635                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       219635                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      11426097                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         11426097                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     11426097                       # number of overall hits
system.cpu.dcache.overall_hits::total        11426097                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1829534                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1829534                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1968037                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1968037                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        23402                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        23402                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3797571                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3797571                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3797571                       # number of overall misses
system.cpu.dcache.overall_misses::total       3797571                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  48866941000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  48866941000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  75341328877                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  75341328877                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    430627500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    430627500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       153500                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       153500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 124208269877                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 124208269877                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 124208269877                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 124208269877                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      9082402                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9082402                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6141266                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6141266                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       213497                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       213497                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       219640                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       219640                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15223668                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15223668                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15223668                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15223668                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.201437                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.201437                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.320461                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.320461                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.109613                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.109613                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000023                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000023                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.249452                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.249452                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.249452                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.249452                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26710.048023                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 26710.048023                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38282.475826                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38282.475826                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18401.311854                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18401.311854                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        30700                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        30700                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32707.293656                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 32707.293656                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32707.293656                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 32707.293656                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs    749837529                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       205000                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             72763                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               8                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 10305.203592                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets        25625                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       841020                       # number of writebacks
system.cpu.dcache.writebacks::total            841020                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       745266                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       745266                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1667773                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1667773                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5284                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         5284                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2413039                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2413039                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2413039                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2413039                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1084268                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1084268                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300264                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       300264                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        18118                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        18118                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1384532                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1384532                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1384532                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1384532                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  28231218500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  28231218500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9703849435                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   9703849435                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    271481500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    271481500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       138000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       138000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  37935067935                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  37935067935                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  37935067935                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  37935067935                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1425162500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1425162500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2002731998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2002731998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3427894498                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3427894498                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119381                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119381                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048893                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048893                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.084863                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.084863                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090946                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.090946                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090946                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.090946                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26037.122280                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26037.122280                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32317.725185                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32317.725185                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14984.076609                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14984.076609                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        27600                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        27600                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27399.199105                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27399.199105                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27399.199105                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27399.199105                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6432                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     211195                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74695     40.95%     40.95% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     137      0.08%     41.02% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1890      1.04%     42.06% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  105693     57.94%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               182415                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73328     49.32%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      137      0.09%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1890      1.27%     50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73331     49.32%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                148686                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1826702082500     97.82%     97.82% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                72077500      0.00%     97.83% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               572984500      0.03%     97.86% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             40025844000      2.14%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1867372988500                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981699                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.693811                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.815097                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4176      2.17%      2.18% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl                175272     91.22%     93.43% # number of callpals executed
system.cpu.kern.callpal::rdps                    6795      3.54%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rti                     5118      2.66%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 192141                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5852                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2108                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1908                      
system.cpu.kern.mode_good::user                  1738                      
system.cpu.kern.mode_good::idle                   170                      
system.cpu.kern.mode_switch_good::kernel     0.326042                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.080645                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.393483                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        29935560000      1.60%      1.60% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           2782423500      0.15%      1.75% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1834654997000     98.25%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------