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|
---------- Begin Simulation Statistics ----------
sim_seconds 1.854316 # Number of seconds simulated
sim_ticks 1854315535000 # Number of ticks simulated
final_tick 1854315535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 136218 # Simulator instruction rate (inst/s)
host_op_rate 136218 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4770234092 # Simulator tick rate (ticks/s)
host_mem_usage 308432 # Number of bytes of host memory used
host_seconds 388.73 # Real time elapsed on the host
sim_insts 52951550 # Number of instructions simulated
sim_ops 52951550 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 963520 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24877248 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
system.physmem.bytes_read::total 28493120 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 963520 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 963520 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7502080 # Number of bytes written to this memory
system.physmem.bytes_written::total 7502080 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 15055 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 388707 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
system.physmem.num_reads::total 445205 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 117220 # Number of write requests responded to by this memory
system.physmem.num_writes::total 117220 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 519610 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 13415866 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1430367 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15365842 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 519610 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 519610 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4045741 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4045741 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4045741 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 519610 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 13415866 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1430367 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 19411583 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 445205 # Total number of read requests seen
system.physmem.writeReqs 117220 # Total number of write requests seen
system.physmem.cpureqs 562608 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 28493120 # Total number of bytes read from memory
system.physmem.bytesWritten 7502080 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 28493120 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7502080 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 28016 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 27755 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 27572 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 27335 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 27903 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 27978 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 27988 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 27793 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 28085 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 27815 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 27957 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 27734 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 27759 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 27962 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 27777 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 27720 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 7553 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 7293 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 7144 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 6986 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 7373 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 7381 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 7449 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 7333 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7646 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 7356 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 7497 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 7211 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 7256 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 7369 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 7178 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 7195 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry
system.physmem.totGap 1854310136000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 445205 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 117220 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 323472 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 64407 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 19558 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 7533 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3163 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2976 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2727 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2719 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 2651 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2584 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1520 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1449 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1411 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1379 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1373 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1392 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1605 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1469 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 938 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 792 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 19 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 2939 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 3695 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4126 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4204 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4741 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5067 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5083 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5086 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5088 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5097 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5097 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5097 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 5096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 5096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 5096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 5096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 5096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 2158 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 1402 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 971 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 893 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 356 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see
system.physmem.totQLat 7478299000 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 15194295250 # Sum of mem lat for all requests
system.physmem.totBusLat 2225745000 # Total cycles spent in databus access
system.physmem.totBankLat 5490251250 # Total cycles spent in bank access
system.physmem.avgQLat 16799.54 # Average queueing delay per request
system.physmem.avgBankLat 12333.51 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 34133.05 # Average memory access latency
system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
system.physmem.avgWrQLen 7.57 # Average write queue length over time
system.physmem.readRowHits 417721 # Number of row buffer hits during reads
system.physmem.writeRowHits 91342 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 77.92 # Row buffer hit rate for writes
system.physmem.avgGap 3296990.95 # Average gap between requests
system.iocache.replacements 41685 # number of replacements
system.iocache.tagsinuse 1.265062 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 1704476481000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 1.265062 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 10641558911 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10641558911 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 10662486909 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10662486909 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 10662486909 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10662486909 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256102.207138 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 256102.207138 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 255541.927118 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 255541.927118 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 255541.927118 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 255541.927118 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 285704 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 27220 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10.496106 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8479547437 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 8479547437 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 8491478686 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8491478686 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 8491478686 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8491478686 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204070.741168 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 204070.741168 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203510.573661 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 203510.573661 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203510.573661 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 203510.573661 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu.branchPred.lookups 13835452 # Number of BP lookups
system.cpu.branchPred.condPredicted 11604498 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 397875 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9360236 # Number of BTB lookups
system.cpu.branchPred.BTBHits 5805061 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 62.018319 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 907052 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 38979 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 9913942 # DTB read hits
system.cpu.dtb.read_misses 41971 # DTB read misses
system.cpu.dtb.read_acv 559 # DTB read access violations
system.cpu.dtb.read_accesses 941163 # DTB read accesses
system.cpu.dtb.write_hits 6591840 # DTB write hits
system.cpu.dtb.write_misses 10659 # DTB write misses
system.cpu.dtb.write_acv 411 # DTB write access violations
system.cpu.dtb.write_accesses 337869 # DTB write accesses
system.cpu.dtb.data_hits 16505782 # DTB hits
system.cpu.dtb.data_misses 52630 # DTB misses
system.cpu.dtb.data_acv 970 # DTB access violations
system.cpu.dtb.data_accesses 1279032 # DTB accesses
system.cpu.itb.fetch_hits 1304387 # ITB hits
system.cpu.itb.fetch_misses 38101 # ITB misses
system.cpu.itb.fetch_acv 1094 # ITB acv
system.cpu.itb.fetch_accesses 1342488 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.numCycles 108709176 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 28075681 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 70625770 # Number of instructions fetch has processed
system.cpu.fetch.Branches 13835452 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 6712113 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 13231336 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1982002 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 37359508 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 32821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 254255 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 361301 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 440 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 8540739 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 263307 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 80598838 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.876263 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.220111 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 67367502 83.58% 83.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 852306 1.06% 84.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1694888 2.10% 86.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 821828 1.02% 87.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2746821 3.41% 91.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 564765 0.70% 91.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 643702 0.80% 92.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1011325 1.25% 93.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 4895701 6.07% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 80598838 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.127270 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.649676 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 29246161 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 37051175 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 12098296 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 961855 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1241350 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 583461 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 42570 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 69332672 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 129212 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1241350 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 30366961 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 13601503 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 19800886 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 11334089 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4254047 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 65583694 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 7011 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 505967 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 1480663 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 43793573 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 79610392 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 79131107 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 479285 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 38157493 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 5636072 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1682036 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 239674 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12118674 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 10434139 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 6898397 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1310169 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 877649 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 58153519 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2049469 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 56771792 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 109314 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 6892902 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3544978 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1388546 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 80598838 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.704375 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.365163 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 55952160 69.42% 69.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 10819456 13.42% 82.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 5161521 6.40% 89.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 3379007 4.19% 93.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 2642777 3.28% 96.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 1459621 1.81% 98.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 760708 0.94% 99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 329892 0.41% 99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 93696 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 80598838 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 91294 11.60% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 373063 47.40% 59.00% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 322658 41.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 38708062 68.18% 68.19% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 61690 0.11% 68.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 10346391 18.22% 86.58% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 6670119 11.75% 98.33% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 949001 1.67% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 56771792 # Type of FU issued
system.cpu.iq.rate 0.522236 # Inst issue rate
system.cpu.iq.fu_busy_cnt 787015 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.013863 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 194345553 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 66772978 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 55538078 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 693197 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 336730 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 327888 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 57189578 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 361943 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 597316 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1346178 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3275 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 14144 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 522891 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 17954 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 174426 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1241350 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 9930800 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 684897 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 63726259 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 676325 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 10434139 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 6898397 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1805166 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 512910 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 18627 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 14144 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 201347 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 411340 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 612687 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 56305820 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 9984116 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 465971 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 3523271 # number of nop insts executed
system.cpu.iew.exec_refs 16601850 # number of memory reference insts executed
system.cpu.iew.exec_branches 8919814 # Number of branches executed
system.cpu.iew.exec_stores 6617734 # Number of stores executed
system.cpu.iew.exec_rate 0.517949 # Inst execution rate
system.cpu.iew.wb_sent 55981553 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 55865966 # cumulative count of insts written-back
system.cpu.iew.wb_producers 27748179 # num instructions producing a value
system.cpu.iew.wb_consumers 37603022 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.513903 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.737924 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 7467988 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 660923 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 566730 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 79357488 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.707446 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.635929 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 58581738 73.82% 73.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 8607533 10.85% 84.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4610804 5.81% 90.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2534837 3.19% 93.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1515398 1.91% 95.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 609514 0.77% 96.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 522093 0.66% 97.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 538800 0.68% 97.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1836771 2.31% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 79357488 # Number of insts commited each cycle
system.cpu.commit.committedInsts 56141140 # Number of instructions committed
system.cpu.commit.committedOps 56141140 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 15463467 # Number of memory references committed
system.cpu.commit.loads 9087961 # Number of loads committed
system.cpu.commit.membars 226334 # Number of memory barriers committed
system.cpu.commit.branches 8436593 # Number of branches committed
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
system.cpu.commit.int_insts 51992006 # Number of committed integer instructions.
system.cpu.commit.function_calls 740231 # Number of function calls committed.
system.cpu.commit.bw_lim_events 1836771 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 140880188 # The number of ROB reads
system.cpu.rob.rob_writes 128461324 # The number of ROB writes
system.cpu.timesIdled 1178621 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 28110338 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 3599915455 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 52951550 # Number of Instructions Simulated
system.cpu.committedOps 52951550 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 52951550 # Number of Instructions Simulated
system.cpu.cpi 2.052993 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.052993 # CPI: Total CPI of All Threads
system.cpu.ipc 0.487094 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.487094 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 73826909 # number of integer regfile reads
system.cpu.int_regfile_writes 40289801 # number of integer regfile writes
system.cpu.fp_regfile_reads 166028 # number of floating regfile reads
system.cpu.fp_regfile_writes 167439 # number of floating regfile writes
system.cpu.misc_regfile_reads 1985478 # number of misc regfile reads
system.cpu.misc_regfile_writes 938924 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu.icache.replacements 1007426 # number of replacements
system.cpu.icache.tagsinuse 510.288426 # Cycle average of tags in use
system.cpu.icache.total_refs 7476565 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1007934 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 7.417713 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 20275724000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.288426 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996657 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996657 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 7476566 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 7476566 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 7476566 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 7476566 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 7476566 # number of overall hits
system.cpu.icache.overall_hits::total 7476566 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1064170 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1064170 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1064170 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1064170 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1064170 # number of overall misses
system.cpu.icache.overall_misses::total 1064170 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14673680991 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 14673680991 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 14673680991 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 14673680991 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 14673680991 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 14673680991 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 8540736 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 8540736 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 8540736 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 8540736 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 8540736 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 8540736 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124599 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.124599 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.124599 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.124599 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.124599 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.124599 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13788.850457 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13788.850457 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13788.850457 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13788.850457 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13788.850457 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13788.850457 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 6348 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 862 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 199 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 31.899497 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 862 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56016 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 56016 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 56016 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 56016 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 56016 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 56016 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1008154 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1008154 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1008154 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1008154 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1008154 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1008154 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12024926992 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 12024926992 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12024926992 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 12024926992 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12024926992 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12024926992 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118041 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118041 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118041 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.118041 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118041 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.118041 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11927.668781 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11927.668781 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11927.668781 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11927.668781 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11927.668781 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11927.668781 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 338281 # number of replacements
system.cpu.l2cache.tagsinuse 65363.167124 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2542180 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 403447 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 6.301150 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 4078120751 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 54044.575759 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 5331.978282 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 5986.613083 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.824655 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.081360 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.091348 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.997363 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 992978 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 826117 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1819095 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 840025 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 840025 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 185422 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 185422 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 992978 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1011539 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2004517 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 992978 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1011539 # number of overall hits
system.cpu.l2cache.overall_hits::total 2004517 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 15057 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 273790 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 288847 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 39 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 39 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 115410 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 115410 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 15057 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 389200 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 404257 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 15057 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 389200 # number of overall misses
system.cpu.l2cache.overall_misses::total 404257 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1043831000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11949641000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 12993472000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 297500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 297500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7647089000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 7647089000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 1043831000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 19596730000 # number of overall miss cycles
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system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7628.205128 # average UpgradeReq miss latency
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.writebacks::total 75708 # number of writebacks
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277853 # mshr miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31407.312203 # average ReadReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14206.025641 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56860.023379 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38119.936673 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1400143 # number of replacements
system.cpu.dcache.tagsinuse 511.995158 # Cycle average of tags in use
system.cpu.dcache.total_refs 11810847 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1400655 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 8.432374 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 21808000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.995158 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy
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system.cpu.dcache.LoadLockedReq_misses::total 22724 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_miss_latency::total 307808500 # number of LoadLockedReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate::total 0.315886 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108895 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108895 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.StoreCondReq_miss_rate::total 0.000023 # miss rate for StoreCondReq accesses
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system.cpu.dcache.overall_miss_rate::total 0.246981 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18816.932059 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 18816.932059 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33465.791477 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33465.791477 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13545.524556 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13545.524556 # average LoadLockedReq miss latency
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system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15300 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26416.083568 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26416.083568 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26416.083568 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26416.083568 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 2179418 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1081 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 95907 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.724285 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 154.428571 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 840025 # number of writebacks
system.cpu.dcache.writebacks::total 840025 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717752 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 717752 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1640976 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1640976 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5261 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5261 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2358728 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2358728 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 2358728 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083104 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1083104 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300236 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 300236 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17463 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17463 # number of LoadLockedReq MSHR misses
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system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1383340 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1383340 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1383340 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1383340 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21322279500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21322279500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9864847262 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9864847262 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200761000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200761000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 66500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 66500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31187126762 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 31187126762 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31187126762 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 31187126762 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423835500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423835500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997377498 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997377498 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421212998 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421212998 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120266 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120266 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048856 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048856 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083684 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083684 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000023 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091302 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.091302 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091302 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.091302 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19686.271586 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19686.271586 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32856.976718 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32856.976718 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11496.363740 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11496.363740 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13300 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13300 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22544.802263 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22544.802263 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22544.802263 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22544.802263 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed
system.cpu.kern.inst.hwrei 211001 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74662 40.97% 40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 105560 57.93% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 182232 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73295 49.32% 49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73295 49.32% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 148600 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1818327594000 98.06% 98.06% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 63775000 0.00% 98.06% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 558444000 0.03% 98.09% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 35364889500 1.91% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1854314702500 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31 0.694344 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.815444 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl 175117 91.23% 93.43% # number of callpals executed
system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.callpal::total 191961 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches
system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1909
system.cpu.kern.mode_good::user 1739
system.cpu.kern.mode_good::idle 170
system.cpu.kern.mode_switch_good::kernel 0.326381 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.394218 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 29464996000 1.59% 1.59% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 2711269000 0.15% 1.74% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1822138429500 98.26% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
---------- End Simulation Statistics ----------
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