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|
---------- Begin Simulation Statistics ----------
sim_seconds 1.859049 # Number of seconds simulated
sim_ticks 1859049148500 # Number of ticks simulated
final_tick 1859049148500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 168870 # Simulator instruction rate (inst/s)
host_op_rate 168870 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5931192571 # Simulator tick rate (ticks/s)
host_mem_usage 320216 # Number of bytes of host memory used
host_seconds 313.44 # Real time elapsed on the host
sim_insts 52930035 # Number of instructions simulated
sim_ops 52930035 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24875776 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 25843904 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 967168 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 967168 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7516224 # Number of bytes written to this memory
system.physmem.bytes_written::total 7516224 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 15112 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 388684 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 403811 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 117441 # Number of write requests responded to by this memory
system.physmem.num_writes::total 117441 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 520249 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 13380914 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13901679 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 520249 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 520249 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4043047 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4043047 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4043047 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 520249 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 13380914 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 17944726 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 403811 # Number of read requests accepted
system.physmem.writeReqs 158993 # Number of write requests accepted
system.physmem.readBursts 403811 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 158993 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 25836928 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue
system.physmem.bytesWritten 10037376 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 25843904 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 10175552 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2130 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 189 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 25744 # Per bank write bursts
system.physmem.perBankRdBursts::1 25560 # Per bank write bursts
system.physmem.perBankRdBursts::2 25512 # Per bank write bursts
system.physmem.perBankRdBursts::3 25342 # Per bank write bursts
system.physmem.perBankRdBursts::4 25388 # Per bank write bursts
system.physmem.perBankRdBursts::5 24802 # Per bank write bursts
system.physmem.perBankRdBursts::6 25022 # Per bank write bursts
system.physmem.perBankRdBursts::7 25128 # Per bank write bursts
system.physmem.perBankRdBursts::8 24929 # Per bank write bursts
system.physmem.perBankRdBursts::9 25033 # Per bank write bursts
system.physmem.perBankRdBursts::10 25435 # Per bank write bursts
system.physmem.perBankRdBursts::11 24778 # Per bank write bursts
system.physmem.perBankRdBursts::12 24542 # Per bank write bursts
system.physmem.perBankRdBursts::13 25239 # Per bank write bursts
system.physmem.perBankRdBursts::14 25649 # Per bank write bursts
system.physmem.perBankRdBursts::15 25599 # Per bank write bursts
system.physmem.perBankWrBursts::0 10531 # Per bank write bursts
system.physmem.perBankWrBursts::1 10049 # Per bank write bursts
system.physmem.perBankWrBursts::2 10576 # Per bank write bursts
system.physmem.perBankWrBursts::3 9740 # Per bank write bursts
system.physmem.perBankWrBursts::4 9614 # Per bank write bursts
system.physmem.perBankWrBursts::5 9115 # Per bank write bursts
system.physmem.perBankWrBursts::6 9087 # Per bank write bursts
system.physmem.perBankWrBursts::7 8933 # Per bank write bursts
system.physmem.perBankWrBursts::8 9694 # Per bank write bursts
system.physmem.perBankWrBursts::9 8895 # Per bank write bursts
system.physmem.perBankWrBursts::10 9699 # Per bank write bursts
system.physmem.perBankWrBursts::11 9449 # Per bank write bursts
system.physmem.perBankWrBursts::12 10004 # Per bank write bursts
system.physmem.perBankWrBursts::13 10709 # Per bank write bursts
system.physmem.perBankWrBursts::14 10413 # Per bank write bursts
system.physmem.perBankWrBursts::15 10326 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
system.physmem.totGap 1859043836000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 403811 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 158993 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 314947 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 37560 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 42912 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 8209 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 57 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1967 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3979 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5517 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 7478 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 9204 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 10713 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 11173 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 12066 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 11628 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 11816 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 10845 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 10205 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 9101 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 9155 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7171 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6920 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6788 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6319 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 496 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 430 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 385 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 365 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 338 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 283 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 237 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 252 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 220 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 203 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 156 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 82 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 63789 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 562.390130 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 348.747922 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 419.715872 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 13502 21.17% 21.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 10319 16.18% 37.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4795 7.52% 44.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2857 4.48% 49.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2332 3.66% 53.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1655 2.59% 55.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1501 2.35% 57.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1587 2.49% 60.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 25241 39.57% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 63789 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5661 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 71.309309 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2806.420357 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191 5658 99.95% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5661 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5661 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 27.704293 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 20.909682 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 34.456612 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 4621 81.63% 81.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 191 3.37% 85.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 281 4.96% 89.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 54 0.95% 90.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 96 1.70% 92.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 48 0.85% 93.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71 17 0.30% 93.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 14 0.25% 94.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 19 0.34% 94.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95 5 0.09% 94.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 15 0.26% 94.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111 4 0.07% 94.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 5 0.09% 94.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127 2 0.04% 94.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 19 0.34% 95.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 42 0.74% 95.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151 21 0.37% 96.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159 11 0.19% 96.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167 96 1.70% 98.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175 35 0.62% 98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 14 0.25% 99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191 13 0.23% 99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199 10 0.18% 99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207 5 0.09% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215 5 0.09% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223 2 0.04% 99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231 5 0.09% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239 6 0.11% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247 2 0.04% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5661 # Writes before turning the bus around for reads
system.physmem.totQLat 3666880250 # Total ticks spent queuing
system.physmem.totMemAccLat 11236292750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2018510000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9083.14 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 27833.14 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 5.40 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.90 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 5.47 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing
system.physmem.readRowHits 364667 # Number of row buffer hits during reads
system.physmem.writeRowHits 132080 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.33 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 84.20 # Row buffer hit rate for writes
system.physmem.avgGap 3303181.63 # Average gap between requests
system.physmem.pageHitRate 88.62 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 1760890123500 # Time in different power states
system.physmem.memoryStateTime::REF 62077600000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 36077600250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem.actEnergy::0 239795640 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 242449200 # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0 130840875 # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1 132288750 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 1579484400 # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1 1569391200 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 503139600 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 513144720 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 121423785600 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 121423785600 # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0 55719498420 # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1 55486362150 # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0 1066550433000 # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1 1066754938500 # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0 1246146977535 # Total energy per rank (pJ)
system.physmem.totalEnergy::1 1246122360120 # Total energy per rank (pJ)
system.physmem.averagePower::0 670.315549 # Core power per rank (mW)
system.physmem.averagePower::1 670.302307 # Core power per rank (mW)
system.cpu.branchPred.lookups 17761302 # Number of BP lookups
system.cpu.branchPred.condPredicted 15456576 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 379954 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 12009119 # Number of BTB lookups
system.cpu.branchPred.BTBHits 5937139 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 49.438589 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 914399 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 21305 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 10308188 # DTB read hits
system.cpu.dtb.read_misses 41379 # DTB read misses
system.cpu.dtb.read_acv 521 # DTB read access violations
system.cpu.dtb.read_accesses 967155 # DTB read accesses
system.cpu.dtb.write_hits 6646702 # DTB write hits
system.cpu.dtb.write_misses 9325 # DTB write misses
system.cpu.dtb.write_acv 410 # DTB write access violations
system.cpu.dtb.write_accesses 342603 # DTB write accesses
system.cpu.dtb.data_hits 16954890 # DTB hits
system.cpu.dtb.data_misses 50704 # DTB misses
system.cpu.dtb.data_acv 931 # DTB access violations
system.cpu.dtb.data_accesses 1309758 # DTB accesses
system.cpu.itb.fetch_hits 1770443 # ITB hits
system.cpu.itb.fetch_misses 36092 # ITB misses
system.cpu.itb.fetch_acv 664 # ITB acv
system.cpu.itb.fetch_accesses 1806535 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.numCycles 118298016 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 29541198 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 78055768 # Number of instructions fetch has processed
system.cpu.fetch.Branches 17761302 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 6851538 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 80476428 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1253224 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 1384 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 28562 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1737629 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 451562 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 217 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 9019799 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 273133 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 112863592 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.691594 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.010851 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 98289284 87.09% 87.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 935566 0.83% 87.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1976201 1.75% 89.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 911928 0.81% 90.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2795335 2.48% 92.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 642698 0.57% 93.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 727750 0.64% 94.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1007954 0.89% 95.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 5576876 4.94% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 112863592 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.150140 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.659823 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 24058379 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 76821722 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 9496623 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1902660 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 584207 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 588094 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 42817 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 68303161 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 133250 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 584207 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 24982800 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 47259981 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 20734687 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 10387203 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 8914712 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 65869472 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 202922 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2041149 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 141248 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 4766165 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 43946104 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 79818079 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 79637315 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 168311 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 38139253 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 5806843 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1691151 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 241440 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13536828 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 10424364 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 6928356 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1483959 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1059889 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 58630025 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2138995 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 57603342 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 50950 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 7503583 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3485287 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1477804 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 112863592 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.510380 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.252962 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 89383207 79.20% 79.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 10013548 8.87% 88.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 4301377 3.81% 91.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 2962557 2.62% 94.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 3086274 2.73% 97.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 1586017 1.41% 98.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1012124 0.90% 99.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 396460 0.35% 99.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 122028 0.11% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 112863592 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 213045 18.77% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 547519 48.24% 67.01% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 374446 32.99% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 39102059 67.88% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 61815 0.11% 68.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 38377 0.07% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.07% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 10718615 18.61% 86.68% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 6722522 11.67% 98.35% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 949032 1.65% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 57603342 # Type of FU issued
system.cpu.iq.rate 0.486934 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1135010 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.019704 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 228544022 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 67957775 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 55921178 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 712213 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 334464 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 328973 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 58348779 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 382287 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 639736 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1339690 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 4038 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 20047 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 554552 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 18285 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 544771 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 584207 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 44318330 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 613096 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 64473181 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 145267 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 10424364 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 6928356 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1890724 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 42751 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 366947 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 20047 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 190952 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 410451 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 601403 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 57018878 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 10377294 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 584463 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 3704161 # number of nop insts executed
system.cpu.iew.exec_refs 17048455 # number of memory reference insts executed
system.cpu.iew.exec_branches 8982580 # Number of branches executed
system.cpu.iew.exec_stores 6671161 # Number of stores executed
system.cpu.iew.exec_rate 0.481994 # Inst execution rate
system.cpu.iew.wb_sent 56384919 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 56250151 # cumulative count of insts written-back
system.cpu.iew.wb_producers 28947314 # num instructions producing a value
system.cpu.iew.wb_consumers 40326252 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.475495 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.717828 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 8239076 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 661191 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 548552 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 111427799 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.503633 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.455266 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 91796177 82.38% 82.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 7808087 7.01% 89.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4129534 3.71% 93.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2155296 1.93% 95.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1855711 1.67% 96.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 615462 0.55% 97.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 470761 0.42% 97.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 513166 0.46% 98.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 2083605 1.87% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 111427799 # Number of insts commited each cycle
system.cpu.commit.committedInsts 56118765 # Number of instructions committed
system.cpu.commit.committedOps 56118765 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 15458478 # Number of memory references committed
system.cpu.commit.loads 9084674 # Number of loads committed
system.cpu.commit.membars 226351 # Number of memory barriers committed
system.cpu.commit.branches 8434924 # Number of branches committed
system.cpu.commit.fp_insts 324518 # Number of committed floating point instructions.
system.cpu.commit.int_insts 51970227 # Number of committed integer instructions.
system.cpu.commit.function_calls 739937 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 3196003 5.70% 5.70% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 36180557 64.47% 70.17% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 60666 0.11% 70.27% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 38089 0.07% 70.34% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 9311025 16.59% 86.94% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 6379757 11.37% 98.31% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 949032 1.69% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 56118765 # Class of committed instruction
system.cpu.commit.bw_lim_events 2083605 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 173452486 # The number of ROB reads
system.cpu.rob.rob_writes 130147702 # The number of ROB writes
system.cpu.timesIdled 575947 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 5434424 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 3599800282 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 52930035 # Number of Instructions Simulated
system.cpu.committedOps 52930035 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 2.234988 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.234988 # CPI: Total CPI of All Threads
system.cpu.ipc 0.447430 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.447430 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 74659793 # number of integer regfile reads
system.cpu.int_regfile_writes 40587610 # number of integer regfile writes
system.cpu.fp_regfile_reads 166949 # number of floating regfile reads
system.cpu.fp_regfile_writes 167607 # number of floating regfile writes
system.cpu.misc_regfile_reads 2029497 # number of misc regfile reads
system.cpu.misc_regfile_writes 939434 # number of misc regfile writes
system.cpu.dcache.tags.replacements 1404580 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.994645 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 11874772 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1405092 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 8.451242 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.994645 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 413 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 63937777 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 63937777 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 7284414 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7284414 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4188003 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4188003 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 186359 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 186359 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 215726 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 215726 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 11472417 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 11472417 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 11472417 # number of overall hits
system.cpu.dcache.overall_hits::total 11472417 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1780024 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1780024 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1955346 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1955346 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 23271 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 23271 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 3735370 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3735370 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3735370 # number of overall misses
system.cpu.dcache.overall_misses::total 3735370 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 39520730746 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 39520730746 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 78084026192 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 78084026192 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 364876749 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 364876749 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 441006 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 441006 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 117604756938 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 117604756938 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 117604756938 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 117604756938 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 9064438 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9064438 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6143349 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6143349 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209630 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 209630 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 215754 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 215754 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 15207787 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 15207787 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 15207787 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15207787 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196374 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.196374 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318287 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.318287 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111010 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111010 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.245622 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.245622 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.245622 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.245622 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22202.358365 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 22202.358365 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39933.610825 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39933.610825 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15679.461519 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15679.461519 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15750.214286 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15750.214286 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31484.098480 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31484.098480 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31484.098480 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31484.098480 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 3992388 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1705 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 180260 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 24 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.147942 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 71.041667 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 842675 # number of writebacks
system.cpu.dcache.writebacks::total 842675 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 683874 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 683874 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664228 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1664228 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5276 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5276 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2348102 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2348102 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2348102 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2348102 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1096150 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1096150 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291118 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 291118 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17995 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17995 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1387268 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1387268 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1387268 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1387268 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27519652282 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 27519652282 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11779193020 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11779193020 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204738251 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204738251 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 384994 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 384994 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39298845302 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 39298845302 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39298845302 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 39298845302 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423580000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423580000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999637498 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999637498 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423217498 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423217498 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120929 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120929 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047388 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047388 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085842 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085842 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.091221 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.091221 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25105.735786 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25105.735786 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40461.919290 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40461.919290 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11377.507697 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11377.507697 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13749.785714 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13749.785714 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28328.228794 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28328.228794 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28328.228794 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28328.228794 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1035530 # number of replacements
system.cpu.icache.tags.tagsinuse 509.402349 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 7932375 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1036038 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 7.656452 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 26422155250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 509.402349 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 10056088 # Number of tag accesses
system.cpu.icache.tags.data_accesses 10056088 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 7932376 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 7932376 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 7932376 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 7932376 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 7932376 # number of overall hits
system.cpu.icache.overall_hits::total 7932376 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1087421 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1087421 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1087421 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1087421 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1087421 # number of overall misses
system.cpu.icache.overall_misses::total 1087421 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15131971529 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15131971529 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15131971529 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15131971529 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15131971529 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15131971529 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 9019797 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 9019797 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 9019797 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 9019797 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 9019797 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 9019797 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120559 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.120559 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::total 0.120559 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.120559 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.120559 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13915.467449 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13915.467449 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13915.467449 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13915.467449 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13915.467449 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13915.467449 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 5307 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 26.142857 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51130 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 51130 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 51130 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 51130 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 51130 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 51130 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1036291 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1036291 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::total 1036291 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1036291 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1036291 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12436978135 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 12436978135 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12436978135 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 12436978135 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12436978135 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12436978135 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114891 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114891 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114891 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.114891 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114891 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.114891 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12001.434090 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12001.434090 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12001.434090 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12001.434090 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12001.434090 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12001.434090 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 338304 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65336.722890 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2576408 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 403470 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 6.385625 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 5538371750 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 53740.358806 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 5341.050861 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 6255.313222 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.820013 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081498 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.095449 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 494 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3497 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3329 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2414 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55432 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 26978409 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 26978409 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 1021005 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 829436 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1850441 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 842675 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 842675 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 32 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 32 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 186561 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 186561 # number of ReadExReq hits
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system.cpu.l2cache.demand_hits::cpu.data 1015997 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2037002 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.data 1015997 # number of overall hits
system.cpu.l2cache.overall_hits::total 2037002 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.data 273817 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 288931 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 47 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 47 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 6 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 115372 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 115372 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 15114 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 389189 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 404303 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 15114 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 389189 # number of overall misses
system.cpu.l2cache.overall_misses::total 404303 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1159992750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17995310250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 19155303000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 355494 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 355494 # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 92496 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 92496 # number of SCUpgradeReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 9679121611 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 1159992750 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 1159992750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 27674431861 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 28834424611 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1036119 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1103253 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2139372 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 842675 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 842675 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 79 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 28 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 301933 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 301933 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1036119 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1405186 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2441305 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1036119 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1405186 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2441305 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014587 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248191 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.135054 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.594937 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.594937 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382111 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.382111 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014587 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.276966 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.165609 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014587 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.276966 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.165609 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76749.553394 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65720.208205 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66297.153992 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7563.702128 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7563.702128 # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 15416 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 15416 # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83894.893137 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83894.893137 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76749.553394 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71107.949765 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71318.849009 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76749.553394 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71107.949765 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71318.849009 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 75929 # number of writebacks
system.cpu.l2cache.writebacks::total 75929 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15113 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273817 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 288930 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 47 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 47 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 6 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115372 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 115372 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15113 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 389189 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 404302 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15113 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 389189 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 404302 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 969372000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14584664250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15554036250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 622542 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 622542 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 60006 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 60006 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8273073889 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8273073889 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 969372000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22857738139 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 23827110139 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 969372000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22857738139 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 23827110139 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333490000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333490000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884459000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884459000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3217949000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3217949000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014586 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248191 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135054 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.594937 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.594937 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382111 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382111 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014586 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276966 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.165609 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014586 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276966 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.165609 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64141.599947 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53264.275958 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53833.233828 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13245.574468 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13245.574468 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71707.813759 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71707.813759 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64141.599947 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58731.716824 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58933.940814 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64141.599947 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58731.716824 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58933.940814 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 2146647 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2146537 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 842675 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 107 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 301933 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 301933 # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError 93 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2072410 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3686471 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 5758881 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66311616 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143911276 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 210222892 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 42053 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 3325984 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.012545 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.111300 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 3284259 98.75% 98.75% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 41725 1.25% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 3325984 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2497867498 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1558461609 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2189866891 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
system.iobus.trans_dist::WriteReq 51149 # Transaction distribution
system.iobus.trans_dist::WriteResp 9597 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 33054 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 116504 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20200 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 44140 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2705748 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 4661000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 406221775 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 42010536 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41685 # number of replacements
system.iocache.tags.tagsinuse 1.260575 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 1709355371000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 1.260575 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.078786 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.078786 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
system.iocache.tags.data_accesses 375525 # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
system.iocache.overall_misses::total 173 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13648838856 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 13648838856 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles
system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328476.098768 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 328476.098768 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 206574 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 23538 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 8.776192 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11488062928 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11488062928 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276474.367732 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276474.367732 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 296033 # Transaction distribution
system.membus.trans_dist::ReadResp 295940 # Transaction distribution
system.membus.trans_dist::WriteReq 9597 # Transaction distribution
system.membus.trans_dist::WriteResp 9597 # Transaction distribution
system.membus.trans_dist::Writeback 117441 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
system.membus.trans_dist::UpgradeReq 186 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution
system.membus.trans_dist::UpgradeResp 192 # Transaction distribution
system.membus.trans_dist::ReadExReq 115233 # Transaction distribution
system.membus.trans_dist::ReadExResp 115233 # Transaction distribution
system.membus.trans_dist::BadAddressError 93 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884176 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 186 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917416 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1042220 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702400 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30746540 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 36063596 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 435 # Total snoops (count)
system.membus.snoop_fanout::samples 563522 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 563522 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 563522 # Request fanout histogram
system.membus.reqLayer0.occupancy 31470000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1857946999 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer2.occupancy 115000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 3754266813 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 43145464 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed
system.cpu.kern.inst.hwrei 211003 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74662 40.97% 40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 105561 57.93% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 182233 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73295 49.32% 49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73295 49.32% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 148600 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1817339213500 97.76% 97.76% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 61863500 0.00% 97.76% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 521835500 0.03% 97.79% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 41125418500 2.21% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1859048331000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31 0.694338 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.815440 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx 4178 2.18% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl 175118 91.22% 93.44% # number of callpals executed
system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.callpal::total 191963 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches
system.cpu.kern.mode_switch::user 1741 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1911
system.cpu.kern.mode_good::user 1741
system.cpu.kern.mode_good::idle 170
system.cpu.kern.mode_switch_good::kernel 0.326499 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.394468 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 29096339500 1.57% 1.57% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 2660038000 0.14% 1.71% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1827291945500 98.29% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4179 # number of times the context was actually changed
---------- End Simulation Statistics ----------
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