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|
---------- Begin Simulation Statistics ----------
sim_seconds 1.859851 # Number of seconds simulated
sim_ticks 1859850554500 # Number of ticks simulated
final_tick 1859850554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 188989 # Simulator instruction rate (inst/s)
host_op_rate 188989 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6621174751 # Simulator tick rate (ticks/s)
host_mem_usage 292896 # Number of bytes of host memory used
host_seconds 280.89 # Real time elapsed on the host
sim_insts 53085804 # Number of instructions simulated
sim_ops 53085804 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 29820864 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1064000 # Number of instructions bytes read from this memory
system.physmem.bytes_written 10193536 # Number of bytes written to this memory
system.physmem.num_reads 465951 # Number of read requests responded to by this memory
system.physmem.num_writes 159274 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 16034011 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 572089 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 5480836 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 21514847 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 391353 # number of replacements
system.l2c.tagsinuse 34925.820021 # Cycle average of tags in use
system.l2c.total_refs 2406767 # Total number of references to valid blocks.
system.l2c.sampled_refs 424249 # Sample count of references to valid blocks.
system.l2c.avg_refs 5.673006 # Average number of references to valid blocks.
system.l2c.warmup_cycle 5619831000 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 22620.354669 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst 4081.669847 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data 8223.795506 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.345159 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst 0.062281 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data 0.125485 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.532926 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.inst 988583 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data 812181 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1800764 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 835189 # number of Writeback hits
system.l2c.Writeback_hits::total 835189 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data 183241 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 183241 # number of ReadExReq hits
system.l2c.demand_hits::cpu.inst 988583 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data 995422 # number of demand (read+write) hits
system.l2c.demand_hits::total 1984005 # number of demand (read+write) hits
system.l2c.overall_hits::cpu.inst 988583 # number of overall hits
system.l2c.overall_hits::cpu.data 995422 # number of overall hits
system.l2c.overall_hits::total 1984005 # number of overall hits
system.l2c.ReadReq_misses::cpu.inst 16626 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data 291511 # number of ReadReq misses
system.l2c.ReadReq_misses::total 308137 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 35 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data 116889 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 116889 # number of ReadExReq misses
system.l2c.demand_misses::cpu.inst 16626 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data 408400 # number of demand (read+write) misses
system.l2c.demand_misses::total 425026 # number of demand (read+write) misses
system.l2c.overall_misses::cpu.inst 16626 # number of overall misses
system.l2c.overall_misses::cpu.data 408400 # number of overall misses
system.l2c.overall_misses::total 425026 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu.inst 869674000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.data 15168138500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 16037812500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu.data 424500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 424500 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu.data 6132457500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 6132457500 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu.inst 869674000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.data 21300596000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 22170270000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu.inst 869674000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.data 21300596000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 22170270000 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu.inst 1005209 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data 1103692 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2108901 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 835189 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 835189 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data 51 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 51 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data 300130 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 300130 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.inst 1005209 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data 1403822 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2409031 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.inst 1005209 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data 1403822 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2409031 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data 0.264124 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data 0.686275 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data 0.389461 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data 0.290920 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data 0.290920 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52308.071695 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 52032.816943 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 12128.571429 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52463.940148 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 52308.071695 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52156.209598 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 52308.071695 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52156.209598 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 117762 # number of writebacks
system.l2c.writebacks::total 117762 # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu.inst 16626 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.data 291511 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 308137 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu.data 116889 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 116889 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu.inst 16626 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.data 408400 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 425026 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu.inst 16626 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.data 408400 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 425026 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 666148500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.data 11667923000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 12334071500 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1460000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 1460000 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4711233500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 4711233500 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.inst 666148500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.data 16379156500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 17045305000 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.inst 666148500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.data 16379156500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 17045305000 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809589500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 809589500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114928998 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1114928998 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924518498 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 1924518498 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264124 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.686275 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389461 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data 0.290920 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data 0.290920 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.672681 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40025.669700 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41714.285714 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40305.191250 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40066.672681 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40105.672135 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40066.672681 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40105.672135 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 41685 # number of replacements
system.iocache.tagsinuse 1.276011 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 1708338781000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 1.276011 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.079751 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.079751 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 19937998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 19937998 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 5721891806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 5721891806 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 5741829804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 5741829804 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 5741829804 # number of overall miss cycles
system.iocache.overall_miss_latency::total 5741829804 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137704.365759 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 137611.259533 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 137611.259533 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 64612060 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 6168.215752 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10941998 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 10941998 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561041984 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 3561041984 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 3571983982 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 3571983982 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 3571983982 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 3571983982 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85700.856373 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85607.764697 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85607.764697 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 10136178 # DTB read hits
system.cpu.dtb.read_misses 46729 # DTB read misses
system.cpu.dtb.read_acv 584 # DTB read access violations
system.cpu.dtb.read_accesses 970980 # DTB read accesses
system.cpu.dtb.write_hits 6626287 # DTB write hits
system.cpu.dtb.write_misses 12218 # DTB write misses
system.cpu.dtb.write_acv 419 # DTB write access violations
system.cpu.dtb.write_accesses 347267 # DTB write accesses
system.cpu.dtb.data_hits 16762465 # DTB hits
system.cpu.dtb.data_misses 58947 # DTB misses
system.cpu.dtb.data_acv 1003 # DTB access violations
system.cpu.dtb.data_accesses 1318247 # DTB accesses
system.cpu.itb.fetch_hits 1326719 # ITB hits
system.cpu.itb.fetch_misses 39613 # ITB misses
system.cpu.itb.fetch_acv 1063 # ITB acv
system.cpu.itb.fetch_accesses 1366332 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.numCycles 116271514 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 14404381 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 12049368 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 531407 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 13004312 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 6709840 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 971693 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 45037 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 29087793 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 73522129 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14404381 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 7681533 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 14275065 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2363223 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 36625670 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 33401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 258943 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 335385 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 155 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 9051216 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 322280 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 82158877 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.894877 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.211744 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 67883812 82.63% 82.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1025449 1.25% 83.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2024221 2.46% 86.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 965546 1.18% 87.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2955118 3.60% 91.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 688428 0.84% 91.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 786197 0.96% 92.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1069042 1.30% 94.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 4761064 5.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 82158877 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.123886 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.632331 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 30342810 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 36285765 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 13055396 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 974232 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1500673 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 609120 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 42110 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 71910719 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 128198 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1500673 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 31545269 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 12820046 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 19759905 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 12205401 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4327581 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 67985937 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 6903 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 504868 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 1537776 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 45488593 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 82604485 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 82125154 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 479331 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 38256265 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 7232320 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1700161 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 251408 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12102195 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 10719689 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 6992362 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1255856 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 835149 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 59697251 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2115237 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 57966423 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 118182 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8327603 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 4293139 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1447692 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 82158877 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.705541 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.352283 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 56706238 69.02% 69.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 11186331 13.62% 82.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 5491014 6.68% 89.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 3497852 4.26% 93.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 2643618 3.22% 96.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 1562284 1.90% 98.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 690020 0.84% 99.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 273664 0.33% 99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 107856 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 82158877 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 66675 8.67% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.67% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 379311 49.30% 57.96% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 323479 42.04% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 39589342 68.30% 68.31% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 62143 0.11% 68.42% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.42% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.47% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 10612322 18.31% 86.77% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 6714161 11.58% 98.36% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 951931 1.64% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 57966423 # Type of FU issued
system.cpu.iq.rate 0.498544 # Inst issue rate
system.cpu.iq.fu_busy_cnt 769465 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.013274 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 198287117 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 69820873 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 56409682 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 692252 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 333301 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 328338 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 58365379 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 363228 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 574200 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1607370 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 13516 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 14481 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 600235 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 173076 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1500673 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 8975371 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 617328 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 65437961 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 865160 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 10719689 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 6992362 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1868933 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 485175 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 15743 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 14481 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 386643 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 382870 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 769513 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 57271021 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 10213321 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 695401 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 3625473 # number of nop insts executed
system.cpu.iew.exec_refs 16867223 # number of memory reference insts executed
system.cpu.iew.exec_branches 9097936 # Number of branches executed
system.cpu.iew.exec_stores 6653902 # Number of stores executed
system.cpu.iew.exec_rate 0.492563 # Inst execution rate
system.cpu.iew.wb_sent 56871872 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 56738020 # cumulative count of insts written-back
system.cpu.iew.wb_producers 28030988 # num instructions producing a value
system.cpu.iew.wb_consumers 37770905 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.487979 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.742132 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 56280196 # The number of committed instructions
system.cpu.commit.commitCommittedOps 56280196 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 9036196 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 667545 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 701106 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 80658204 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.697762 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.611283 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 59481462 73.75% 73.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 8887876 11.02% 84.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4721135 5.85% 90.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2612091 3.24% 93.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1531941 1.90% 95.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 645193 0.80% 96.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 475603 0.59% 97.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 516794 0.64% 97.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1786109 2.21% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 80658204 # Number of insts commited each cycle
system.cpu.commit.committedInsts 56280196 # Number of instructions committed
system.cpu.commit.committedOps 56280196 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 15504446 # Number of memory references committed
system.cpu.commit.loads 9112319 # Number of loads committed
system.cpu.commit.membars 227818 # Number of memory barriers committed
system.cpu.commit.branches 8461284 # Number of branches committed
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
system.cpu.commit.int_insts 52119152 # Number of committed integer instructions.
system.cpu.commit.function_calls 744404 # Number of function calls committed.
system.cpu.commit.bw_lim_events 1786109 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 143937484 # The number of ROB reads
system.cpu.rob.rob_writes 132136289 # The number of ROB writes
system.cpu.timesIdled 1255783 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 34112637 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 3603423163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 53085804 # Number of Instructions Simulated
system.cpu.committedOps 53085804 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 53085804 # Number of Instructions Simulated
system.cpu.cpi 2.190256 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.190256 # CPI: Total CPI of All Threads
system.cpu.ipc 0.456568 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.456568 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 75080091 # number of integer regfile reads
system.cpu.int_regfile_writes 40965330 # number of integer regfile writes
system.cpu.fp_regfile_reads 166532 # number of floating regfile reads
system.cpu.fp_regfile_writes 167403 # number of floating regfile writes
system.cpu.misc_regfile_reads 1996306 # number of misc regfile reads
system.cpu.misc_regfile_writes 949674 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu.icache.replacements 1004588 # number of replacements
system.cpu.icache.tagsinuse 509.963959 # Cycle average of tags in use
system.cpu.icache.total_refs 7985769 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1005097 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 7.945272 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 23358400000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 509.963959 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996023 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996023 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 7985770 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 7985770 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 7985770 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 7985770 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 7985770 # number of overall hits
system.cpu.icache.overall_hits::total 7985770 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1065446 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1065446 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1065446 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1065446 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1065446 # number of overall misses
system.cpu.icache.overall_misses::total 1065446 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15927822494 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15927822494 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15927822494 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15927822494 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15927822494 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15927822494 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 9051216 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 9051216 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 9051216 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 9051216 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 9051216 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 9051216 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117713 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.117713 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.117713 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14949.441355 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14949.441355 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14949.441355 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 1315496 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 121 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 10871.867769 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 234 # number of writebacks
system.cpu.icache.writebacks::total 234 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60134 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 60134 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 60134 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 60134 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 60134 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 60134 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1005312 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1005312 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1005312 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1005312 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1005312 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1005312 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12047333996 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 12047333996 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12047333996 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 12047333996 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12047333996 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12047333996 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.676705 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.676705 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.676705 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1403406 # number of replacements
system.cpu.dcache.tagsinuse 511.996008 # Cycle average of tags in use
system.cpu.dcache.total_refs 12086534 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1403918 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 8.609145 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 19221000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.996008 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 7453772 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7453772 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4220462 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4220462 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 192050 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 192050 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 220033 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 220033 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 11674234 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 11674234 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 11674234 # number of overall hits
system.cpu.dcache.overall_hits::total 11674234 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1809182 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1809182 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1936475 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1936475 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22599 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 22599 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 3745657 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3745657 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3745657 # number of overall misses
system.cpu.dcache.overall_misses::total 3745657 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 38930236000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 38930236000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57815325976 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 57815325976 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 338636000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 338636000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 28500 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 28500 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 96745561976 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 96745561976 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 96745561976 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 96745561976 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 9262954 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9262954 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6156937 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6156937 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 214649 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 214649 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 220035 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 220035 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 15419891 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 15419891 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 15419891 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15419891 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.195314 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314519 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.105284 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.242911 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.242911 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21518.142453 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29855.963013 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14984.556839 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14250 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25828.729640 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25828.729640 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 920169326 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 212000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 101826 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9036.683421 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 23555.555556 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 834955 # number of writebacks
system.cpu.dcache.writebacks::total 834955 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721461 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 721461 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1637588 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1637588 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5103 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5103 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2359049 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2359049 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2359049 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2359049 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1087721 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1087721 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298887 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 298887 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17496 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17496 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1386608 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1386608 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1386608 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1386608 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24804888500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24804888500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509686826 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509686826 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 206420500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 206420500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33314575326 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 33314575326 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33314575326 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 33314575326 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904009500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904009500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1234178998 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1234178998 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2138188498 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 2138188498 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.117427 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048545 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.081510 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22804.458588 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28471.251095 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11798.153864 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed
system.cpu.kern.inst.hwrei 211491 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74854 40.97% 40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 241 0.13% 41.10% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1878 1.03% 42.13% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 105750 57.87% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 182723 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73487 49.29% 49.29% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1878 1.26% 50.71% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73489 49.29% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149095 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1821211214000 97.92% 97.92% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 93652500 0.01% 97.93% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 383616500 0.02% 97.95% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 38161211000 2.05% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1859849694000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981738 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31 0.694931 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl 175394 91.19% 93.39% # number of callpals executed
system.cpu.kern.callpal::rdps 6783 3.53% 96.92% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
system.cpu.kern.callpal::rti 5211 2.71% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.callpal::total 192344 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches
system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2105 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1909
system.cpu.kern.mode_good::user 1739
system.cpu.kern.mode_good::idle 170
system.cpu.kern.mode_switch_good::kernel 0.320948 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.080760 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 1.401708 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 29148036500 1.57% 1.57% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 2681917500 0.14% 1.71% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1828019732000 98.29% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
---------- End Simulation Statistics ----------
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