path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.860172                       # Number of seconds simulated
sim_ticks                                1860172195000                       # Number of ticks simulated
final_tick                               1860172195000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 152063                       # Simulator instruction rate (inst/s)
host_op_rate                                   152063                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5340733222                       # Simulator tick rate (ticks/s)
host_mem_usage                                 304984                       # Number of bytes of host memory used
host_seconds                                   348.30                       # Real time elapsed on the host
sim_insts                                    52963419                       # Number of instructions simulated
sim_ops                                      52963419                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            965120                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24879104                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28496512                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       965120                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          965120                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7515712                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7515712                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              15080                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388736                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                445258                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          117433                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               117433                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               518834                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13374624                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1425829                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15319287                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          518834                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             518834                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4040331                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4040331                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4040331                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              518834                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13374624                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1425829                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19359618                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        445258                       # Number of read requests accepted
system.physmem.writeReqs                       117433                       # Number of write requests accepted
system.physmem.readBursts                      445258                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     117433                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 28490432                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6080                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7513664                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  28496512                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7515712                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       95                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            176                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               28223                       # Per bank write bursts
system.physmem.perBankRdBursts::1               27968                       # Per bank write bursts
system.physmem.perBankRdBursts::2               28292                       # Per bank write bursts
system.physmem.perBankRdBursts::3               27927                       # Per bank write bursts
system.physmem.perBankRdBursts::4               27805                       # Per bank write bursts
system.physmem.perBankRdBursts::5               27242                       # Per bank write bursts
system.physmem.perBankRdBursts::6               27352                       # Per bank write bursts
system.physmem.perBankRdBursts::7               27274                       # Per bank write bursts
system.physmem.perBankRdBursts::8               27691                       # Per bank write bursts
system.physmem.perBankRdBursts::9               27508                       # Per bank write bursts
system.physmem.perBankRdBursts::10              27933                       # Per bank write bursts
system.physmem.perBankRdBursts::11              27527                       # Per bank write bursts
system.physmem.perBankRdBursts::12              27552                       # Per bank write bursts
system.physmem.perBankRdBursts::13              28225                       # Per bank write bursts
system.physmem.perBankRdBursts::14              28330                       # Per bank write bursts
system.physmem.perBankRdBursts::15              28314                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7932                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7496                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7821                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7427                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7353                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6703                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6854                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6665                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7118                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6889                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7323                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6981                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7116                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7874                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8055                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7794                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
system.physmem.totGap                    1860166839000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  445258                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 117433                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    317162                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     38754                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     44609                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9021                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2051                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      4407                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      3954                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      3974                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2513                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2195                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     2171                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2106                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1630                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1618                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1898                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1857                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     2113                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                     1232                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      984                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      899                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1086                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2248                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4215                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4772                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4937                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5276                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5563                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5819                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6253                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6876                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6083                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6291                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6234                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6019                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      966                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      924                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      969                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      901                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      939                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      988                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1058                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      973                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1276                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1414                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1656                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1977                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     1860                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1689                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                     1697                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                     1803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                     1633                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      837                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      395                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      207                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       16                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        63680                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      565.384925                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     351.672479                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     419.574374                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          13299     20.88%     20.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        10397     16.33%     37.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4628      7.27%     44.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2746      4.31%     48.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2553      4.01%     52.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1655      2.60%     55.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1376      2.16%     57.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1696      2.66%     60.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        25330     39.78%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          63680                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6888                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        64.625581                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       16.554610                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2544.325145                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           6885     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6888                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6888                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.044280                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.812634                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        3.762583                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               5511     80.01%     80.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 31      0.45%     80.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                662      9.61%     90.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                220      3.19%     93.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                110      1.60%     94.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 25      0.36%     95.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 25      0.36%     95.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 91      1.32%     96.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 22      0.32%     97.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 31      0.45%     97.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                 12      0.17%     97.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                 22      0.32%     98.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  6      0.09%     98.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                 14      0.20%     98.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  3      0.04%     98.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                 16      0.23%     98.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                 12      0.17%     98.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34                  7      0.10%     99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35                  1      0.01%     99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36                  1      0.01%     99.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37                  3      0.04%     99.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38                  4      0.06%     99.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39                  4      0.06%     99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40                  4      0.06%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::41                  6      0.09%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43                  3      0.04%     99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46                  3      0.04%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::47                  7      0.10%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48                  2      0.03%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::49                  1      0.01%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50                  2      0.03%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::51                  2      0.03%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52                  1      0.01%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::53                  1      0.01%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::54                  1      0.01%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::55                  1      0.01%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56                  8      0.12%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::57                 12      0.17%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58                  1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6888                       # Writes before turning the bus around for reads
system.physmem.totQLat                     8740437500                       # Total ticks spent queuing
system.physmem.totMemAccLat               17087243750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2225815000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       19634.24                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  38384.24                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          15.32                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           4.04                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       15.32                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        4.04                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.65                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.75                       # Average write queue length when enqueuing
system.physmem.readRowHits                     403028                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     95855                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.53                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  81.63                       # Row buffer hit rate for writes
system.physmem.avgGap                      3305840.75                       # Average gap between requests
system.physmem.pageHitRate                      88.68                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     1761575145500                       # Time in different power states
system.physmem.memoryStateTime::REF       62115040000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       36476358250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                     19402477                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              295985                       # Transaction distribution
system.membus.trans_dist::ReadResp             295900                       # Transaction distribution
system.membus.trans_dist::WriteReq               9597                       # Transaction distribution
system.membus.trans_dist::WriteResp              9597                       # Transaction distribution
system.membus.trans_dist::Writeback            117433                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              178                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             179                       # Transaction distribution
system.membus.trans_dist::ReadExReq            156844                       # Transaction distribution
system.membus.trans_dist::ReadExResp           156844                       # Transaction distribution
system.membus.trans_dist::BadAddressError           85                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33054                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       884181                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          170                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       917405                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124679                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       124679                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1042084                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44140                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30703168                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30747308                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5309056                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5309056                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            36056364                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               36056364                       # Total data (bytes)
system.membus.snoop_data_through_bus            35584                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            29838500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1526200750                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer2.occupancy              104500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3755175800                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy          376659242                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41685                       # number of replacements
system.iocache.tags.tagsinuse                1.260971                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1710335831000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.260971                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.078811                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.078811                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
system.iocache.tags.data_accesses              375525                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21134383                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21134383                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  12441682213                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  12441682213                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  12462816596                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  12462816596                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  12462816596                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  12462816596                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122164.063584                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299424.389031                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 299424.389031                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 298689.433098                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 298689.433098                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 298689.433098                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 298689.433098                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        366119                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                28395                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    12.893784                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12137383                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12137383                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10278710729                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total  10278710729                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide  10290848112                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total  10290848112                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide  10290848112                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total  10290848112                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247369.819239                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 247369.819239                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246635.065596                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 246635.065596                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246635.065596                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 246635.065596                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                13973676                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11739131                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            397652                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9590938                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 5932533                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             61.855608                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                  905503                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              38808                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                     10112222                       # DTB read hits
system.cpu.dtb.read_misses                      41745                       # DTB read misses
system.cpu.dtb.read_acv                           542                       # DTB read access violations
system.cpu.dtb.read_accesses                   945441                       # DTB read accesses
system.cpu.dtb.write_hits                     6611008                       # DTB write hits
system.cpu.dtb.write_misses                     10791                       # DTB write misses
system.cpu.dtb.write_acv                          413                       # DTB write access violations
system.cpu.dtb.write_accesses                  339727                       # DTB write accesses
system.cpu.dtb.data_hits                     16723230                       # DTB hits
system.cpu.dtb.data_misses                      52536                       # DTB misses
system.cpu.dtb.data_acv                           955                       # DTB access violations
system.cpu.dtb.data_accesses                  1285168                       # DTB accesses
system.cpu.itb.fetch_hits                     1309723                       # ITB hits
system.cpu.itb.fetch_misses                     39683                       # ITB misses
system.cpu.itb.fetch_acv                         1073                       # ITB acv
system.cpu.itb.fetch_accesses                 1349406                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                        121578156                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           28154197                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       72069959                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    13973676                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            6838036                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      13462286                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 2111809                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               36504135                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                32813                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        258219                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       367287                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          202                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8654218                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                283642                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           80169891                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.898965                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.245398                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 66707605     83.21%     83.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                   850391      1.06%     84.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1701562      2.12%     86.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   829510      1.03%     87.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2814732      3.51%     90.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                   566680      0.71%     91.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   649069      0.81%     92.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1061564      1.32%     93.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  4988778      6.22%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             80169891                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.114936                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.592787                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 28969141                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              36597720                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  12749238                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                505228                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1348563                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved               587502                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 42619                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts               70583559                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                129875                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1348563                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 29902418                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                12633582                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       20046715                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  11807818                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               4430793                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               66640171                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  8986                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 787429                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                  47943                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                1601274                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands            44565634                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups              80920867                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups         80741427                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            166989                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              38166970                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  6398656                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1681821                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         238696                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                   9832739                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             10696003                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             7004082                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1336985                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           877203                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   58981840                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2047452                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  57223975                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            117650                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         7712570                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined      4365148                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved        1386476                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      80169891                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.713784                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.404933                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            56166624     70.06%     70.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            10391261     12.96%     83.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             4679899      5.84%     88.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             3142763      3.92%     92.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2796032      3.49%     96.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             1647190      2.05%     98.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6              895238      1.12%     99.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              353951      0.44%     99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8               96933      0.12%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        80169891                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   98738     11.92%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.92% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 400158     48.30%     60.22% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                329520     39.78%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              7286      0.01%      0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              38901419     67.98%     67.99% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                61759      0.11%     68.10% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd               25607      0.04%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.15% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             10584317     18.50%     86.65% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             6690891     11.69%     98.34% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess             949060      1.66%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               57223975                       # Type of FU issued
system.cpu.iq.rate                           0.470676                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                      828416                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.014477                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          194870458                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes          68419457                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     55733530                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads              693448                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             335810                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       328249                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               57682446                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  362659                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           614531                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1606237                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         3745                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        13777                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       627539                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        18239                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        375591                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1348563                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 9312966                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                978337                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            64604997                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            590069                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              10696003                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              7004082                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1802911                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 468863                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                377382                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          13777                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         204854                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       411482                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               616336                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              56685901                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              10182131                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            538073                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       3575705                       # number of nop insts executed
system.cpu.iew.exec_refs                     16819167                       # number of memory reference insts executed
system.cpu.iew.exec_branches                  8947461                       # Number of branches executed
system.cpu.iew.exec_stores                    6637036                       # Number of stores executed
system.cpu.iew.exec_rate                     0.466251                       # Inst execution rate
system.cpu.iew.wb_sent                       56177988                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      56061779                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  28606216                       # num instructions producing a value
system.cpu.iew.wb_consumers                  39617780                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.461117                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.722055                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts         8325898                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls          660976                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            566478                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     78821328                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.712415                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.665597                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     58682621     74.45%     74.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      8193641     10.40%     84.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4257107      5.40%     90.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2319840      2.94%     93.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1767395      2.24%     95.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       615421      0.78%     96.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       496583      0.63%     96.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       549859      0.70%     97.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      1938861      2.46%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     78821328                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             56153459                       # Number of instructions committed
system.cpu.commit.committedOps               56153459                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       15466309                       # Number of memory references committed
system.cpu.commit.loads                       9089766                       # Number of loads committed
system.cpu.commit.membars                      226357                       # Number of memory barriers committed
system.cpu.commit.branches                    8438044                       # Number of branches committed
system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  52003822                       # Number of committed integer instructions.
system.cpu.commit.function_calls               740374                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      3197313      5.69%      5.69% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         36218566     64.50%     70.19% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           60658      0.11%     70.30% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.30% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd          25607      0.05%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv           3636      0.01%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead         9316123     16.59%     86.94% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        6382496     11.37%     98.31% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess        949060      1.69%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          56153459                       # Class of committed instruction
system.cpu.commit.bw_lim_events               1938861                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    141112277                       # The number of ROB reads
system.cpu.rob.rob_writes                   130308588                       # The number of ROB writes
system.cpu.timesIdled                         1194216                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        41408265                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   3598759795                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    52963419                       # Number of Instructions Simulated
system.cpu.committedOps                      52963419                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               2.295512                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.295512                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.435633                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.435633                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                 74250743                       # number of integer regfile reads
system.cpu.int_regfile_writes                40442410                       # number of integer regfile writes
system.cpu.fp_regfile_reads                    166399                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   167429                       # number of floating regfile writes
system.cpu.misc_regfile_reads                 2028427                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 938976                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.iobus.throughput                       1454569                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
system.iobus.trans_dist::WriteReq               51149                       # Transaction distribution
system.iobus.trans_dist::WriteResp              51149                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5050                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        33054                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  116504                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20200                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total        44140                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              2705748                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 2705748                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              4661000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13484000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           380163354                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            23457000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            43205758                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.cpu.toL2Bus.throughput               111909594                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        2117185                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2117083                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq          9597                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp         9597                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       840753                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           64                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           66                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       342629                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       301078                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError           85                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2018148                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3678150                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           5696298                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     64577024                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143586668                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      208163692                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         208153644                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus        17472                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     2479804999                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       235500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1516964420                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2185370157                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.icache.tags.replacements           1008400                       # number of replacements
system.cpu.icache.tags.tagsinuse           509.648597                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             7589401                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1008908                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              7.522392                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       26586363250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   509.648597                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.995407                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.995407                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          123                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          314                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses           9663349                       # Number of tag accesses
system.cpu.icache.tags.data_accesses          9663349                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      7589402                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7589402                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7589402                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7589402                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7589402                       # number of overall hits
system.cpu.icache.overall_hits::total         7589402                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1064815                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1064815                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1064815                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1064815                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1064815                       # number of overall misses
system.cpu.icache.overall_misses::total       1064815                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14788071318                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14788071318                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14788071318                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14788071318                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14788071318                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14788071318                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8654217                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8654217                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8654217                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8654217                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8654217                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8654217                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.123040                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.123040                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.123040                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.123040                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.123040                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.123040                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13887.925431                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13887.925431                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13887.925431                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13887.925431                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13887.925431                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13887.925431                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         4640                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               182                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    25.494505                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        55683                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        55683                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        55683                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        55683                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        55683                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        55683                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1009132                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1009132                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1009132                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1009132                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1009132                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1009132                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12130132326                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12130132326                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12130132326                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12130132326                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12130132326                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12130132326                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.116606                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.116606                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.116606                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.116606                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.116606                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.116606                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12020.362377                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12020.362377                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12020.362377                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12020.362377                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12020.362377                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12020.362377                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           338319                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65340.875442                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            2545143                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           403486                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             6.307884                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       5540956750                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 53842.334774                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  5321.183862                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  6177.356806                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.821569                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.081195                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.094259                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.997023                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65167                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          492                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3496                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3313                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2397                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55469                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994370                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         26719739                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        26719739                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst       993934                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       827149                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1821083                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       840753                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       840753                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           26                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           26                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            1                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       185645                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       185645                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       993934                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1012794                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2006728                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       993934                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1012794                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2006728                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        15082                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       273801                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       288883                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           38                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           38                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       115432                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       115432                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst        15082                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       389233                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        404315                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        15082                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       389233                       # number of overall misses
system.cpu.l2cache.overall_misses::total       404315                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1156562743                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17908390235                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  19064952978                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       285997                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       285997                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9622114357                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9622114357                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1156562743                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  27530504592                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  28687067335                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1156562743                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  27530504592                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  28687067335                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1009016                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1100950                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2109966                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       840753                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       840753                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           64                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           64                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       301077                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       301077                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      1009016                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1402027                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2411043                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1009016                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1402027                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2411043                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014947                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.248695                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.136914                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.593750                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.593750                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383397                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.383397                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014947                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.277622                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.167693                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014947                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.277622                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.167693                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76684.971688                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65406.591777                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 65995.413292                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  7526.236842                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  7526.236842                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83357.425645                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83357.425645                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76684.971688                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70730.140024                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70952.270717                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76684.971688                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70730.140024                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70952.270717                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        75921                       # number of writebacks
system.cpu.l2cache.writebacks::total            75921                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15081                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273801                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       288882                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           38                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           38                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115432                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       115432                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        15081                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       389233                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       404314                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        15081                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       389233                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       404314                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    966321757                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14496174265                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15462496022                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       531034                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       531034                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        10001                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        10001                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8215113143                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8215113143                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    966321757                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  22711287408                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  23677609165                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    966321757                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  22711287408                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  23677609165                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1333995500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333995500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1882363500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1882363500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3216359000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3216359000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014946                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248695                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.136913                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.593750                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.593750                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383397                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383397                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014946                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277622                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.167693                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014946                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277622                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.167693                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64075.443074                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52944.197665                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53525.301064                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13974.578947                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13974.578947                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71168.420741                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71168.420741                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64075.443074                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58348.822962                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58562.427136                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64075.443074                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58348.822962                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58562.427136                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1401429                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.994598                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            11820645                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1401941                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs              8.431628                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          25377000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.994598                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999989                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999989                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          415                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           95                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          63732446                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         63732446                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data      7221951                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7221951                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      4197394                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4197394                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       185535                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       185535                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       215521                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       215521                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      11419345                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         11419345                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     11419345                       # number of overall hits
system.cpu.dcache.overall_hits::total        11419345                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1789877                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1789877                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1948925                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1948925                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        23421                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        23421                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3738802                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3738802                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3738802                       # number of overall misses
system.cpu.dcache.overall_misses::total       3738802                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  40163370133                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  40163370133                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  77928512640                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  77928512640                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    358310999                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    358310999                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        38001                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total        38001                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 118091882773                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 118091882773                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 118091882773                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 118091882773                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      9011828                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9011828                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6146319                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6146319                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       208956                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       208956                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       215523                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       215523                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15158147                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15158147                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15158147                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15158147                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.198614                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.198614                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.317088                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.317088                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.112086                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.112086                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000009                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000009                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.246653                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.246653                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.246653                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.246653                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22439.178856                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 22439.178856                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39985.383039                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39985.383039                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15298.706247                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15298.706247                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000.500000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000.500000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31585.487216                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31585.487216                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31585.487216                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31585.487216                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      3437281                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          992                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs            114395                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               8                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    30.047476                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          124                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       840753                       # number of writebacks
system.cpu.dcache.writebacks::total            840753                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       705849                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       705849                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1648446                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1648446                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5839                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         5839                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2354295                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2354295                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2354295                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2354295                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1084028                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1084028                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300479                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       300479                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17582                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17582                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1384507                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1384507                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1384507                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1384507                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27275332511                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  27275332511                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11834545572                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11834545572                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    200445001                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    200445001                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        33999                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        33999                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  39109878083                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  39109878083                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  39109878083                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  39109878083                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424085500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424085500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1997539998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1997539998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3421625498                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3421625498                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120289                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120289                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048888                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048888                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.084142                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.084142                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091337                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.091337                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091337                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.091337                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25161.095941                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25161.095941                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39385.599566                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39385.599566                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11400.580196                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11400.580196                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16999.500000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16999.500000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28248.234269                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28248.234269                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28248.234269                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28248.234269                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6440                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     211015                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74666     40.97%     40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1879      1.03%     42.07% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  105570     57.93%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               182246                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73299     49.32%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1879      1.26%     50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73299     49.32%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                148608                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1817910535000     97.73%     97.73% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                64222000      0.00%     97.73% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               554846000      0.03%     97.76% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             41641763000      2.24%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1860171366000                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981692                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.694317                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.815425                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl                175131     91.23%     93.44% # number of callpals executed
system.cpu.kern.callpal::rdps                    6784      3.53%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::rti                     5104      2.66%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 191975                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5851                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2095                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1910                      
system.cpu.kern.mode_good::user                  1740                      
system.cpu.kern.mode_good::idle                   170                      
system.cpu.kern.mode_switch_good::kernel     0.326440                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.081146                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.394384                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        29515260500      1.59%      1.59% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           2703792500      0.15%      1.73% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1827952305000     98.27%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------