path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.843672                       # Number of seconds simulated
sim_ticks                                1843672389000                       # Number of ticks simulated
final_tick                               1843672389000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 195444                       # Simulator instruction rate (inst/s)
host_op_rate                                   195444                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4916161077                       # Simulator tick rate (ticks/s)
host_mem_usage                                 347768                       # Number of bytes of host memory used
host_seconds                                   375.02                       # Real time elapsed on the host
sim_insts                                    73296119                       # Number of instructions simulated
sim_ops                                      73296119                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst           488384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         20120896                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           147840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          2228608                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           281856                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          2520448                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28440384                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       488384                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       147840                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       281856                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          918080                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7465920                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7465920                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst              7631                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            314389                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2310                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             34822                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              4404                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             39382                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                444381                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          116655                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               116655                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              264897                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            10913488                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1438624                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               80188                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1208787                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst              152877                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             1367080                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15425942                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         264897                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          80188                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst         152877                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             497963                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4049483                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4049483                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4049483                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             264897                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           10913488                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1438624                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              80188                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1208787                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst             152877                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            1367080                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19475425                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         98065                       # Number of read requests accepted
system.physmem.writeReqs                        44647                       # Number of write requests accepted
system.physmem.readBursts                       98065                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      44647                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  6274880                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      1280                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   2856000                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   6276160                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                2857408                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       20                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs             43                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                6107                       # Per bank write bursts
system.physmem.perBankRdBursts::1                5922                       # Per bank write bursts
system.physmem.perBankRdBursts::2                6220                       # Per bank write bursts
system.physmem.perBankRdBursts::3                6321                       # Per bank write bursts
system.physmem.perBankRdBursts::4                5635                       # Per bank write bursts
system.physmem.perBankRdBursts::5                6235                       # Per bank write bursts
system.physmem.perBankRdBursts::6                5931                       # Per bank write bursts
system.physmem.perBankRdBursts::7                6044                       # Per bank write bursts
system.physmem.perBankRdBursts::8                6533                       # Per bank write bursts
system.physmem.perBankRdBursts::9                6108                       # Per bank write bursts
system.physmem.perBankRdBursts::10               6507                       # Per bank write bursts
system.physmem.perBankRdBursts::11               5966                       # Per bank write bursts
system.physmem.perBankRdBursts::12               5866                       # Per bank write bursts
system.physmem.perBankRdBursts::13               6273                       # Per bank write bursts
system.physmem.perBankRdBursts::14               6336                       # Per bank write bursts
system.physmem.perBankRdBursts::15               6041                       # Per bank write bursts
system.physmem.perBankWrBursts::0                2748                       # Per bank write bursts
system.physmem.perBankWrBursts::1                2555                       # Per bank write bursts
system.physmem.perBankWrBursts::2                2839                       # Per bank write bursts
system.physmem.perBankWrBursts::3                3065                       # Per bank write bursts
system.physmem.perBankWrBursts::4                2620                       # Per bank write bursts
system.physmem.perBankWrBursts::5                2963                       # Per bank write bursts
system.physmem.perBankWrBursts::6                2854                       # Per bank write bursts
system.physmem.perBankWrBursts::7                2670                       # Per bank write bursts
system.physmem.perBankWrBursts::8                3259                       # Per bank write bursts
system.physmem.perBankWrBursts::9                2627                       # Per bank write bursts
system.physmem.perBankWrBursts::10               3029                       # Per bank write bursts
system.physmem.perBankWrBursts::11               2539                       # Per bank write bursts
system.physmem.perBankWrBursts::12               2431                       # Per bank write bursts
system.physmem.perBankWrBursts::13               2744                       # Per bank write bursts
system.physmem.perBankWrBursts::14               2948                       # Per bank write bursts
system.physmem.perBankWrBursts::15               2734                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
system.physmem.totGap                    1842660063500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   98065                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  44647                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     65397                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      7824                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      8078                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      2035                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       831                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      1795                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1629                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1651                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1059                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       913                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      873                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      850                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      660                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      661                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      817                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      795                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      896                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      513                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      393                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      373                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                        77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        43                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      569                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      590                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     1447                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     1573                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     1674                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     1688                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     1720                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1786                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     1841                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     1914                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     2036                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     2069                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     2187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     2080                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     2119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     2107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     2073                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      340                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      344                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      350                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      302                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      350                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      363                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      393                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      364                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      474                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      505                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      461                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      587                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      667                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      827                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      929                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      857                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      863                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      793                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      769                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      814                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      721                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      371                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        21868                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      417.545272                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     236.447646                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     397.078129                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127           6878     31.45%     31.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         4663     21.32%     52.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         1715      7.84%     60.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511          976      4.46%     65.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639          897      4.10%     69.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          495      2.26%     71.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          365      1.67%     73.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          382      1.75%     74.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         5497     25.14%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          21868                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          2618                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        37.446906                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      907.093650                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           2616     99.92%     99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.04%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.04%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            2618                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          2618                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.045455                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.392541                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        4.534822                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-1                25      0.95%      0.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2-3                 9      0.34%      1.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-5                 2      0.08%      1.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::6-7                 3      0.11%      1.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-9                 2      0.08%      1.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::10-11               1      0.04%      1.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::14-15               1      0.04%      1.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            1908     72.88%     74.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19             472     18.03%     92.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21              41      1.57%     94.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23              56      2.14%     96.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25              26      0.99%     97.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27              16      0.61%     97.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29              10      0.38%     98.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31              14      0.53%     98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33               7      0.27%     99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37               1      0.04%     99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38-39               1      0.04%     99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41               3      0.11%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45               4      0.15%     99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-53               1      0.04%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::54-55               1      0.04%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-57              11      0.42%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58-59               1      0.04%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-61               1      0.04%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-65               1      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            2618                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2942753000                       # Total ticks spent queuing
system.physmem.totMemAccLat                4781096750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    490225000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       30014.31                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  48764.31                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.40                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.55                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.40                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.55                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.17                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         4.22                       # Average write queue length when enqueuing
system.physmem.readRowHits                      85384                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     35418                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   87.09                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  79.33                       # Row buffer hit rate for writes
system.physmem.avgGap                     12911738.77                       # Average gap between requests
system.physmem.pageHitRate                      84.66                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     1768578867000                       # Time in different power states
system.physmem.memoryStateTime::REF       61564100000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       13524513000                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                     19519346                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq               44419                       # Transaction distribution
system.membus.trans_dist::ReadResp              44389                       # Transaction distribution
system.membus.trans_dist::WriteReq               3765                       # Transaction distribution
system.membus.trans_dist::WriteResp              3765                       # Transaction distribution
system.membus.trans_dist::Writeback             44647                       # Transaction distribution
system.membus.trans_dist::UpgradeReq               46                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              46                       # Transaction distribution
system.membus.trans_dist::ReadExReq             56746                       # Transaction distribution
system.membus.trans_dist::ReadExResp            56746                       # Transaction distribution
system.membus.trans_dist::BadAddressError           30                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        13356                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       189542                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           60                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       202958                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        51481                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        51481                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 254439                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        15715                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      6940992                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total      6956707                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2192576                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      2192576                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total             9149283                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               35977232                       # Total data (bytes)
system.membus.snoop_data_through_bus            10048                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            12506000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           516947250                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy               37500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy          762242703                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          155440000                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                   337456                       # number of replacements
system.l2c.tags.tagsinuse                65422.465864                       # Cycle average of tags in use
system.l2c.tags.total_refs                    2473240                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   402619                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     6.142879                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                614754000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   54816.531838                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     2443.286445                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2722.487240                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      580.950396                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      624.587700                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     2109.099829                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     2125.522416                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.836434                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.037282                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.041542                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.008865                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.009530                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.032182                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.032433                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.998268                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        65163                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1         1026                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         5608                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         2978                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        55383                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 26151122                       # Number of tag accesses
system.l2c.tags.data_accesses                26151122                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst             519486                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             493287                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             124779                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              84464                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst             292648                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data             239510                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1754174                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          836240                       # number of Writeback hits
system.l2c.Writeback_hits::total               836240                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   7                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data             1                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 1                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            92910                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            26171                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            67815                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               186896                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              519486                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              586197                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              124779                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              110635                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              292648                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              307325                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1941070                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             519486                       # number of overall hits
system.l2c.overall_hits::cpu0.data             586197                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             124779                       # number of overall hits
system.l2c.overall_hits::cpu1.data             110635                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             292648                       # number of overall hits
system.l2c.overall_hits::cpu2.data             307325                       # number of overall hits
system.l2c.overall_hits::total                1941070                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst             7631                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           238513                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             2310                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data            16826                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst             4404                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data            17896                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               287580                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data             8                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            12                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                20                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          76151                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          18045                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          21583                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             115779                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst              7631                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            314664                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2310                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             34871                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              4404                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             39479                       # number of demand (read+write) misses
system.l2c.demand_misses::total                403359                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst             7631                       # number of overall misses
system.l2c.overall_misses::cpu0.data           314664                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2310                       # number of overall misses
system.l2c.overall_misses::cpu1.data            34871                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             4404                       # number of overall misses
system.l2c.overall_misses::cpu2.data            39479                       # number of overall misses
system.l2c.overall_misses::total               403359                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst    168327497                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data   1121769250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst    335079500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data   1193124499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     2818300746                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data       318496                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       318496                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1237365240                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   1750671726                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2988036966                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst    168327497                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   2359134490                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    335079500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   2943796225                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      5806337712                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst    168327497                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   2359134490                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    335079500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   2943796225                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     5806337712                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         527117                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         731800                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         127089                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         101290                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst         297052                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data         257406                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2041754                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       836240                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           836240                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           11                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data            1                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           15                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              27                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       169061                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        44216                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        89398                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           302675                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          527117                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          900861                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          127089                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          145506                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          297052                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          346804                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2344429                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         527117                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         900861                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         127089                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         145506                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         297052                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         346804                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2344429                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.014477                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.325926                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.018176                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.166117                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.014826                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.069524                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.140849                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.727273                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.800000                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.740741                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.450435                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.408110                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.241426                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.382519                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.014477                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.349293                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.018176                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.239653                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.014826                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.113837                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.172050                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.014477                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.349293                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.018176                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.239653                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.014826                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.113837                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.172050                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72869.046320                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 66668.801260                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76085.263397                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 66669.898245                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total  9800.058231                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 26541.333333                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 15924.800000                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68571.085619                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81113.456239                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 25808.108258                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 72869.046320                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 67653.192911                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 76085.263397                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 74566.129461                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 14394.962582                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 72869.046320                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 67653.192911                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 76085.263397                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 74566.129461                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 14394.962582                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               75143                       # number of writebacks
system.l2c.writebacks::total                    75143                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu1.inst         2310                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data        16826                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst         4404                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data        17896                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           41436                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           12                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           12                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        18045                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        21583                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         39628                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2310                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        34871                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         4404                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        39479                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            81064                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2310                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        34871                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         4404                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        39479                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           81064                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    138909503                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    911100250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    279632500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data    972656001                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   2302298254                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       279009                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total       279009                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1010621760                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1486000274                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2496622034                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    138909503                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1921722010                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    279632500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   2458656275                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   4798920288                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    138909503                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1921722010                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    279632500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   2458656275                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   4798920288                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    277729500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    292749000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total    570478500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    344555500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    403769000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total    748324500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    622285000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data    696518000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   1318803000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.018176                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.166117                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.014826                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.069524                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.020294                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.800000                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.444444                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.408110                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.241426                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.130926                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.018176                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.239653                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014826                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.113837                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.034577                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.018176                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.239653                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014826                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.113837                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.034577                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60133.983983                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54148.356710                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63495.118074                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54350.469435                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 55562.753499                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 23250.750000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23250.750000                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56005.639235                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68850.496873                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 63001.464470                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60133.983983                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55109.460870                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63495.118074                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62277.572254                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 59199.154841                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60133.983983                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55109.460870                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63495.118074                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62277.572254                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 59199.154841                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                41685                       # number of replacements
system.iocache.tags.tagsinuse                1.262765                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1694865594000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.262765                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.078923                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.078923                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
system.iocache.tags.data_accesses              375525                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide      9418062                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total      9418062                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide   5145673458                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   5145673458                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide   5155091520                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   5155091520                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide   5155091520                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   5155091520                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54439.664740                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 54439.664740                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 123836.962312                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123836.962312                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 123549.227561                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 123549.227561                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 123549.227561                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 123549.227561                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        151978                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                11614                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    13.085759                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide           70                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total           70                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        17152                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        17152                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        17222                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        17222                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        17222                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        17222                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5777062                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total      5777062                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   4252886458                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   4252886458                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   4258663520                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   4258663520                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   4258663520                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   4258663520                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.404624                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide     0.412784                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total     0.412784                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide     0.412750                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.412750                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide     0.412750                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.412750                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82529.457143                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 82529.457143                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247952.801889                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 247952.801889                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247280.427360                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 247280.427360                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247280.427360                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 247280.427360                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     4916751                       # DTB read hits
system.cpu0.dtb.read_misses                      6099                       # DTB read misses
system.cpu0.dtb.read_acv                          126                       # DTB read access violations
system.cpu0.dtb.read_accesses                  428233                       # DTB read accesses
system.cpu0.dtb.write_hits                    3511411                       # DTB write hits
system.cpu0.dtb.write_misses                      670                       # DTB write misses
system.cpu0.dtb.write_acv                          84                       # DTB write access violations
system.cpu0.dtb.write_accesses                 163777                       # DTB write accesses
system.cpu0.dtb.data_hits                     8428162                       # DTB hits
system.cpu0.dtb.data_misses                      6769                       # DTB misses
system.cpu0.dtb.data_acv                          210                       # DTB access violations
system.cpu0.dtb.data_accesses                  592010                       # DTB accesses
system.cpu0.itb.fetch_hits                    2761691                       # ITB hits
system.cpu0.itb.fetch_misses                     3034                       # ITB misses
system.cpu0.itb.fetch_acv                         104                       # ITB acv
system.cpu0.itb.fetch_accesses                2764725                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       928579533                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   33817210                       # Number of instructions committed
system.cpu0.committedOps                     33817210                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             31677975                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                169596                       # Number of float alu accesses
system.cpu0.num_func_calls                     812570                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      4683135                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    31677975                       # number of integer instructions
system.cpu0.num_fp_insts                       169596                       # number of float instructions
system.cpu0.num_int_register_reads           44495639                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          23114141                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads               87595                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes              89102                       # number of times the floating registers were written
system.cpu0.num_mem_refs                      8458293                       # number of memory refs
system.cpu0.num_load_insts                    4938120                       # Number of load instructions
system.cpu0.num_store_insts                   3520173                       # Number of store instructions
system.cpu0.num_idle_cycles              904460149.841647                       # Number of idle cycles
system.cpu0.num_busy_cycles              24119383.158353                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.025974                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.974026                       # Percentage of idle cycles
system.cpu0.Branches                          5759211                       # Number of branches fetched
system.cpu0.op_class::No_OpClass              1618304      4.78%      4.78% # Class of executed instruction
system.cpu0.op_class::IntAlu                 23033604     68.10%     72.88% # Class of executed instruction
system.cpu0.op_class::IntMult                   32432      0.10%     72.98% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     72.98% # Class of executed instruction
system.cpu0.op_class::FloatAdd                  12174      0.04%     73.01% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     73.01% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     73.01% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     73.01% # Class of executed instruction
system.cpu0.op_class::FloatDiv                   1606      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     73.02% # Class of executed instruction
system.cpu0.op_class::MemRead                 5072252     15.00%     88.02% # Class of executed instruction
system.cpu0.op_class::MemWrite                3523323     10.42%     98.43% # Class of executed instruction
system.cpu0.op_class::IprAccess                530494      1.57%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  33824189                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6417                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    211389                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   74803     40.97%     40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1880      1.03%     42.11% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                 105703     57.89%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              182589                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    73436     49.30%     49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1880      1.26%     50.70% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   73436     49.30%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               148955                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1820445327500     98.74%     98.74% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               38826000      0.00%     98.74% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              365496000      0.02%     98.76% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            22821970000      1.24%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1843671619500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.981725                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.694739                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.815794                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      2.45%      2.45% # number of syscalls executed
system.cpu0.kern.syscall::3                        30      9.20%     11.66% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.23%     12.88% # number of syscalls executed
system.cpu0.kern.syscall::6                        42     12.88%     25.77% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.31%     26.07% # number of syscalls executed
system.cpu0.kern.syscall::15                        1      0.31%     26.38% # number of syscalls executed
system.cpu0.kern.syscall::17                       15      4.60%     30.98% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      3.07%     34.05% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      1.84%     35.89% # number of syscalls executed
system.cpu0.kern.syscall::23                        4      1.23%     37.12% # number of syscalls executed
system.cpu0.kern.syscall::24                        6      1.84%     38.96% # number of syscalls executed
system.cpu0.kern.syscall::33                       11      3.37%     42.33% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.61%     42.94% # number of syscalls executed
system.cpu0.kern.syscall::45                       54     16.56%     59.51% # number of syscalls executed
system.cpu0.kern.syscall::47                        6      1.84%     61.35% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      3.07%     64.42% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      3.07%     67.48% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.31%     67.79% # number of syscalls executed
system.cpu0.kern.syscall::59                        7      2.15%     69.94% # number of syscalls executed
system.cpu0.kern.syscall::71                       54     16.56%     86.50% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      0.92%     87.42% # number of syscalls executed
system.cpu0.kern.syscall::74                       16      4.91%     92.33% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.31%     92.64% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      0.92%     93.56% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      2.76%     96.32% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.61%     96.93% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.61%     97.55% # number of syscalls executed
system.cpu0.kern.syscall::132                       4      1.23%     98.77% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.61%     99.39% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.61%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   326                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 4174      2.17%      2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi                      54      0.03%      2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.21% # number of callpals executed
system.cpu0.kern.callpal::swpipl               175328     91.20%     93.41% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6784      3.53%     96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     7      0.00%     96.94% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.00%     96.94% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.95% # number of callpals executed
system.cpu0.kern.callpal::rti                    5177      2.69%     99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys                 515      0.27%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     181      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                192243                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             5923                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1739                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle               2094                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1908                      
system.cpu0.kern.mode_good::user                 1739                      
system.cpu0.kern.mode_good::idle                  169                      
system.cpu0.kern.mode_switch_good::kernel     0.322134                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle      0.080707                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.391144                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel       29786667000      1.62%      1.62% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          2578002500      0.14%      1.76% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle        1811306945500     98.24%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    4175                       # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.toL2Bus.throughput                   110441912                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq             785832                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            785787                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq              3765                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp             3765                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           372222                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq              16                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp             17                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           150766                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          133614                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError           30                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       848294                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1370287                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               2218581                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     27145024                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     55347363                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total           82492387                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             203607824                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus           10880                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         2138460500                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           247500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1910550337                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        2233740752                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.iobus.throughput                       1468369                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq                 2983                       # Transaction distribution
system.iobus.trans_dist::ReadResp                2983                       # Transaction distribution
system.iobus.trans_dist::WriteReq               20917                       # Transaction distribution
system.iobus.trans_dist::WriteResp              20917                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         2330                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          136                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio           66                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio         8382                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         2408                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        13356                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        34444                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        34444                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                   47800                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio         9320                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio          544                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio           61                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         4191                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         1568                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf           31                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total        15715                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      1099184                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      1099184                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              1114899                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 2707192                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              2199000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               102000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy               57000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6246000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             1819000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy               20000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           156921520                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy             9591000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            17887000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.cpu0.icache.tags.replacements           950608                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.189792                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           43374256                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           951119                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            45.603396                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      10403794250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   251.164377                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst    98.345392                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst   161.680023                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.490555                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.192081                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.315781                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998418                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         45292775                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        45292775                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     33297051                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      7835821                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      2241384                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       43374256                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     33297051                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      7835821                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      2241384                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        43374256                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     33297051                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      7835821                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      2241384                       # number of overall hits
system.cpu0.icache.overall_hits::total       43374256                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       527138                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       127089                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       313001                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       967228                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       527138                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       127089                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       313001                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        967228                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       527138                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       127089                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       313001                       # number of overall misses
system.cpu0.icache.overall_misses::total       967228                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1805503003                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4394679722                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   6200182725                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   1805503003                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   4394679722                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   6200182725                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   1805503003                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   4394679722                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   6200182725                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     33824189                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      7962910                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      2554385                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     44341484                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     33824189                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      7962910                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      2554385                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     44341484                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     33824189                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      7962910                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      2554385                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     44341484                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015585                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015960                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122535                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.021813                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015585                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015960                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.122535                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.021813                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015585                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015960                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122535                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.021813                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14206.603270                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14040.465436                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  6410.259758                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14206.603270                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14040.465436                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  6410.259758                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14206.603270                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14040.465436                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  6410.259758                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         2211                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              139                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.906475                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        15937                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        15937                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        15937                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        15937                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        15937                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        15937                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       127089                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       297064                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       424153                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       127089                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       297064                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       424153                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       127089                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       297064                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       424153                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1550405997                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3623912160                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   5174318157                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1550405997                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3623912160                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   5174318157                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1550405997                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3623912160                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   5174318157                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015960                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116296                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009566                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015960                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116296                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.009566                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015960                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116296                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.009566                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12199.372070                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12199.095683                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12199.178497                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12199.372070                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12199.095683                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12199.178497                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12199.372070                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12199.095683                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12199.178497                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements          1392627                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.997813                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           13291421                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1393139                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs             9.540628                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   251.446594                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   129.524111                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data   131.027107                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.491107                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.252977                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.255912                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          266                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         63293161                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        63293161                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      4078776                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      1086651                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      2400445                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        7565872                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3215108                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data       831895                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      1295006                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       5342009                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       117088                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19357                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        47741                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       184186                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       126296                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21393                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data        51592                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       199281                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      7293884                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      1918546                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      3695451                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        12907881                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      7293884                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      1918546                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      3695451                       # number of overall hits
system.cpu0.dcache.overall_hits::total       12907881                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       722029                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data        99123                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       533441                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1354593                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       169072                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        44217                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       597048                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       810337                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9771                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2167                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         6787                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        18725                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       891101                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       143340                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data      1130489                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2164930                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       891101                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       143340                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1130489                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2164930                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2252505500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9329560863                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  11582066363                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1640569260                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  17995165012                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  19635734272                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     28565250                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    103170749                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    131735999                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        13000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total        13000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   3893074760                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  27324725875                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  31217800635                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   3893074760                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  27324725875                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  31217800635                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      4800805                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      1185774                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      2933886                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8920465                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      3384180                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data       876112                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      1892054                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      6152346                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       126859                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21524                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        54528                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       202911                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       126297                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21393                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        51593                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       199283                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data      8184985                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      2061886                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      4825940                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     15072811                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data      8184985                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      2061886                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      4825940                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     15072811                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.150397                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.083594                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.181821                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.151852                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049960                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.050470                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.315555                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.131712                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.077023                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.100678                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.124468                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.092282                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000008                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000019                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000010                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.108870                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.069519                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.234253                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.143631                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.108870                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.069519                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.234253                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.143631                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22724.347528                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17489.395946                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total  8550.218673                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37102.681322                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30140.231626                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 24231.565721                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13181.933549                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15201.230146                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  7035.300347                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total         6500                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27159.723455                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24170.713625                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14419.773681                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27159.723455                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24170.713625                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14419.773681                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       573016                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets          707                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            17657                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    32.452625                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          101                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       836240                       # number of writebacks
system.cpu0.dcache.writebacks::total           836240                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       281234                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       281234                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       507881                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       507881                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1344                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1344                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       789115                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       789115                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       789115                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       789115                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        99123                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       252207                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       351330                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        44217                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        89167                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       133384                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2167                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5443                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7610                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       143340                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       341374                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       484714                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       143340                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       341374                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       484714                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2046709500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4236520898                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6283230398                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1543938740                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2600534498                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4144473238                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     24229750                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     66769000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     90998750                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        11000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        11000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3590648240                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   6837055396                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  10427703636                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3590648240                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   6837055396                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  10427703636                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    296463000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    311893000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    608356000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    365040500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    428466000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    793506500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    661503500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    740359000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1401862500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.083594                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.085963                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.039385                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.050470                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.047127                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.021680                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.100678                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.099820                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.037504                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000019                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.069519                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.070737                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.032158                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.069519                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.070737                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.032158                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20648.179535                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16797.792678                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17884.127168                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34917.310989                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29164.763848                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31071.742023                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11181.241347                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12266.948374                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.785808                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25049.869122                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20028.049576                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21513.105947                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25049.869122                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20028.049576                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21513.105947                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1205243                       # DTB read hits
system.cpu1.dtb.read_misses                      1367                       # DTB read misses
system.cpu1.dtb.read_acv                           34                       # DTB read access violations
system.cpu1.dtb.read_accesses                  142945                       # DTB read accesses
system.cpu1.dtb.write_hits                     897974                       # DTB write hits
system.cpu1.dtb.write_misses                      185                       # DTB write misses
system.cpu1.dtb.write_acv                          23                       # DTB write access violations
system.cpu1.dtb.write_accesses                  58533                       # DTB write accesses
system.cpu1.dtb.data_hits                     2103217                       # DTB hits
system.cpu1.dtb.data_misses                      1552                       # DTB misses
system.cpu1.dtb.data_acv                           57                       # DTB access violations
system.cpu1.dtb.data_accesses                  201478                       # DTB accesses
system.cpu1.itb.fetch_hits                     859888                       # ITB hits
system.cpu1.itb.fetch_misses                      693                       # ITB misses
system.cpu1.itb.fetch_acv                          30                       # ITB acv
system.cpu1.itb.fetch_accesses                 860581                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                       953622390                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                    7961300                       # Number of instructions committed
system.cpu1.committedOps                      7961300                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses              7416956                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                 45099                       # Number of float alu accesses
system.cpu1.num_func_calls                     213358                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      1019863                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                     7416956                       # number of integer instructions
system.cpu1.num_fp_insts                        45099                       # number of float instructions
system.cpu1.num_int_register_reads           10395465                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           5394572                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads               24307                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              24707                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      2110464                       # number of memory refs
system.cpu1.num_load_insts                    1210140                       # Number of load instructions
system.cpu1.num_store_insts                    900324                       # Number of store instructions
system.cpu1.num_idle_cycles              923192460.103175                       # Number of idle cycles
system.cpu1.num_busy_cycles              30429929.896825                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.031910                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.968090                       # Percentage of idle cycles
system.cpu1.Branches                          1300058                       # Number of branches fetched
system.cpu1.op_class::No_OpClass               413905      5.20%      5.20% # Class of executed instruction
system.cpu1.op_class::IntAlu                  5261386     66.07%     71.27% # Class of executed instruction
system.cpu1.op_class::IntMult                    8416      0.11%     71.38% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     71.38% # Class of executed instruction
system.cpu1.op_class::FloatAdd                   5003      0.06%     71.44% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     71.44% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     71.44% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     71.44% # Class of executed instruction
system.cpu1.op_class::FloatDiv                    810      0.01%     71.45% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     71.45% # Class of executed instruction
system.cpu1.op_class::MemRead                 1239389     15.56%     87.01% # Class of executed instruction
system.cpu1.op_class::MemWrite                 901545     11.32%     98.34% # Class of executed instruction
system.cpu1.op_class::IprAccess                132455      1.66%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                   7962909                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                         0                       # number of hwrei instructions executed
system.cpu1.kern.mode_switch::kernel                0                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                  0                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                  0                      
system.cpu1.kern.mode_good::user                    0                      
system.cpu1.kern.mode_good::idle                    0                      
system.cpu1.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
system.cpu2.branchPred.lookups                9178120                       # Number of BP lookups
system.cpu2.branchPred.condPredicted          8499449                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           123200                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups             7695654                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                6571533                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            85.392781                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 282084                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             12342                       # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits                          0                       # ITB hits
system.cpu2.dtb.fetch_misses                        0                       # ITB misses
system.cpu2.dtb.fetch_acv                           0                       # ITB acv
system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu2.dtb.read_hits                     3191151                       # DTB read hits
system.cpu2.dtb.read_misses                     11650                       # DTB read misses
system.cpu2.dtb.read_acv                          122                       # DTB read access violations
system.cpu2.dtb.read_accesses                  216295                       # DTB read accesses
system.cpu2.dtb.write_hits                    2013879                       # DTB write hits
system.cpu2.dtb.write_misses                     2626                       # DTB write misses
system.cpu2.dtb.write_acv                         104                       # DTB write access violations
system.cpu2.dtb.write_accesses                  81955                       # DTB write accesses
system.cpu2.dtb.data_hits                     5205030                       # DTB hits
system.cpu2.dtb.data_misses                     14276                       # DTB misses
system.cpu2.dtb.data_acv                          226                       # DTB access violations
system.cpu2.dtb.data_accesses                  298250                       # DTB accesses
system.cpu2.itb.fetch_hits                     370022                       # ITB hits
system.cpu2.itb.fetch_misses                     5569                       # ITB misses
system.cpu2.itb.fetch_acv                         246                       # ITB acv
system.cpu2.itb.fetch_accesses                 375591                       # ITB accesses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.read_acv                            0                       # DTB read access violations
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.write_acv                           0                       # DTB write access violations
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.data_hits                           0                       # DTB hits
system.cpu2.itb.data_misses                         0                       # DTB misses
system.cpu2.itb.data_acv                            0                       # DTB access violations
system.cpu2.itb.data_accesses                       0                       # DTB accesses
system.cpu2.numCycles                        31335688                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles           8331242                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                      37157937                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                    9178120                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches           6853617                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                      8899845                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                 601293                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles               9656250                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles               10264                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles             1927                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        62491                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles        87858                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          258                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  2554389                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                85437                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples          27441825                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.354062                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.292990                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                18541980     67.57%     67.57% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  269924      0.98%     68.55% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                  430608      1.57%     70.12% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                 5041958     18.37%     88.49% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  762355      2.78%     91.27% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  165901      0.60%     91.88% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  191104      0.70%     92.57% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  428586      1.56%     94.14% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                 1609409      5.86%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total            27441825                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.292897                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.185802                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                 8480872                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles              9736053                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                  8290323                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles               308881                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                379812                       # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved              165178                       # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred                12521                       # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts              36770346                       # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts                39237                       # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles                379812                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                 8839767                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                2783657                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles       5759458                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                  8162466                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles              1270789                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts              35635356                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents                 2433                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents                230404                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents               445807                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands           23881418                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups             44614948                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups        44558512                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups            52675                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps             22098169                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                 1783249                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            500707                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts         58904                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                  3714662                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             3352351                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            2102718                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           368829                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          261079                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                  33144056                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             620028                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                 32694445                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued            35243                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        2135274                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined      1079120                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved        437376                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples     27441825                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.191409                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.576872                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           15111094     55.07%     55.07% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            3067205     11.18%     66.24% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            1556680      5.67%     71.92% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            5872597     21.40%     93.32% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4             904620      3.30%     96.61% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5             481374      1.75%     98.37% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6             286422      1.04%     99.41% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             142457      0.52%     99.93% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8              19376      0.07%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total       27441825                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                  33866     13.68%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     13.68% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                112679     45.53%     59.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite               100956     40.79%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass             2440      0.01%      0.01% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu             27019317     82.64%     82.65% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               20282      0.06%     82.71% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     82.71% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd               8426      0.03%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv               1220      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     82.74% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead             3318398     10.15%     92.89% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            2035966      6.23%     99.12% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess            288396      0.88%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total              32694445                       # Type of FU issued
system.cpu2.iq.rate                          1.043361                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                     247501                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.007570                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads          92879210                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes         35788610                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses     32300559                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads             234249                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes            114557                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses       110717                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses              32817438                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                 122068                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          187489                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads       409544                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses          984                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         3929                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       155635                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads         4136                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked        26287                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                379812                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                2011431                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles               204809                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts           35034427                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts           220433                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              3352351                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             2102718                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            550753                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                142349                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                 2108                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          3929                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect         63003                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       127121                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              190124                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts             32537756                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts              3211080                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           156689                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                      1270343                       # number of nop insts executed
system.cpu2.iew.exec_refs                     5232018                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                 7610407                       # Number of branches executed
system.cpu2.iew.exec_stores                   2020938                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.038361                       # Inst execution rate
system.cpu2.iew.wb_sent                      32444193                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                     32411276                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                 18891849                       # num instructions producing a value
system.cpu2.iew.wb_consumers                 22089477                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.034325                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.855242                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        2305077                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         182652                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           175963                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples     27062013                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.207707                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.849174                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     16121128     59.57%     59.57% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      2330838      8.61%     68.18% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1224813      4.53%     72.71% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3      5615394     20.75%     93.46% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       503174      1.86%     95.32% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       185895      0.69%     96.01% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       176248      0.65%     96.66% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7       179513      0.66%     97.32% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8       725010      2.68%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total     27062013                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts            32682976                       # Number of instructions committed
system.cpu2.commit.committedOps              32682976                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       4889890                       # Number of memory references committed
system.cpu2.commit.loads                      2942807                       # Number of loads committed
system.cpu2.commit.membars                      63964                       # Number of memory barriers committed
system.cpu2.commit.branches                   7465437                       # Number of branches committed
system.cpu2.commit.fp_insts                    109562                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                 31237309                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              229028                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass      1167807      3.57%      3.57% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu        26241804     80.29%     83.87% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult          19886      0.06%     83.93% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv               0      0.00%     83.93% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd          8426      0.03%     83.95% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     83.95% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     83.95% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     83.95% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv          1220      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     83.96% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead        3006771      9.20%     93.16% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite       1948666      5.96%     99.12% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess       288396      0.88%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total         32682976                       # Class of committed instruction
system.cpu2.commit.bw_lim_events               725010                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                    61251181                       # The number of ROB reads
system.cpu2.rob.rob_writes                   70355425                       # The number of ROB writes
system.cpu2.timesIdled                         245354                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                        3893863                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  1748379581                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                   31517609                       # Number of Instructions Simulated
system.cpu2.committedOps                     31517609                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              0.994228                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.994228                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.005806                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.005806                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                42812311                       # number of integer regfile reads
system.cpu2.int_regfile_writes               22772429                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    67678                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   67966                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                5406368                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                257490                       # number of misc regfile writes
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei                         0                       # number of hwrei instructions executed
system.cpu2.kern.mode_switch::kernel                0                       # number of protection mode switches
system.cpu2.kern.mode_switch::user                  0                       # number of protection mode switches
system.cpu2.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu2.kern.mode_good::kernel                  0                      
system.cpu2.kern.mode_good::user                    0                      
system.cpu2.kern.mode_good::idle                    0                      
system.cpu2.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
system.cpu2.kern.swap_context                       0                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------