path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.841721                       # Number of seconds simulated
sim_ticks                                1841721066000                       # Number of ticks simulated
final_tick                               1841721066000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 314597                       # Simulator instruction rate (inst/s)
host_op_rate                                   314597                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             8282501609                       # Simulator tick rate (ticks/s)
host_mem_usage                                 307380                       # Number of bytes of host memory used
host_seconds                                   222.36                       # Real time elapsed on the host
sim_insts                                    69954713                       # Number of instructions simulated
sim_ops                                      69954713                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst           472704                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         19360768                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           152256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          2811776                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           294016                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          2696640                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28440512                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       472704                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       152256                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       294016                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          918976                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7466048                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7466048                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst              7386                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            302512                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2379                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             43934                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              4594                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             42135                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                444383                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          116657                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               116657                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              256664                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            10512324                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1440149                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               82670                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1526711                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst              159642                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             1464196                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15442356                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         256664                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          82670                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst         159642                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             498977                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4053843                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4053843                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4053843                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             256664                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           10512324                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1440149                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              82670                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1526711                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst             159642                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            1464196                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19496199                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        109805                       # Total number of read requests seen
system.physmem.writeReqs                        45348                       # Total number of write requests seen
system.physmem.cpureqs                         155202                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                      7027520                       # Total number of bytes read from memory
system.physmem.bytesWritten                   2902272                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                7027520                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                2902272                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        5                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                 42                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                  6903                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                  6718                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                  6604                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                  6507                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                  6918                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                  6911                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                  6891                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                  6873                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                  7028                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                  6837                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                 7200                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                 6974                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                 6884                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                 6958                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                 6841                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                 6753                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  2939                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  2758                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  2643                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  2556                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  2819                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  2749                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  2776                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  2848                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  3031                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  2909                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 3192                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 2889                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 2835                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 2902                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 2803                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 2699                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           7                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1840708761500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  109805                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  45348                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                     80824                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      9409                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      5385                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1978                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      1285                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      1199                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1092                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1088                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1066                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1043                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      617                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      590                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      574                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      554                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      550                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      573                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      668                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      614                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      376                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      310                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      1246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      1413                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      1617                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      1638                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      1833                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      1972                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      1971                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      1969                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      1965                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      1972                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     1970                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     1968                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     1965                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     1964                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     1962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1960                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1959                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1957                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     1954                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     1953                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     1953                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     1951                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     1950                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                      781                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      589                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      373                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                      350                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        8                       # What write queue length does an incoming req see
system.physmem.totQLat                     2404806500                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                4407346500                       # Sum of mem lat for all requests
system.physmem.totBusLat                    549000000                       # Total cycles spent in databus access
system.physmem.totBankLat                  1453540000                       # Total cycles spent in bank access
system.physmem.avgQLat                       21901.70                       # Average queueing delay per request
system.physmem.avgBankLat                    13238.07                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  40139.77                       # Average memory access latency
system.physmem.avgRdBW                           3.82                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           1.58                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   3.82                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.58                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                         0.17                       # Average write queue length over time
system.physmem.readRowHits                      99784                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     34161                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.88                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.33                       # Row buffer hit rate for writes
system.physmem.avgGap                     11863829.65                       # Average gap between requests
system.l2c.replacements                        337457                       # number of replacements
system.l2c.tagsinuse                     65420.293999                       # Cycle average of tags in use
system.l2c.total_refs                         2475568                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        402619                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          6.148662                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                     614754000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        54855.924450                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          2280.990805                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          2631.435167                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst           619.089376                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data           660.267485                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst          2247.126162                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data          2125.460555                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.837035                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.034805                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.040153                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.009447                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.010075                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst            0.034288                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data            0.032432                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.998234                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst             516823                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             491434                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             126840                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              83916                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst             295941                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data             241655                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1756609                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          836144                       # number of Writeback hits
system.l2c.Writeback_hits::total               836144                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data               4                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   8                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data             1                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 1                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            92196                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            27303                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            67454                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               186953                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              516823                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              583630                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              126840                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              111219                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              295941                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              309109                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1943562                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             516823                       # number of overall hits
system.l2c.overall_hits::cpu0.data             583630                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             126840                       # number of overall hits
system.l2c.overall_hits::cpu1.data             111219                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             295941                       # number of overall hits
system.l2c.overall_hits::cpu2.data             309109                       # number of overall hits
system.l2c.overall_hits::total                1943562                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst             7386                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           225254                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             2379                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data            23011                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst             4594                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data            24976                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               287600                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data             8                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            12                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                20                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          77534                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          20972                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          17259                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             115765                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst              7386                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            302788                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2379                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             43983                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              4594                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             42235                       # number of demand (read+write) misses
system.l2c.demand_misses::total                403365                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst             7386                       # number of overall misses
system.l2c.overall_misses::cpu0.data           302788                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2379                       # number of overall misses
system.l2c.overall_misses::cpu1.data            43983                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             4594                       # number of overall misses
system.l2c.overall_misses::cpu2.data            42235                       # number of overall misses
system.l2c.overall_misses::total               403365                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst    157366500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data   1048946500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst    324027500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data   1120293500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     2650634000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data       290500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       290500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    973350000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   1284432500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2257782500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst    157366500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   2022296500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    324027500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   2404726000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      4908416500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst    157366500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   2022296500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    324027500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   2404726000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     4908416500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         524209                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         716688                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         129219                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         106927                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst         300535                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data         266631                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2044209                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       836144                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           836144                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           11                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data            1                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           16                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              28                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       169730                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        48275                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        84713                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           302718                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          524209                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          886418                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          129219                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          155202                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          300535                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          351344                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2346927                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         524209                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         886418                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         129219                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         155202                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         300535                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         351344                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2346927                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.014090                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.314299                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.018411                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.215203                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.015286                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.093673                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.140690                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.727273                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.750000                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.714286                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.456808                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.434428                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.203735                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.382419                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.014090                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.341586                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.018411                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.283392                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.015286                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.120210                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.171869                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.014090                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.341586                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.018411                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.283392                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.015286                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.120210                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.171869                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 66148.171501                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 45584.568250                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70532.760122                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 44854.800609                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total  9216.390821                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 24208.333333                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total        14525                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46411.882510                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74421.026711                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 19503.152939                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 66148.171501                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 45979.048723                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 70532.760122                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 56936.805967                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 12168.672294                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 66148.171501                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 45979.048723                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 70532.760122                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 56936.805967                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 12168.672294                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               75145                       # number of writebacks
system.l2c.writebacks::total                    75145                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu1.inst         2379                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data        23011                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst         4594                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data        24976                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           54960                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           12                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           12                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        20972                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        17259                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         38231                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2379                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        43983                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         4594                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        42235                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            93191                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2379                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        43983                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         4594                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        42235                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           93191                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    127442377                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    765878734                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    266759238                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data    816997015                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1977077364                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       276009                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total       276009                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    714450960                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1073803133                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1788254093                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    127442377                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1480329694                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    266759238                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   1890800148                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   3765331457                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    127442377                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1480329694                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    266759238                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   1890800148                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   3765331457                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    269358500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    331052000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total    600410500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    336186000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    405849000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total    742035000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    605544500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data    736901000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   1342445500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.018411                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.215203                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.015286                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.093673                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.026886                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.750000                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.434428                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.203735                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.126292                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.018411                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.283392                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.015286                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.120210                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.039708                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.018411                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.283392                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.015286                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.120210                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.039708                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 53569.725515                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 33283.157360                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58066.878102                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 32711.283432                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 35973.023362                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 23000.750000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23000.750000                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34066.896815                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62216.995944                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 46774.975622                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 53569.725515                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33656.860469                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58066.878102                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 44768.560388                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40404.453831                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 53569.725515                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33656.860469                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58066.878102                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 44768.560388                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40404.453831                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41685                       # number of replacements
system.iocache.tagsinuse                     1.255737                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1693878100000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       1.255737                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.078484                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.078484                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide      9177998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total      9177998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide   4330975325                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   4330975325                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide   4340153323                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4340153323                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide   4340153323                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4340153323                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 53052.011561                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104230.249446                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 104230.249446                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 104018.054476                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 104018.054476                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 104018.054476                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 104018.054476                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        117509                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                11192                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.499375                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide           69                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total           69                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        16768                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        16768                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        16837                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        16837                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        16837                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        16837                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5589249                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total      5589249                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   3458522887                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   3458522887                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   3464112136                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   3464112136                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   3464112136                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   3464112136                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.398844                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.398844                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide     0.403543                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total     0.403543                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide     0.403523                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.403523                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide     0.403523                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.403523                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81003.608696                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 81003.608696                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 206257.328662                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 206257.328662                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205744.024232                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 205744.024232                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205744.024232                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 205744.024232                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     4882934                       # DTB read hits
system.cpu0.dtb.read_misses                      6016                       # DTB read misses
system.cpu0.dtb.read_acv                          120                       # DTB read access violations
system.cpu0.dtb.read_accesses                  427387                       # DTB read accesses
system.cpu0.dtb.write_hits                    3510109                       # DTB write hits
system.cpu0.dtb.write_misses                      663                       # DTB write misses
system.cpu0.dtb.write_acv                          82                       # DTB write access violations
system.cpu0.dtb.write_accesses                 162920                       # DTB write accesses
system.cpu0.dtb.data_hits                     8393043                       # DTB hits
system.cpu0.dtb.data_misses                      6679                       # DTB misses
system.cpu0.dtb.data_acv                          202                       # DTB access violations
system.cpu0.dtb.data_accesses                  590307                       # DTB accesses
system.cpu0.itb.fetch_hits                    2747668                       # ITB hits
system.cpu0.itb.fetch_misses                     3002                       # ITB misses
system.cpu0.itb.fetch_acv                         100                       # ITB acv
system.cpu0.itb.fetch_accesses                2750670                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       928534019                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   33030135                       # Number of instructions committed
system.cpu0.committedOps                     33030135                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             30904296                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                168660                       # Number of float alu accesses
system.cpu0.num_func_calls                     809909                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      4463035                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    30904296                       # number of integer instructions
system.cpu0.num_fp_insts                       168660                       # number of float instructions
system.cpu0.num_int_register_reads           43221651                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          22562663                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads               87082                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes              88661                       # number of times the floating registers were written
system.cpu0.num_mem_refs                      8422848                       # number of memory refs
system.cpu0.num_load_insts                    4904051                       # Number of load instructions
system.cpu0.num_store_insts                   3518797                       # Number of store instructions
system.cpu0.num_idle_cycles              214028158129.505707                       # Number of idle cycles
system.cpu0.num_busy_cycles              -213099624110.505707                       # Number of busy cycles
system.cpu0.not_idle_fraction             -229.501149                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                  230.501149                       # Percentage of idle cycles
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6421                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    211352                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   74794     40.97%     40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1878      1.03%     42.11% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                 105677     57.89%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              182552                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    73427     49.30%     49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1878      1.26%     50.70% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   73427     49.30%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               148935                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1818574542500     98.74%     98.74% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               39495500      0.00%     98.75% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              364949500      0.02%     98.77% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            22741309000      1.23%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1841720296500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.981723                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.694825                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.815850                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      2.45%      2.45% # number of syscalls executed
system.cpu0.kern.syscall::3                        30      9.20%     11.66% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.23%     12.88% # number of syscalls executed
system.cpu0.kern.syscall::6                        42     12.88%     25.77% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.31%     26.07% # number of syscalls executed
system.cpu0.kern.syscall::15                        1      0.31%     26.38% # number of syscalls executed
system.cpu0.kern.syscall::17                       15      4.60%     30.98% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      3.07%     34.05% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      1.84%     35.89% # number of syscalls executed
system.cpu0.kern.syscall::23                        4      1.23%     37.12% # number of syscalls executed
system.cpu0.kern.syscall::24                        6      1.84%     38.96% # number of syscalls executed
system.cpu0.kern.syscall::33                       11      3.37%     42.33% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.61%     42.94% # number of syscalls executed
system.cpu0.kern.syscall::45                       54     16.56%     59.51% # number of syscalls executed
system.cpu0.kern.syscall::47                        6      1.84%     61.35% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      3.07%     64.42% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      3.07%     67.48% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.31%     67.79% # number of syscalls executed
system.cpu0.kern.syscall::59                        7      2.15%     69.94% # number of syscalls executed
system.cpu0.kern.syscall::71                       54     16.56%     86.50% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      0.92%     87.42% # number of syscalls executed
system.cpu0.kern.syscall::74                       16      4.91%     92.33% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.31%     92.64% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      0.92%     93.56% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      2.76%     96.32% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.61%     96.93% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.61%     97.55% # number of syscalls executed
system.cpu0.kern.syscall::132                       4      1.23%     98.77% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.61%     99.39% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.61%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   326                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 4174      2.17%      2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi                      54      0.03%      2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.21% # number of callpals executed
system.cpu0.kern.callpal::swpipl               175295     91.20%     93.41% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6782      3.53%     96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     7      0.00%     96.94% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.00%     96.94% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.95% # number of callpals executed
system.cpu0.kern.callpal::rti                    5175      2.69%     99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys                 515      0.27%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     181      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                192206                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             5921                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1738                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle               2094                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1907                      
system.cpu0.kern.mode_good::user                 1738                      
system.cpu0.kern.mode_good::idle                  169                      
system.cpu0.kern.mode_switch_good::kernel     0.322074                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle      0.080707                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.391059                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel       29798472500      1.62%      1.62% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          2570740000      0.14%      1.76% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle        1809351079500     98.24%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    4175                       # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.icache.replacements                953317                       # number of replacements
system.cpu0.icache.tagsinuse               511.202573                       # Cycle average of tags in use
system.cpu0.icache.total_refs                42520473                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                953828                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                 44.578764                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           10247489000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   251.172377                       # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst    83.809654                       # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu2.inst   176.220543                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.490571                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst     0.163691                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu2.inst     0.344181                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.998443                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst     32512787                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      7733014                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      2274672                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       42520473                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     32512787                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      7733014                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      2274672                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        42520473                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     32512787                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      7733014                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      2274672                       # number of overall hits
system.cpu0.icache.overall_hits::total       42520473                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       524229                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       129219                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       317357                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       970805                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       524229                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       129219                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       317357                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        970805                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       524229                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       129219                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       317357                       # number of overall misses
system.cpu0.icache.overall_misses::total       970805                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1820764500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4451463485                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   6272227985                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   1820764500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   4451463485                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   6272227985                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   1820764500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   4451463485                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   6272227985                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     33037016                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      7862233                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      2592029                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     43491278                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     33037016                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      7862233                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      2592029                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     43491278                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     33037016                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      7862233                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      2592029                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     43491278                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015868                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016435                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122436                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.022322                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015868                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016435                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.122436                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.022322                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015868                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016435                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122436                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.022322                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14090.532352                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14026.674959                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  6460.852576                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14090.532352                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14026.674959                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  6460.852576                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14090.532352                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14026.674959                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  6460.852576                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         7042                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              180                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    39.122222                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16804                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        16804                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        16804                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        16804                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        16804                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        16804                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       129219                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       300553                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       429772                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       129219                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       300553                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       429772                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       129219                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       300553                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       429772                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1562326500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3669413485                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   5231739985                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1562326500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3669413485                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   5231739985                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1562326500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3669413485                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   5231739985                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016435                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.115953                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009882                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016435                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.115953                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.009882                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016435                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.115953                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.009882                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12090.532352                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12208.873260                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12173.291850                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12090.532352                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12208.873260                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12173.291850                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12090.532352                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12208.873260                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12173.291850                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1392417                       # number of replacements
system.cpu0.dcache.tagsinuse               511.997811                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                13323507                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1392929                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                  9.565101                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              10840000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   244.771660                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data    89.928637                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu2.data   177.297515                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.478070                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data     0.175642                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu2.data     0.346284                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.999996                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      4060433                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      1097155                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      2407299                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        7564887                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3213478                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data       859336                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      1302261                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       5375075                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       116788                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19286                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        48129                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       184203                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       125890                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21377                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data        52004                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       199271                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      7273911                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      1956491                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      3709560                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        12939962                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      7273911                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      1956491                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      3709560                       # number of overall hits
system.cpu0.dcache.overall_hits::total       12939962                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       707025                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       104703                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       545654                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1357382                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       169741                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        48276                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       557910                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       775927                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9663                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2224                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         6949                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        18836                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       876766                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       152979                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data      1103564                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2133309                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       876766                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       152979                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1103564                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2133309                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2182842500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9423315500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  11606158000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1391881500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  14686223273                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  16078104773                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     29301500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    104213500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    133515000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        13000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total        13000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   3574724000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  24109538773                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  27684262773                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   3574724000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  24109538773                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  27684262773                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      4767458                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      1201858                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      2952953                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8922269                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      3383219                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data       907612                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      1860171                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      6151002                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       126451                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21510                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        55078                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       203039                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       125890                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21377                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        52005                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       199272                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data      8150677                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      2109470                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      4813124                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     15073271                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data      8150677                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      2109470                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      4813124                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     15073271                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.148302                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.087118                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.184782                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.152134                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.050171                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.053190                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.299924                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.126146                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.076417                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.103394                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.126167                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.092770                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000019                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000005                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.107570                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.072520                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.229282                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.141529                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.107570                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.072520                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.229282                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.141529                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 20847.946095                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17269.763440                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total  8550.399224                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 28831.748695                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26323.642295                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20721.156466                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13175.134892                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14996.906030                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  7088.288384                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23367.416443                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21846.978311                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 12977.146195                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23367.416443                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21846.978311                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12977.146195                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       427872                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         2656                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            16826                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    25.429217                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   379.428571                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       836144                       # number of writebacks
system.cpu0.dcache.writebacks::total           836144                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       284274                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       284274                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       473431                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       473431                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1450                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1450                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       757705                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       757705                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       757705                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       757705                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       104703                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       261380                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       366083                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        48276                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        84479                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       132755                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2224                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5499                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7723                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       152979                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       345859                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       498838                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       152979                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       345859                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       498838                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1973436500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4297066000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6270502500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1295329500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2136901128                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   3432230628                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     24853500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     70377000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     95230500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        11000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        11000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3268766000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   6433967128                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   9702733128                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3268766000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   6433967128                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   9702733128                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    287559000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    353651000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    641210000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    356203000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    430620000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    786823000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    643762000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    784271000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1428033000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.087118                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.088515                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.041030                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.053190                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.045415                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.021583                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.103394                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.099840                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.038037                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000019                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.072520                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.071857                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.033094                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.072520                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.071857                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.033094                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18847.946095                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16439.918892                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17128.636129                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26831.748695                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25295.057091                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25853.870875                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11175.134892                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12798.145117                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.765247                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21367.416443                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18602.861652                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19450.669612                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21367.416443                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18602.861652                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19450.669612                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1221065                       # DTB read hits
system.cpu1.dtb.read_misses                      1489                       # DTB read misses
system.cpu1.dtb.read_acv                           40                       # DTB read access violations
system.cpu1.dtb.read_accesses                  143781                       # DTB read accesses
system.cpu1.dtb.write_hits                     929390                       # DTB write hits
system.cpu1.dtb.write_misses                      202                       # DTB write misses
system.cpu1.dtb.write_acv                          24                       # DTB write access violations
system.cpu1.dtb.write_accesses                  59266                       # DTB write accesses
system.cpu1.dtb.data_hits                     2150455                       # DTB hits
system.cpu1.dtb.data_misses                      1691                       # DTB misses
system.cpu1.dtb.data_acv                           64                       # DTB access violations
system.cpu1.dtb.data_accesses                  203047                       # DTB accesses
system.cpu1.itb.fetch_hits                     872017                       # ITB hits
system.cpu1.itb.fetch_misses                      756                       # ITB misses
system.cpu1.itb.fetch_acv                          43                       # ITB acv
system.cpu1.itb.fetch_accesses                 872773                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                       953614996                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                    7860477                       # Number of instructions committed
system.cpu1.committedOps                      7860477                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses              7311992                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                 45303                       # Number of float alu accesses
system.cpu1.num_func_calls                     212165                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts       960179                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                     7311992                       # number of integer instructions
system.cpu1.num_fp_insts                        45303                       # number of float instructions
system.cpu1.num_int_register_reads           10165443                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           5319467                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads               24490                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              24717                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      2158115                       # number of memory refs
system.cpu1.num_load_insts                    1226297                       # Number of load instructions
system.cpu1.num_store_insts                    931818                       # Number of store instructions
system.cpu1.num_idle_cycles              -703122010.262243                       # Number of idle cycles
system.cpu1.num_busy_cycles              1656737006.262243                       # Number of busy cycles
system.cpu1.not_idle_fraction                1.737323                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                   -0.737323                       # Percentage of idle cycles
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                         0                       # number of hwrei instructions executed
system.cpu1.kern.mode_switch::kernel                0                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                  0                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                  0                      
system.cpu1.kern.mode_good::user                    0                      
system.cpu1.kern.mode_good::idle                    0                      
system.cpu1.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
system.cpu2.branchPred.lookups                8370437                       # Number of BP lookups
system.cpu2.branchPred.condPredicted          7682240                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           128031                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups             6854257                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                5743720                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            83.797850                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 284899                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             14987                       # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits                          0                       # ITB hits
system.cpu2.dtb.fetch_misses                        0                       # ITB misses
system.cpu2.dtb.fetch_acv                           0                       # ITB acv
system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu2.dtb.read_hits                     3211638                       # DTB read hits
system.cpu2.dtb.read_misses                     11756                       # DTB read misses
system.cpu2.dtb.read_acv                          123                       # DTB read access violations
system.cpu2.dtb.read_accesses                  216825                       # DTB read accesses
system.cpu2.dtb.write_hits                    1985602                       # DTB write hits
system.cpu2.dtb.write_misses                     2511                       # DTB write misses
system.cpu2.dtb.write_acv                         137                       # DTB write access violations
system.cpu2.dtb.write_accesses                  81903                       # DTB write accesses
system.cpu2.dtb.data_hits                     5197240                       # DTB hits
system.cpu2.dtb.data_misses                     14267                       # DTB misses
system.cpu2.dtb.data_acv                          260                       # DTB access violations
system.cpu2.dtb.data_accesses                  298728                       # DTB accesses
system.cpu2.itb.fetch_hits                     370869                       # ITB hits
system.cpu2.itb.fetch_misses                     5705                       # ITB misses
system.cpu2.itb.fetch_acv                         274                       # ITB acv
system.cpu2.itb.fetch_accesses                 376574                       # ITB accesses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.read_acv                            0                       # DTB read access violations
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.write_acv                           0                       # DTB write access violations
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.data_hits                           0                       # DTB hits
system.cpu2.itb.data_misses                         0                       # DTB misses
system.cpu2.itb.data_acv                            0                       # DTB access violations
system.cpu2.itb.data_accesses                       0                       # DTB accesses
system.cpu2.numCycles                        30454355                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles           8502723                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                      34791371                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                    8370437                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches           6028619                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                      8097928                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                 618452                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles               9649671                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles               10614                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles             1974                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        63437                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles        88147                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          485                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  2592037                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                89025                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples          26817742                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.297327                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.307851                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                18719814     69.80%     69.80% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  271918      1.01%     70.82% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                  439106      1.64%     72.46% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                 4240914     15.81%     88.27% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  731900      2.73%     91.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  166811      0.62%     91.62% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  194731      0.73%     92.35% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  431926      1.61%     93.96% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                 1620622      6.04%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total            26817742                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.274852                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.142410                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                 8640997                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles              9744638                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                  7501940                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles               293665                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                390587                       # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved              167981                       # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred                12867                       # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts              34389263                       # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts                40403                       # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles                390587                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                 8994385                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                2850333                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles       5733998                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                  7360278                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles              1242256                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts              33240737                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents                 2380                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents                234906                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents               409580                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands           22320164                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups             41423386                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups        41259446                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups           163940                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps             20500425                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                 1819739                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            502711                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts         59638                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                  3682174                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             3369954                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            2075842                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           372990                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          254270                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                  30724821                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             626542                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                 30272457                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued            30970                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        2165066                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined      1087715                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved        442386                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples     26817742                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.128822                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.564509                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           15272797     56.95%     56.95% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            3099841     11.56%     68.51% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            1551477      5.79%     74.29% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            5057037     18.86%     93.15% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4             907037      3.38%     96.53% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5             485633      1.81%     98.34% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6             283575      1.06%     99.40% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             141972      0.53%     99.93% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8              18373      0.07%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total       26817742                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                  34129     13.74%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     13.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                111357     44.84%     58.58% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite               102854     41.42%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass             2448      0.01%      0.01% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu             24602631     81.27%     81.28% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               20294      0.07%     81.35% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     81.35% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd               8465      0.03%     81.37% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     81.37% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     81.37% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     81.37% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv               1224      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     81.38% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead             3340354     11.03%     92.41% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            2007868      6.63%     99.04% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess            289173      0.96%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total              30272457                       # Type of FU issued
system.cpu2.iq.rate                          0.994027                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                     248340                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.008203                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads          87406741                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes         33405587                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses     29873950                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads             235225                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes            114899                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses       111509                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses              30395868                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                 122481                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          188565                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads       411297                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses          939                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         4131                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       160227                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads         4708                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked        24260                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                390587                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                2070216                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles               210596                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts           32630441                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts           224813                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              3369954                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             2075842                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            556425                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                148713                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                 2116                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          4131                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect         65748                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       128933                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              194681                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts             30112166                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts              3231643                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           160291                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                      1279078                       # number of nop insts executed
system.cpu2.iew.exec_refs                     5224243                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                 6789433                       # Number of branches executed
system.cpu2.iew.exec_stores                   1992600                       # Number of stores executed
system.cpu2.iew.exec_rate                    0.988764                       # Inst execution rate
system.cpu2.iew.wb_sent                      30017965                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                     29985459                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                 17323993                       # num instructions producing a value
system.cpu2.iew.wb_consumers                 20546016                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      0.984603                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.843180                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        2350466                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         184156                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           180720                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples     26427155                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.144119                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.849310                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     16325181     61.77%     61.77% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      2317842      8.77%     70.54% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1215370      4.60%     75.14% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3      4792789     18.14%     93.28% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       500443      1.89%     95.17% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       186108      0.70%     95.88% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       178909      0.68%     96.55% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7       180996      0.68%     97.24% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8       729517      2.76%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total     26427155                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts            30235823                       # Number of instructions committed
system.cpu2.commit.committedOps              30235823                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       4874272                       # Number of memory references committed
system.cpu2.commit.loads                      2958657                       # Number of loads committed
system.cpu2.commit.membars                      64665                       # Number of memory barriers committed
system.cpu2.commit.branches                   6641301                       # Number of branches committed
system.cpu2.commit.fp_insts                    110294                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                 28781664                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              230734                       # Number of function calls committed.
system.cpu2.commit.bw_lim_events               729517                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                    58211181                       # The number of ROB reads
system.cpu2.rob.rob_writes                   65562875                       # The number of ROB writes
system.cpu2.timesIdled                         242498                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                        3636613                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  1745370399                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                   29064101                       # Number of Instructions Simulated
system.cpu2.committedOps                     29064101                       # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total             29064101                       # Number of Instructions Simulated
system.cpu2.cpi                              1.047834                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        1.047834                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.954350                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.954350                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                39595533                       # number of integer regfile reads
system.cpu2.int_regfile_writes               21195830                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    68078                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   68404                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                4592506                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                258747                       # number of misc regfile writes
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei                         0                       # number of hwrei instructions executed
system.cpu2.kern.mode_switch::kernel                0                       # number of protection mode switches
system.cpu2.kern.mode_switch::user                  0                       # number of protection mode switches
system.cpu2.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu2.kern.mode_good::kernel                  0                      
system.cpu2.kern.mode_good::user                    0                      
system.cpu2.kern.mode_good::idle                    0                      
system.cpu2.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
system.cpu2.kern.swap_context                       0                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------