path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.842705                       # Number of seconds simulated
sim_ticks                                1842705252000                       # Number of ticks simulated
final_tick                               1842705252000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 308319                       # Simulator instruction rate (inst/s)
host_op_rate                                   308319                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             7821132493                       # Simulator tick rate (ticks/s)
host_mem_usage                                 307864                       # Number of bytes of host memory used
host_seconds                                   235.61                       # Real time elapsed on the host
sim_insts                                    72641883                       # Number of instructions simulated
sim_ops                                      72641883                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst           488448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         20049216                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           147328                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          2290432                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           282112                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          2525760                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28435648                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       488448                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       147328                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       282112                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          917888                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7459584                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7459584                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst              7632                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            313269                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2302                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             35788                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              4408                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             39465                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                444307                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          116556                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               116556                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              265071                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            10880316                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1439379                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               79952                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1242973                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst              153097                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             1370680                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15431468                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         265071                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          79952                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst         153097                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             498120                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4048170                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4048170                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4048170                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             265071                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           10880316                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1439379                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              79952                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1242973                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst             153097                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            1370680                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19479638                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         99238                       # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs                        44800                       # Total number of write requests accepted by DRAM controller
system.physmem.readBursts                       99238                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts                      44800                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead                      6351232                       # Total number of bytes read from memory
system.physmem.bytesWritten                   2867200                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                6351232                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                2867200                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       11                       # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite                 44                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                  6232                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                  6043                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                  6220                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                  6348                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                  5767                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                  6398                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                  6152                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                  6059                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                  6519                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                  6372                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                 6626                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                 6008                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                 5967                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                 6231                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                 6240                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                 6045                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  2861                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  2670                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  2847                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  2964                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  2622                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  3000                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  2942                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  2703                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  3213                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  2742                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 3001                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 2449                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 2468                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 2705                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 2852                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 2761                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1841692926500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                   99238                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  44800                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                     67489                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     12659                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      6294                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      2227                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      1387                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      1264                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       650                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       635                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       621                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       612                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      600                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      599                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      588                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      864                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      994                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      932                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      505                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      183                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       84                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       39                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      1381                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      1406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      1848                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      1963                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      1959                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      1957                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      1956                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      1952                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      1949                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      1949                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     1946                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     1943                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     1942                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     1941                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     1939                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1937                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1937                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1934                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     1933                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     1931                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     1929                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     1928                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     1926                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                      626                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      568                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        15760                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      584.832487                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     171.909397                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev    1926.760563                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67           6603     41.90%     41.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131         2572     16.32%     58.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195         1454      9.23%     67.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259          899      5.70%     73.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323          642      4.07%     77.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387          535      3.39%     80.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451          370      2.35%     82.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515          312      1.98%     84.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579          250      1.59%     86.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643          195      1.24%     87.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707          235      1.49%     89.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771          190      1.21%     90.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835          101      0.64%     91.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899           71      0.45%     91.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963           63      0.40%     91.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027           80      0.51%     92.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091           51      0.32%     92.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155           28      0.18%     92.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219           32      0.20%     93.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283           74      0.47%     93.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347           51      0.32%     93.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411           34      0.22%     94.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475          173      1.10%     95.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539           86      0.55%     95.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603           27      0.17%     95.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667           14      0.09%     96.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731           12      0.08%     96.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795           22      0.14%     96.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859           10      0.06%     96.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923            4      0.03%     96.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987            2      0.01%     96.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051            6      0.04%     96.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115            7      0.04%     96.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179            1      0.01%     96.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307            3      0.02%     96.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371            1      0.01%     96.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435            2      0.01%     96.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499            1      0.01%     96.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563            2      0.01%     96.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627            1      0.01%     96.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691            1      0.01%     96.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819            2      0.01%     96.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883            3      0.02%     96.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011            3      0.02%     96.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075            1      0.01%     96.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523            1      0.01%     96.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587            1      0.01%     96.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651            2      0.01%     96.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715            1      0.01%     96.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907            2      0.01%     96.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227            1      0.01%     96.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4675            1      0.01%     96.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931            1      0.01%     96.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059            2      0.01%     96.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5315            2      0.01%     96.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5699            1      0.01%     96.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6467            1      0.01%     96.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7811            1      0.01%     96.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8003            1      0.01%     96.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195          383      2.43%     99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11456-11459            1      0.01%     99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13827            1      0.01%     99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14016-14019            1      0.01%     99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14400-14403            1      0.01%     99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15040-15043            2      0.01%     99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363            6      0.04%     99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15552-15555            1      0.01%     99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15744-15747            1      0.01%     99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387          111      0.70%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16448-16451            1      0.01%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16515            2      0.01%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16643            3      0.02%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16832-16835            1      0.01%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17088-17091            1      0.01%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          15760                       # Bytes accessed per row activation
system.physmem.totQLat                     1910826000                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                3572864750                       # Sum of mem lat for all requests
system.physmem.totBusLat                    496135000                       # Total cycles spent in databus access
system.physmem.totBankLat                  1165903750                       # Total cycles spent in bank access
system.physmem.avgQLat                       19257.12                       # Average queueing delay per request
system.physmem.avgBankLat                    11749.86                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  36006.98                       # Average memory access latency
system.physmem.avgRdBW                           3.45                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           1.56                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   3.45                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.56                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                         0.17                       # Average write queue length over time
system.physmem.readRowHits                      92920                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     35346                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.64                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  78.90                       # Row buffer hit rate for writes
system.physmem.avgGap                     12786160.09                       # Average gap between requests
system.membus.throughput                     19523578                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq               45592                       # Transaction distribution
system.membus.trans_dist::ReadResp              45560                       # Transaction distribution
system.membus.trans_dist::WriteReq               3756                       # Transaction distribution
system.membus.trans_dist::WriteResp              3756                       # Transaction distribution
system.membus.trans_dist::Writeback             44800                       # Transaction distribution
system.membus.trans_dist::UpgradeReq               46                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              47                       # Transaction distribution
system.membus.trans_dist::ReadExReq             56741                       # Transaction distribution
system.membus.trans_dist::ReadExResp            56741                       # Transaction distribution
system.membus.trans_dist::BadAddressError           32                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        13322                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       191660                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           64                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       205046                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        51865                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        51865                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 256911                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        15754                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      7009472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total      7025226                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2208960                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      2208960                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total             9234186                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               35966088                       # Total data (bytes)
system.membus.snoop_data_through_bus            10112                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            12465000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           516080000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy               39000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy          771793954                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          156435750                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.l2c.tags.replacements                   337384                       # number of replacements
system.l2c.tags.tagsinuse                65423.390976                       # Cycle average of tags in use
system.l2c.tags.total_refs                    2471195                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   402547                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     6.138898                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                614754000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   54840.022307                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     2455.785986                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2733.317890                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      573.564095                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      593.217562                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     2104.783507                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     2122.699630                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.836792                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.037472                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.041707                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.008752                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.009052                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.032116                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.032390                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.998282                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst             518817                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             493229                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             124693                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              83730                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst             293247                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data             239325                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1753041                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          835257                       # number of Writeback hits
system.l2c.Writeback_hits::total               835257                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   7                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data             1                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 1                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            92556                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            26552                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            67733                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               186841                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              518817                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              585785                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              124693                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              110282                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              293247                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              307058                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1939882                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             518817                       # number of overall hits
system.l2c.overall_hits::cpu0.data             585785                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             124693                       # number of overall hits
system.l2c.overall_hits::cpu1.data             110282                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             293247                       # number of overall hits
system.l2c.overall_hits::cpu2.data             307058                       # number of overall hits
system.l2c.overall_hits::total                1939882                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst             7632                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           237318                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             2302                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data            17365                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst             4408                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data            18542                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               287567                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data             8                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            11                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                19                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu2.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          76225                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          18470                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          21026                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             115721                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst              7632                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            313543                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2302                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             35835                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              4408                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             39568                       # number of demand (read+write) misses
system.l2c.demand_misses::total                403288                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst             7632                       # number of overall misses
system.l2c.overall_misses::cpu0.data           313543                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2302                       # number of overall misses
system.l2c.overall_misses::cpu1.data            35835                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             4408                       # number of overall misses
system.l2c.overall_misses::cpu2.data            39568                       # number of overall misses
system.l2c.overall_misses::total               403288                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst    186892499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data   1138263250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst    380152250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data   1198688249                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     2903996248                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data       263498                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       263498                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1209958491                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   1715474224                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2925432715                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst    186892499                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   2348221741                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    380152250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   2914162473                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      5829428963                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst    186892499                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   2348221741                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    380152250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   2914162473                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     5829428963                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         526449                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         730547                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         126995                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         101095                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst         297655                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data         257867                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2040608                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       835257                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           835257                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           11                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data            1                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           14                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              26                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       168781                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        45022                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        88759                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           302562                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          526449                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          899328                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          126995                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          146117                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          297655                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          346626                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2343170                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         526449                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         899328                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         126995                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         146117                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         297655                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         346626                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2343170                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.014497                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.324850                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.018127                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.171769                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.014809                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.071905                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.140922                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.727273                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.785714                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.730769                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu2.data     0.500000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.451621                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.410244                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.236889                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.382470                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.014497                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.348641                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.018127                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.245249                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.014809                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.114152                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.172112                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.014497                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.348641                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.018127                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.245249                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.014809                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.114152                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.172112                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81187.010860                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 65549.280161                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 86241.436025                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 64647.192806                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 10098.503124                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 23954.363636                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 13868.315789                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 65509.393124                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81588.234757                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 25280.050423                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 81187.010860                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 65528.721669                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 86241.436025                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 73649.476168                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 14454.754327                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 81187.010860                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 65528.721669                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 86241.436025                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 73649.476168                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 14454.754327                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               75044                       # number of writebacks
system.l2c.writebacks::total                    75044                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu1.inst         2302                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data        17365                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst         4408                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data        18542                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           42617                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           11                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           11                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu2.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        18470                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        21026                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         39496                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2302                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        35835                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         4408                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        39568                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            82113                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2302                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        35835                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         4408                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        39568                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           82113                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    157803001                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    920718250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    324243750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data    970102251                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   2372867252                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       261008                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total       261008                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data        10001                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total        10001                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    978413509                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1456000776                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2434414285                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    157803001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1899131759                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    324243750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   2426103027                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   4807281537                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    157803001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1899131759                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    324243750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   2426103027                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   4807281537                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    275693000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    292819000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total    568512000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    341668500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    404628500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total    746297000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    617361500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data    697447500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   1314809000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.018127                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.171769                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.014809                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.071905                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.020884                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.785714                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.423077                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.410244                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.236889                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.130539                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.018127                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.245249                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014809                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.114152                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.035044                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.018127                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.245249                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014809                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.114152                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.035044                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68550.391399                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 53021.494385                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73558.019510                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 52319.180833                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 55678.889927                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        23728                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total        23728                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 52973.119058                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69247.635118                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 61636.983112                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 68550.391399                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52996.560876                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73558.019510                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61314.775248                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 58544.707135                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 68550.391399                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52996.560876                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73558.019510                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61314.775248                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 58544.707135                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                41685                       # number of replacements
system.iocache.tags.tagsinuse                1.254957                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1694872745000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.254957                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.078435                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.078435                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide      9629212                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total      9629212                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide   4353407559                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   4353407559                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide   4363036771                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4363036771                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide   4363036771                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4363036771                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55660.184971                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 55660.184971                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104770.108755                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 104770.108755                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 104566.489419                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 104566.489419                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 104566.489419                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 104566.489419                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        114649                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                11461                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.003403                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide           70                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total           70                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        17280                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        17280                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        17350                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        17350                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        17350                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        17350                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5987712                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total      5987712                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   3454277559                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   3454277559                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   3460265271                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   3460265271                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   3460265271                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   3460265271                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.404624                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide     0.415864                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total     0.415864                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide     0.415818                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.415818                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide     0.415818                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.415818                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 85538.742857                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 85538.742857                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199900.321701                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 199900.321701                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199438.920519                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 199438.920519                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199438.920519                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 199438.920519                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     4909978                       # DTB read hits
system.cpu0.dtb.read_misses                      6100                       # DTB read misses
system.cpu0.dtb.read_acv                          126                       # DTB read access violations
system.cpu0.dtb.read_accesses                  428319                       # DTB read accesses
system.cpu0.dtb.write_hits                    3504299                       # DTB write hits
system.cpu0.dtb.write_misses                      671                       # DTB write misses
system.cpu0.dtb.write_acv                          84                       # DTB write access violations
system.cpu0.dtb.write_accesses                 163761                       # DTB write accesses
system.cpu0.dtb.data_hits                     8414277                       # DTB hits
system.cpu0.dtb.data_misses                      6771                       # DTB misses
system.cpu0.dtb.data_acv                          210                       # DTB access violations
system.cpu0.dtb.data_accesses                  592080                       # DTB accesses
system.cpu0.itb.fetch_hits                    2758234                       # ITB hits
system.cpu0.itb.fetch_misses                     3034                       # ITB misses
system.cpu0.itb.fetch_acv                         104                       # ITB acv
system.cpu0.itb.fetch_accesses                2761268                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       928316891                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   33736461                       # Number of instructions committed
system.cpu0.committedOps                     33736461                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             31599588                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                169686                       # Number of float alu accesses
system.cpu0.num_func_calls                     810809                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      4665593                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    31599588                       # number of integer instructions
system.cpu0.num_fp_insts                       169686                       # number of float instructions
system.cpu0.num_int_register_reads           44374544                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          23060255                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads               87629                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes              89168                       # number of times the floating registers were written
system.cpu0.num_mem_refs                      8444409                       # number of memory refs
system.cpu0.num_load_insts                    4931349                       # Number of load instructions
system.cpu0.num_store_insts                   3513060                       # Number of store instructions
system.cpu0.num_idle_cycles              903633014.989213                       # Number of idle cycles
system.cpu0.num_busy_cycles              24683876.010787                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.026590                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.973410                       # Percentage of idle cycles
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6419                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    211396                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   74806     40.97%     40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1879      1.03%     42.11% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                 105698     57.89%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              182586                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    73439     49.30%     49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1879      1.26%     50.70% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   73439     49.30%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               148960                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1819515680500     98.74%     98.74% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               39349500      0.00%     98.74% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              365678500      0.02%     98.76% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            22783774000      1.24%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1842704482500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.981726                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.694800                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.815835                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      2.45%      2.45% # number of syscalls executed
system.cpu0.kern.syscall::3                        30      9.20%     11.66% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.23%     12.88% # number of syscalls executed
system.cpu0.kern.syscall::6                        42     12.88%     25.77% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.31%     26.07% # number of syscalls executed
system.cpu0.kern.syscall::15                        1      0.31%     26.38% # number of syscalls executed
system.cpu0.kern.syscall::17                       15      4.60%     30.98% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      3.07%     34.05% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      1.84%     35.89% # number of syscalls executed
system.cpu0.kern.syscall::23                        4      1.23%     37.12% # number of syscalls executed
system.cpu0.kern.syscall::24                        6      1.84%     38.96% # number of syscalls executed
system.cpu0.kern.syscall::33                       11      3.37%     42.33% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.61%     42.94% # number of syscalls executed
system.cpu0.kern.syscall::45                       54     16.56%     59.51% # number of syscalls executed
system.cpu0.kern.syscall::47                        6      1.84%     61.35% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      3.07%     64.42% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      3.07%     67.48% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.31%     67.79% # number of syscalls executed
system.cpu0.kern.syscall::59                        7      2.15%     69.94% # number of syscalls executed
system.cpu0.kern.syscall::71                       54     16.56%     86.50% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      0.92%     87.42% # number of syscalls executed
system.cpu0.kern.syscall::74                       16      4.91%     92.33% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.31%     92.64% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      0.92%     93.56% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      2.76%     96.32% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.61%     96.93% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.61%     97.55% # number of syscalls executed
system.cpu0.kern.syscall::132                       4      1.23%     98.77% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.61%     99.39% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.61%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   326                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 4176      2.17%      2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi                      54      0.03%      2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.21% # number of callpals executed
system.cpu0.kern.callpal::swpipl               175327     91.20%     93.41% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6783      3.53%     96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     7      0.00%     96.94% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.00%     96.94% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.95% # number of callpals executed
system.cpu0.kern.callpal::rti                    5176      2.69%     99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys                 515      0.27%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     181      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                192242                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             5923                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1738                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle               2095                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1908                      
system.cpu0.kern.mode_good::user                 1738                      
system.cpu0.kern.mode_good::idle                  170                      
system.cpu0.kern.mode_switch_good::kernel     0.322134                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle      0.081146                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.391144                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel       29786026000      1.62%      1.62% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          2614250500      0.14%      1.76% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle        1810304201500     98.24%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    4177                       # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.toL2Bus.throughput                   110422039                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq             786602                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            786555                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq              3756                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp             3756                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           371447                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq              15                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp             17                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           151061                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          133781                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError           32                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       849315                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1370344                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               2219659                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     27177600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     55325386                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total           82502986                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             203464200                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus           11072                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         2135432500                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           247500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1913139810                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        2237602233                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.iobus.throughput                       1469136                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq                 2975                       # Transaction distribution
system.iobus.trans_dist::ReadResp                2975                       # Transaction distribution
system.iobus.trans_dist::WriteReq               21036                       # Transaction distribution
system.iobus.trans_dist::WriteResp              21036                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         2342                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          140                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio           66                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio         8320                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         2420                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        13322                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        34700                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        34700                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                   48022                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio         9368                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio          560                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio           61                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         4160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         1574                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf           31                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total        15754                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      1107376                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      1107376                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              1123130                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 2707184                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              2208000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               105000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy               57000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6200000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             1827000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy               20000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           157303021                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy             9566000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            17990250                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.cpu0.icache.tags.replacements           950451                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.192015                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           43221003                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           950962                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            45.449769                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      10381115250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   246.999230                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst    99.674980                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst   164.517805                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.482420                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.194678                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.321324                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998422                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst     33216972                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      7763860                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      2240171                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       43221003                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     33216972                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      7763860                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      2240171                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        43221003                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     33216972                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      7763860                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      2240171                       # number of overall hits
system.cpu0.icache.overall_hits::total       43221003                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       526470                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       126995                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       313704                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       967169                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       526470                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       126995                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       313704                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        967169                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       526470                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       126995                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       313704                       # number of overall misses
system.cpu0.icache.overall_misses::total       967169                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1823123501                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4463889198                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   6287012699                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   1823123501                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   4463889198                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   6287012699                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   1823123501                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   4463889198                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   6287012699                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     33743442                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      7890855                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      2553875                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     44188172                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     33743442                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      7890855                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      2553875                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     44188172                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     33743442                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      7890855                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      2553875                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     44188172                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015602                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016094                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122835                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.021888                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015602                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016094                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.122835                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.021888                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015602                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016094                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122835                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.021888                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14355.868349                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14229.621548                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  6500.428259                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14355.868349                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14229.621548                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  6500.428259                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14355.868349                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14229.621548                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  6500.428259                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         4785                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              202                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    23.688119                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16034                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        16034                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        16034                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        16034                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        16034                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        16034                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       126995                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       297670                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       424665                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       126995                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       297670                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       424665                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       126995                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       297670                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       424665                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1568013499                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3675865433                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   5243878932                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1568013499                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3675865433                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   5243878932                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1568013499                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3675865433                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   5243878932                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016094                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116556                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009610                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016094                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116556                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.009610                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016094                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116556                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.009610                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12347.049089                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12348.793741                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12348.272007                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12347.049089                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12348.793741                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12348.272007                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12347.049089                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12348.793741                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12348.272007                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements          1391525                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.997811                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           13285085                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1392037                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs             9.543629                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   250.196143                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   130.348399                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data   131.453270                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.488664                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.254587                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.256745                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      4073389                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      1086662                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      2399601                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        7559652                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3208453                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data       837545                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      1295843                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       5341841                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       116948                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19346                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        47955                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       184249                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       126113                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21379                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data        51797                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       199289                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      7281842                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      1924207                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      3695444                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        12901493                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      7281842                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      1924207                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      3695444                       # number of overall hits
system.cpu0.dcache.overall_hits::total       12901493                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       720818                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data        98930                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       533963                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1353711                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       168792                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        45023                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       591984                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       805799                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9729                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2165                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         6797                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        18691                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data            2                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       889610                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       143953                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data      1125947                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2159510                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       889610                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       143953                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1125947                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2159510                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2262060250                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9361678086                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  11623738336                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1620272009                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  17690504226                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  19310776235                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     28582500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    102574499                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    131156999                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        38001                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total        38001                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   3882332259                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  27052182312                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  30934514571                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   3882332259                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  27052182312                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  30934514571                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      4794207                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      1185592                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      2933564                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8913363                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      3377245                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data       882568                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      1887827                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      6147640                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       126677                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21511                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        54752                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       202940                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       126113                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21379                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        51799                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       199291                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data      8171452                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      2068160                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      4821391                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     15061003                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data      8171452                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      2068160                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      4821391                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     15061003                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.150352                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.083444                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.182019                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.151874                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049979                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.051014                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.313580                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.131075                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.076802                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.100646                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.124142                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.092101                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000039                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000010                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.108868                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.069604                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.233532                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.143384                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.108868                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.069604                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.233532                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.143384                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22865.260790                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17532.447166                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total  8586.573010                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35987.650956                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 29883.416150                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 23964.755770                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13202.078522                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15091.143004                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  7017.120486                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 19000.500000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 19000.500000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26969.443214                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24026.159590                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14324.784127                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26969.443214                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24026.159590                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14324.784127                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       557875                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets          852                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            17918                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    31.134892                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   121.714286                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       835257                       # number of writebacks
system.cpu0.dcache.writebacks::total           835257                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       281255                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       281255                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       503456                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       503456                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1394                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1394                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       784711                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       784711                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       784711                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       784711                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        98930                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       252708                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       351638                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        45023                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        88528                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       133551                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2165                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5403                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7568                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       143953                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       341236                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       485189                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       143953                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       341236                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       485189                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2055649750                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4240939408                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6296589158                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1521155991                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2563125747                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4084281738                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     24249500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     66698251                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     90947751                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        33999                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        33999                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3576805741                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   6804065155                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  10380870896                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3576805741                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   6804065155                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  10380870896                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    294283500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    312003000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    606286500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    361937500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    429433000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    791370500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    656221000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    741436000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1397657000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.083444                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086144                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.039451                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.051014                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.046894                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.021724                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.100646                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.098681                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.037292                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000039                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.069604                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.070775                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.032215                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.069604                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.070775                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.032215                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20778.830992                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16781.975276                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17906.452539                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33786.197965                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 28952.712667                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30582.187614                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11200.692841                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12344.669813                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12017.408959                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 16999.500000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16999.500000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24847.038554                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19939.470498                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21395.519882                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24847.038554                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19939.470498                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21395.519882                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1205047                       # DTB read hits
system.cpu1.dtb.read_misses                      1367                       # DTB read misses
system.cpu1.dtb.read_acv                           34                       # DTB read access violations
system.cpu1.dtb.read_accesses                  142944                       # DTB read accesses
system.cpu1.dtb.write_hits                     904403                       # DTB write hits
system.cpu1.dtb.write_misses                      185                       # DTB write misses
system.cpu1.dtb.write_acv                          23                       # DTB write access violations
system.cpu1.dtb.write_accesses                  58533                       # DTB write accesses
system.cpu1.dtb.data_hits                     2109450                       # DTB hits
system.cpu1.dtb.data_misses                      1552                       # DTB misses
system.cpu1.dtb.data_acv                           57                       # DTB access violations
system.cpu1.dtb.data_accesses                  201477                       # DTB accesses
system.cpu1.itb.fetch_hits                     861634                       # ITB hits
system.cpu1.itb.fetch_misses                      693                       # ITB misses
system.cpu1.itb.fetch_acv                          30                       # ITB acv
system.cpu1.itb.fetch_accesses                 862327                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                       953630418                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                    7889245                       # Number of instructions committed
system.cpu1.committedOps                      7889245                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses              7344952                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                 44937                       # Number of float alu accesses
system.cpu1.num_func_calls                     213049                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts       993802                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                     7344952                       # number of integer instructions
system.cpu1.num_fp_insts                        44937                       # number of float instructions
system.cpu1.num_int_register_reads           10269748                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           5343251                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads               24271                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              24577                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      2116682                       # number of memory refs
system.cpu1.num_load_insts                    1209934                       # Number of load instructions
system.cpu1.num_store_insts                    906748                       # Number of store instructions
system.cpu1.num_idle_cycles              923700977.463911                       # Number of idle cycles
system.cpu1.num_busy_cycles              29929440.536089                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.031385                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.968615                       # Percentage of idle cycles
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                         0                       # number of hwrei instructions executed
system.cpu1.kern.mode_switch::kernel                0                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                  0                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                  0                      
system.cpu1.kern.mode_good::user                    0                      
system.cpu1.kern.mode_good::idle                    0                      
system.cpu1.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
system.cpu2.branchPred.lookups                9022316                       # Number of BP lookups
system.cpu2.branchPred.condPredicted          8342315                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           122648                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups             7529449                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                6410701                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            85.141702                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 283187                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             12478                       # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits                          0                       # ITB hits
system.cpu2.dtb.fetch_misses                        0                       # ITB misses
system.cpu2.dtb.fetch_acv                           0                       # ITB acv
system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu2.dtb.read_hits                     3192037                       # DTB read hits
system.cpu2.dtb.read_misses                     11608                       # DTB read misses
system.cpu2.dtb.read_acv                          121                       # DTB read access violations
system.cpu2.dtb.read_accesses                  216573                       # DTB read accesses
system.cpu2.dtb.write_hits                    2009173                       # DTB write hits
system.cpu2.dtb.write_misses                     2522                       # DTB write misses
system.cpu2.dtb.write_acv                         106                       # DTB write access violations
system.cpu2.dtb.write_accesses                  81978                       # DTB write accesses
system.cpu2.dtb.data_hits                     5201210                       # DTB hits
system.cpu2.dtb.data_misses                     14130                       # DTB misses
system.cpu2.dtb.data_acv                          227                       # DTB access violations
system.cpu2.dtb.data_accesses                  298551                       # DTB accesses
system.cpu2.itb.fetch_hits                     369667                       # ITB hits
system.cpu2.itb.fetch_misses                     5681                       # ITB misses
system.cpu2.itb.fetch_acv                         262                       # ITB acv
system.cpu2.itb.fetch_accesses                 375348                       # ITB accesses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.read_acv                            0                       # DTB read access violations
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.write_acv                           0                       # DTB write access violations
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.data_hits                           0                       # DTB hits
system.cpu2.itb.data_misses                         0                       # DTB misses
system.cpu2.itb.data_acv                            0                       # DTB access violations
system.cpu2.itb.data_accesses                       0                       # DTB accesses
system.cpu2.numCycles                        31245078                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles           8348883                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                      36663716                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                    9022316                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches           6693888                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                      8736568                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                 602984                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles               9694630                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles               11222                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles             1957                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        63711                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles        86195                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          437                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  2553880                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                85053                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples          27335965                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.341226                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.294449                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                18599397     68.04%     68.04% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  269863      0.99%     69.03% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                  429102      1.57%     70.60% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                 4885317     17.87%     88.47% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  756803      2.77%     91.24% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  166340      0.61%     91.85% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  191609      0.70%     92.55% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  429140      1.57%     94.12% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                 1608394      5.88%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total            27335965                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.288760                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.173424                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                 8495766                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles              9778515                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                  8128034                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles               307242                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                380496                       # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved              165135                       # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred                12538                       # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts              36269918                       # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts                39153                       # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles                380496                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                 8853799                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                2797423                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles       5789351                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                  7998658                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles              1270334                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts              35131949                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents                 2438                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents                231189                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents               444117                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands           23541427                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups             43931372                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups        43768405                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups           162967                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps             21760313                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                 1781114                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            501831                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts         59191                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                  3719256                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             3350609                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            2097879                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           369762                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          260934                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                  32641753                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             622044                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                 32196803                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued            34835                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        2138258                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined      1073109                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved        438824                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples     27335965                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.177818                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.573987                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           15167963     55.49%     55.49% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            3067850     11.22%     66.71% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            1557003      5.70%     72.41% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            5712284     20.90%     93.30% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4             903378      3.30%     96.61% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5             480833      1.76%     98.37% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6             285081      1.04%     99.41% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             142652      0.52%     99.93% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8              18921      0.07%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total       27335965                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                  33684     13.60%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     13.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                113022     45.64%     59.24% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite               100957     40.76%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass             2440      0.01%      0.01% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu             26526068     82.39%     82.39% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               20082      0.06%     82.46% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     82.46% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd               8432      0.03%     82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv               1220      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     82.49% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead             3318552     10.31%     92.79% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            2030927      6.31%     99.10% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess            289082      0.90%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total              32196803                       # Type of FU issued
system.cpu2.iq.rate                          1.030460                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                     247663                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.007692                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads          91777621                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes         35291242                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses     31803164                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads             234448                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes            114643                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses       110912                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses              32319915                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                 122111                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          186470                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads       409308                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         1087                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         3940                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       154806                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads         4179                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked        28515                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                380496                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                2018433                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles               205280                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts           34533473                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts           223572                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              3350609                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             2097879                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            552418                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                143005                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                 2030                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          3940                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect         62474                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       127218                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              189692                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts             32041792                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts              3211958                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           155011                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                      1269676                       # number of nop insts executed
system.cpu2.iew.exec_refs                     5228104                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                 7451179                       # Number of branches executed
system.cpu2.iew.exec_stores                   2016146                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.025499                       # Inst execution rate
system.cpu2.iew.wb_sent                      31946323                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                     31914076                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                 18560539                       # num instructions producing a value
system.cpu2.iew.wb_consumers                 21756623                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.021411                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.853098                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        2307107                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         183220                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           175579                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples     26955469                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.193861                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.846623                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     16175286     60.01%     60.01% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      2330504      8.65%     68.65% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1226068      4.55%     73.20% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3      5456953     20.24%     93.45% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       503178      1.87%     95.31% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       186113      0.69%     96.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       177622      0.66%     96.66% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7       179384      0.67%     97.33% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8       720361      2.67%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total     26955469                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts            32181084                       # Number of instructions committed
system.cpu2.commit.committedOps              32181084                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       4884374                       # Number of memory references committed
system.cpu2.commit.loads                      2941301                       # Number of loads committed
system.cpu2.commit.membars                      64148                       # Number of memory barriers committed
system.cpu2.commit.branches                   7305681                       # Number of branches committed
system.cpu2.commit.fp_insts                    109768                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                 30735120                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              229363                       # Number of function calls committed.
system.cpu2.commit.bw_lim_events               720361                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                    60649307                       # The number of ROB reads
system.cpu2.rob.rob_writes                   69356385                       # The number of ROB writes
system.cpu2.timesIdled                         245741                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                        3909113                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  1746532644                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                   31016177                       # Number of Instructions Simulated
system.cpu2.committedOps                     31016177                       # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total             31016177                       # Number of Instructions Simulated
system.cpu2.cpi                              1.007380                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        1.007380                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.992674                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.992674                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                42141472                       # number of integer regfile reads
system.cpu2.int_regfile_writes               22438304                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    67749                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   68082                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                5235386                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                258296                       # number of misc regfile writes
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei                         0                       # number of hwrei instructions executed
system.cpu2.kern.mode_switch::kernel                0                       # number of protection mode switches
system.cpu2.kern.mode_switch::user                  0                       # number of protection mode switches
system.cpu2.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu2.kern.mode_good::kernel                  0                      
system.cpu2.kern.mode_good::user                    0                      
system.cpu2.kern.mode_good::idle                    0                      
system.cpu2.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
system.cpu2.kern.swap_context                       0                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------