blob: 296ab434c80f44ec03bb7e2140857ff0d80fe8a2 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
|
---------- Begin Simulation Statistics ----------
sim_seconds 1.841535 # Number of seconds simulated
sim_ticks 1841535479500 # Number of ticks simulated
final_tick 1841535479500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 156573 # Simulator instruction rate (inst/s)
host_op_rate 156573 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3970842510 # Simulator tick rate (ticks/s)
host_mem_usage 369896 # Number of bytes of host memory used
host_seconds 463.76 # Real time elapsed on the host
sim_insts 72613172 # Number of instructions simulated
sim_ops 72613172 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 466112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 20058112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 2156288 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 305728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 2656832 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 25791040 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 466112 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 305728 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 918848 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7482432 # Number of bytes written to this memory
system.physmem.bytes_written::total 7482432 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 7283 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 313408 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 33692 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 4777 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 41513 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 402985 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 116913 # Number of write requests responded to by this memory
system.physmem.num_writes::total 116913 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 253111 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 10892058 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 79829 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1170919 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 166018 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 1442726 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14005182 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 253111 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 79829 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 166018 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 498958 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4063148 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4063148 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4063148 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 253111 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 10892058 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 79829 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1170919 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 166018 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 1442726 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18068331 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 82294 # Number of read requests accepted
system.physmem.writeReqs 47398 # Number of write requests accepted
system.physmem.readBursts 82294 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 47398 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 5265472 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 1344 # Total number of bytes read from write queue
system.physmem.bytesWritten 3032512 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 5266816 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 3033472 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 21 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 17325 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 5126 # Per bank write bursts
system.physmem.perBankRdBursts::1 5048 # Per bank write bursts
system.physmem.perBankRdBursts::2 4814 # Per bank write bursts
system.physmem.perBankRdBursts::3 4971 # Per bank write bursts
system.physmem.perBankRdBursts::4 5248 # Per bank write bursts
system.physmem.perBankRdBursts::5 5169 # Per bank write bursts
system.physmem.perBankRdBursts::6 5184 # Per bank write bursts
system.physmem.perBankRdBursts::7 5149 # Per bank write bursts
system.physmem.perBankRdBursts::8 5417 # Per bank write bursts
system.physmem.perBankRdBursts::9 4756 # Per bank write bursts
system.physmem.perBankRdBursts::10 5535 # Per bank write bursts
system.physmem.perBankRdBursts::11 5117 # Per bank write bursts
system.physmem.perBankRdBursts::12 4885 # Per bank write bursts
system.physmem.perBankRdBursts::13 5047 # Per bank write bursts
system.physmem.perBankRdBursts::14 5632 # Per bank write bursts
system.physmem.perBankRdBursts::15 5175 # Per bank write bursts
system.physmem.perBankWrBursts::0 2819 # Per bank write bursts
system.physmem.perBankWrBursts::1 2870 # Per bank write bursts
system.physmem.perBankWrBursts::2 2836 # Per bank write bursts
system.physmem.perBankWrBursts::3 2977 # Per bank write bursts
system.physmem.perBankWrBursts::4 3104 # Per bank write bursts
system.physmem.perBankWrBursts::5 2797 # Per bank write bursts
system.physmem.perBankWrBursts::6 3160 # Per bank write bursts
system.physmem.perBankWrBursts::7 2831 # Per bank write bursts
system.physmem.perBankWrBursts::8 3459 # Per bank write bursts
system.physmem.perBankWrBursts::9 2567 # Per bank write bursts
system.physmem.perBankWrBursts::10 3319 # Per bank write bursts
system.physmem.perBankWrBursts::11 2907 # Per bank write bursts
system.physmem.perBankWrBursts::12 2644 # Per bank write bursts
system.physmem.perBankWrBursts::13 2801 # Per bank write bursts
system.physmem.perBankWrBursts::14 3392 # Per bank write bursts
system.physmem.perBankWrBursts::15 2900 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
system.physmem.totGap 1840523607000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 82294 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 47398 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 64239 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 7821 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 5630 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 4551 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 73 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 41 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 769 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 932 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 1881 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 2133 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 2124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 2452 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 2795 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 2907 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 3952 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 3624 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 3062 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 3399 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 2706 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 2701 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 3062 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 2331 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 2249 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 2118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 72 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 47 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 67 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 67 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 43 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 69 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 21780 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 380.991001 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 216.949703 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 378.684450 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 7216 33.13% 33.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 4887 22.44% 55.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 1962 9.01% 64.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 1034 4.75% 69.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 848 3.89% 73.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 523 2.40% 75.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 452 2.08% 77.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 368 1.69% 79.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 4490 20.62% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 21780 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 2078 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 39.592397 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 979.363215 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 2076 99.90% 99.90% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 2078 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 2078 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 22.802214 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.584158 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 22.825875 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 29 1.40% 1.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 6 0.29% 1.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 1 0.05% 1.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 6 0.29% 2.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 1724 82.96% 84.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 39 1.88% 86.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 91 4.38% 91.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 19 0.91% 92.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 9 0.43% 92.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 19 0.91% 93.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 4 0.19% 93.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 2 0.10% 93.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 3 0.14% 93.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 1 0.05% 93.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 2 0.10% 94.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 3 0.14% 94.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 1 0.05% 94.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 3 0.14% 94.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 4 0.19% 94.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 8 0.38% 95.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 4 0.19% 95.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 76 3.66% 98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 6 0.29% 99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.10% 99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 1 0.05% 99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 3 0.14% 99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 2 0.10% 99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 1 0.05% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.05% 99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 1 0.05% 99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 1 0.05% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 2 0.10% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203 1 0.05% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227 1 0.05% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231 2 0.10% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 2078 # Writes before turning the bus around for reads
system.physmem.totQLat 922774500 # Total ticks spent queuing
system.physmem.totMemAccLat 2465393250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 411365000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11216.01 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 29966.01 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.86 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.65 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.86 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.65 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing
system.physmem.avgWrQLen 16.09 # Average write queue length when enqueuing
system.physmem.readRowHits 70442 # Number of row buffer hits during reads
system.physmem.writeRowHits 37434 # Number of row buffer hits during writes
system.physmem.readRowHitRate 85.62 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 78.98 # Row buffer hit rate for writes
system.physmem.avgGap 14191496.83 # Average gap between requests
system.physmem.pageHitRate 83.19 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 81065880 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 44121000 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 317530200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 151593120 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 35745647625 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 800947233750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 926343167415 # Total energy per rank (pJ)
system.physmem_0.averagePower 667.792687 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 1308857547000 # Time in different power states
system.physmem_0.memoryStateTime::REF 45529640000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 9287627500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 83590920 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 45449250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 324199200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 155448720 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 35447161140 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 801537520500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 926649345570 # Total energy per rank (pJ)
system.physmem_1.averagePower 667.749891 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1309278655250 # Time in different power states
system.physmem_1.memoryStateTime::REF 45529640000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 8857363000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 4774172 # DTB read hits
system.cpu0.dtb.read_misses 5959 # DTB read misses
system.cpu0.dtb.read_acv 109 # DTB read access violations
system.cpu0.dtb.read_accesses 427834 # DTB read accesses
system.cpu0.dtb.write_hits 3388527 # DTB write hits
system.cpu0.dtb.write_misses 664 # DTB write misses
system.cpu0.dtb.write_acv 80 # DTB write access violations
system.cpu0.dtb.write_accesses 164366 # DTB write accesses
system.cpu0.dtb.data_hits 8162699 # DTB hits
system.cpu0.dtb.data_misses 6623 # DTB misses
system.cpu0.dtb.data_acv 189 # DTB access violations
system.cpu0.dtb.data_accesses 592200 # DTB accesses
system.cpu0.itb.fetch_hits 2715643 # ITB hits
system.cpu0.itb.fetch_misses 3015 # ITB misses
system.cpu0.itb.fetch_acv 97 # ITB acv
system.cpu0.itb.fetch_accesses 2718658 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 928469977 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 30414467 # Number of instructions committed
system.cpu0.committedOps 30414467 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 28351523 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 162419 # Number of float alu accesses
system.cpu0.num_func_calls 792250 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 3751370 # number of instructions that are conditional controls
system.cpu0.num_int_insts 28351523 # number of integer instructions
system.cpu0.num_fp_insts 162419 # number of float instructions
system.cpu0.num_int_register_reads 39201854 # number of times the integer registers were read
system.cpu0.num_int_register_writes 20853832 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 84043 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 85470 # number of times the floating registers were written
system.cpu0.num_mem_refs 8191763 # number of memory refs
system.cpu0.num_load_insts 4794790 # Number of load instructions
system.cpu0.num_store_insts 3396973 # Number of store instructions
system.cpu0.num_idle_cycles 905786099.867998 # Number of idle cycles
system.cpu0.num_busy_cycles 22683877.132002 # Number of busy cycles
system.cpu0.not_idle_fraction 0.024431 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.975569 # Percentage of idle cycles
system.cpu0.Branches 4797930 # Number of branches fetched
system.cpu0.op_class::No_OpClass 1559380 5.13% 5.13% # Class of executed instruction
system.cpu0.op_class::IntAlu 19980835 65.68% 70.81% # Class of executed instruction
system.cpu0.op_class::IntMult 31353 0.10% 70.91% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 70.91% # Class of executed instruction
system.cpu0.op_class::FloatAdd 12822 0.04% 70.95% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 70.95% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 70.95% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 70.95% # Class of executed instruction
system.cpu0.op_class::FloatDiv 1598 0.01% 70.96% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.96% # Class of executed instruction
system.cpu0.op_class::MemRead 4924664 16.19% 87.15% # Class of executed instruction
system.cpu0.op_class::MemWrite 3400050 11.18% 98.32% # Class of executed instruction
system.cpu0.op_class::IprAccess 510577 1.68% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 30421279 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 211362 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 105680 57.89% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 182555 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1818807757000 98.77% 98.77% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 38797500 0.00% 98.77% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 357175000 0.02% 98.79% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 22331016000 1.21% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1841534745500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.694805 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.815836 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu0.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu0.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu0.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu0.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu0.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu0.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu0.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu0.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu0.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu0.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu0.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu0.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu0.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu0.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu0.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu0.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu0.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu0.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu0.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 326 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
system.cpu0.kern.callpal::swpipl 175298 91.20% 93.41% # number of callpals executed
system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed
system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 192209 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1906
system.cpu0.kern.mode_good::user 1737
system.cpu0.kern.mode_good::idle 169
system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 29743380000 1.62% 1.62% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 2567925500 0.14% 1.75% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 1809223438000 98.25% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 4175 # number of times the context was actually changed
system.cpu0.dcache.tags.replacements 1392924 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 13249026 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1393436 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 9.508170 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 177.335991 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 163.453449 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 171.208376 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.346359 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.319245 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.334391 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 63330121 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 63330121 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 3955641 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 1077876 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 2532941 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 7566458 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3102475 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 828519 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 1367883 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5298877 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113517 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19685 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51083 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 184285 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122198 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21798 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55320 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 199316 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 7058116 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 1906395 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 3900824 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 12865335 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 7058116 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 1906395 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 3900824 # number of overall hits
system.cpu0.dcache.overall_hits::total 12865335 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 705857 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 97562 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 561486 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1364905 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 162429 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 43967 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 644644 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 851040 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9228 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2243 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7808 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 19279 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 11 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 868286 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 141529 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 1206130 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2215945 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 868286 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 141529 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1206130 # number of overall misses
system.cpu0.dcache.overall_misses::total 2215945 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2272668500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8215053500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 10487722000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1750811500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19626601777 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 21377413277 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 29663000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 127096500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 156759500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 184000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 184000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 4023480000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 27841655277 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 31865135277 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 4023480000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 27841655277 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 31865135277 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 4661498 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1175438 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 3094427 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8931363 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3264904 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 872486 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 2012527 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 6149917 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 122745 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21928 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58891 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 203564 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122198 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21798 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55331 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 199327 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 7926402 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 2047924 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 5106954 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 15081280 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 7926402 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 2047924 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 5106954 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 15081280 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151423 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083001 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181451 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.152822 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049750 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050393 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.320316 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.138382 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075180 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102289 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.132584 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094707 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000199 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000055 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109544 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069109 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.236174 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.146933 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109544 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069109 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.236174 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.146933 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23294.607532 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14630.914217 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 7683.847594 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39821.036232 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30445.644072 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 25119.163937 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13224.699064 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16277.727971 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8131.101198 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16727.272727 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16727.272727 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28428.661264 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23083.461382 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14379.930584 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28428.661264 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 23083.461382 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14379.930584 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 1023083 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 1722 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 60080 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 18 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.028678 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 95.666667 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 835650 # number of writebacks
system.cpu0.dcache.writebacks::total 835650 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 291568 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 291568 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 548541 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 548541 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1641 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1641 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 840109 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 840109 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 840109 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 840109 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 97562 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 269918 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 367480 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43967 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 96103 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 140070 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2243 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6167 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8410 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 11 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 141529 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 366021 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 507550 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 141529 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 366021 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 507550 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1107 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1558 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2665 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1386 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2128 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3514 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2493 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3686 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6179 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2175106500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4426228500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6601335000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1706844500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3108596312 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4815440812 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 27420000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 77097500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104517500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 173000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 173000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3881951000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7534824812 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 11416775812 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3881951000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7534824812 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 11416775812 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 226227500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 334192500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 560420000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298200000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 450969000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 749169000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 524427500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 785161500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1309589000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083001 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087227 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041145 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050393 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047752 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022776 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102289 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.104719 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.041314 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000199 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000055 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069109 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071671 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.033654 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069109 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071671 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.033654 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22294.607532 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16398.419150 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17963.793948 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38821.036232 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32346.506477 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34378.816392 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12224.699064 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12501.621534 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12427.764566 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15727.272727 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15727.272727 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27428.661264 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20585.771887 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22493.893827 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27428.661264 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20585.771887 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22493.893827 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 204360.885276 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 214500.962773 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210288.930582 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 215151.515152 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211921.522556 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 213195.503699 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 210360.008022 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 213011.801411 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 211941.899984 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 963177 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.919668 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 40183368 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 963688 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 41.697487 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 10187899500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 148.948748 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 136.141622 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 225.829298 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.290916 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.265902 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.441073 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.997890 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 42127818 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 42127818 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 29914547 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 7792823 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 2475998 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 40183368 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 29914547 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 7792823 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 2475998 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 40183368 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 29914547 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 7792823 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 2475998 # number of overall hits
system.cpu0.icache.overall_hits::total 40183368 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 506732 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 128884 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 344958 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 980574 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 506732 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 128884 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 344958 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 980574 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 506732 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 128884 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 344958 # number of overall misses
system.cpu0.icache.overall_misses::total 980574 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1840159000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4813824984 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 6653983984 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 1840159000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 4813824984 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 6653983984 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 1840159000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 4813824984 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 6653983984 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 30421279 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 7921707 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 2820956 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 41163942 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 30421279 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 7921707 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 2820956 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 41163942 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 30421279 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 7921707 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 2820956 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 41163942 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016657 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016270 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122284 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.023821 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016657 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016270 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122284 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.023821 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016657 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016270 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122284 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.023821 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14277.637255 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13954.814743 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 6785.805033 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14277.637255 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13954.814743 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 6785.805033 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14277.637255 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13954.814743 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 6785.805033 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 4577 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 237 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.312236 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16698 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 16698 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 16698 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 16698 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 16698 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 16698 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 128884 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 328260 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 457144 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 128884 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 328260 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 457144 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 128884 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 328260 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 457144 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1711275000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4293223488 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 6004498488 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1711275000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4293223488 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 6004498488 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1711275000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4293223488 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 6004498488 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016270 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116365 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011105 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016270 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116365 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.011105 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016270 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116365 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.011105 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13277.637255 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13078.728715 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13134.807605 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13277.637255 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13078.728715 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13134.807605 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13277.637255 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13078.728715 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13134.807605 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 1195033 # DTB read hits
system.cpu1.dtb.read_misses 1325 # DTB read misses
system.cpu1.dtb.read_acv 35 # DTB read access violations
system.cpu1.dtb.read_accesses 141268 # DTB read accesses
system.cpu1.dtb.write_hits 894434 # DTB write hits
system.cpu1.dtb.write_misses 169 # DTB write misses
system.cpu1.dtb.write_acv 22 # DTB write access violations
system.cpu1.dtb.write_accesses 56923 # DTB write accesses
system.cpu1.dtb.data_hits 2089467 # DTB hits
system.cpu1.dtb.data_misses 1494 # DTB misses
system.cpu1.dtb.data_acv 57 # DTB access violations
system.cpu1.dtb.data_accesses 198191 # DTB accesses
system.cpu1.itb.fetch_hits 856224 # ITB hits
system.cpu1.itb.fetch_misses 659 # ITB misses
system.cpu1.itb.fetch_acv 35 # ITB acv
system.cpu1.itb.fetch_accesses 856883 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 953248779 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 7920155 # Number of instructions committed
system.cpu1.committedOps 7920155 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 7379126 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 45865 # Number of float alu accesses
system.cpu1.num_func_calls 207333 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1021718 # number of instructions that are conditional controls
system.cpu1.num_int_insts 7379126 # number of integer instructions
system.cpu1.num_fp_insts 45865 # number of float instructions
system.cpu1.num_int_register_reads 10346831 # number of times the integer registers were read
system.cpu1.num_int_register_writes 5362502 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 24725 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 25053 # number of times the floating registers were written
system.cpu1.num_mem_refs 2096589 # number of memory refs
system.cpu1.num_load_insts 1199833 # Number of load instructions
system.cpu1.num_store_insts 896756 # Number of store instructions
system.cpu1.num_idle_cycles 922000099.418594 # Number of idle cycles
system.cpu1.num_busy_cycles 31248679.581406 # Number of busy cycles
system.cpu1.not_idle_fraction 0.032781 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.967219 # Percentage of idle cycles
system.cpu1.Branches 1295631 # Number of branches fetched
system.cpu1.op_class::No_OpClass 410705 5.18% 5.18% # Class of executed instruction
system.cpu1.op_class::IntAlu 5234650 66.08% 71.26% # Class of executed instruction
system.cpu1.op_class::IntMult 8605 0.11% 71.37% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 71.37% # Class of executed instruction
system.cpu1.op_class::FloatAdd 5163 0.07% 71.44% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 71.44% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 71.44% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 71.44% # Class of executed instruction
system.cpu1.op_class::FloatDiv 810 0.01% 71.45% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.45% # Class of executed instruction
system.cpu1.op_class::MemRead 1228944 15.51% 86.96% # Class of executed instruction
system.cpu1.op_class::MemWrite 897985 11.34% 98.30% # Class of executed instruction
system.cpu1.op_class::IprAccess 134844 1.70% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 7921706 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu1.kern.mode_switch::kernel 0 # number of protection mode switches
system.cpu1.kern.mode_switch::user 0 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 0
system.cpu1.kern.mode_good::user 0
system.cpu1.kern.mode_good::idle 0
system.cpu1.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
system.cpu2.branchPred.lookups 11475270 # Number of BP lookups
system.cpu2.branchPred.condPredicted 10735483 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 123474 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 9110272 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 7311084 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 80.250996 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 301261 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 7742 # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
system.cpu2.dtb.read_hits 3542926 # DTB read hits
system.cpu2.dtb.read_misses 12527 # DTB read misses
system.cpu2.dtb.read_acv 162 # DTB read access violations
system.cpu2.dtb.read_accesses 225242 # DTB read accesses
system.cpu2.dtb.write_hits 2156991 # DTB write hits
system.cpu2.dtb.write_misses 2860 # DTB write misses
system.cpu2.dtb.write_acv 147 # DTB write access violations
system.cpu2.dtb.write_accesses 84372 # DTB write accesses
system.cpu2.dtb.data_hits 5699917 # DTB hits
system.cpu2.dtb.data_misses 15387 # DTB misses
system.cpu2.dtb.data_acv 309 # DTB access violations
system.cpu2.dtb.data_accesses 309614 # DTB accesses
system.cpu2.itb.fetch_hits 534150 # ITB hits
system.cpu2.itb.fetch_misses 5562 # ITB misses
system.cpu2.itb.fetch_acv 158 # ITB acv
system.cpu2.itb.fetch_accesses 539712 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.write_acv 0 # DTB write access violations
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.data_hits 0 # DTB hits
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
system.cpu2.numCycles 31796057 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 9294739 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 42846452 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 11475270 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 7612345 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 20400927 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 406592 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 934 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles 9632 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 1958 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 201207 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 109893 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 558 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 2820959 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 91095 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples 30222906 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.417681 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.345063 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 20065674 66.39% 66.39% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 304778 1.01% 67.40% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 474119 1.57% 68.97% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 5709833 18.89% 87.86% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 849889 2.81% 90.67% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 195244 0.65% 91.32% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 232616 0.77% 92.09% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 433559 1.43% 93.52% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 1957194 6.48% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 30222906 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.360902 # Number of branch fetches per cycle
system.cpu2.fetch.rate 1.347540 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 7641311 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 13078900 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 8781400 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 530431 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 190274 # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved 176731 # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred 13389 # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts 39469462 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 42545 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 190274 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 7916618 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 4614900 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 6334560 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 9009266 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 2156706 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 38654408 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 61763 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 395728 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 57668 # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents 1091797 # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands 25842385 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 48471958 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 48411597 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 56430 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 23967156 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 1875229 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 535043 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 63361 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 3828496 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 3518120 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 2250866 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 468779 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 334709 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 36116015 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 683906 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 35834403 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 15167 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 2521371 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 1120007 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 489344 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 30222906 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.185670 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.632890 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 17428882 57.67% 57.67% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 2748935 9.10% 66.76% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 1369590 4.53% 71.29% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 6435558 21.29% 92.59% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 1033977 3.42% 96.01% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 595062 1.97% 97.98% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 394555 1.31% 99.28% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 169710 0.56% 99.85% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 46637 0.15% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 30222906 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 86081 21.74% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.74% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 183352 46.31% 68.05% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 126504 31.95% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 29630335 82.69% 82.69% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 21208 0.06% 82.75% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.75% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 20533 0.06% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.81% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 3671135 10.24% 93.06% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 2181666 6.09% 99.15% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 305842 0.85% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 35834403 # Type of FU issued
system.cpu2.iq.rate 1.127008 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 395937 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.011049 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 102047941 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 39206340 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 35210799 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 254875 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 120668 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 117568 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 36091226 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 136658 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 206130 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 426126 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 1149 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 5847 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 179431 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 5057 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 224722 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 190274 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 4003128 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 196899 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 38192826 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 53825 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 3518120 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 2250866 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 608609 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 12914 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 142416 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 5847 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 60692 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 135198 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 195890 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 35634663 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 3564372 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 199740 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 1392905 # number of nop insts executed
system.cpu2.iew.exec_refs 5729004 # number of memory reference insts executed
system.cpu2.iew.exec_branches 8402054 # Number of branches executed
system.cpu2.iew.exec_stores 2164632 # Number of stores executed
system.cpu2.iew.exec_rate 1.120726 # Inst execution rate
system.cpu2.iew.wb_sent 35371199 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 35328367 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 20848782 # num instructions producing a value
system.cpu2.iew.wb_consumers 24577214 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 1.111093 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.848297 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 2641573 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 194562 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 179155 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 29759977 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.193046 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.869762 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 18187552 61.11% 61.11% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 2254342 7.58% 68.69% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1186941 3.99% 72.68% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 6165862 20.72% 93.40% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 562678 1.89% 95.29% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 198394 0.67% 95.95% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 165216 0.56% 96.51% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 166703 0.56% 97.07% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 872289 2.93% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 29759977 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 35505021 # Number of instructions committed
system.cpu2.commit.committedOps 35505021 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 5163429 # Number of memory references committed
system.cpu2.commit.loads 3091994 # Number of loads committed
system.cpu2.commit.membars 68344 # Number of memory barriers committed
system.cpu2.commit.branches 8230032 # Number of branches committed
system.cpu2.commit.fp_insts 115972 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 33980571 # Number of committed integer instructions.
system.cpu2.commit.function_calls 241816 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 1228927 3.46% 3.46% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu 28694755 80.82% 84.28% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult 20756 0.06% 84.34% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 84.34% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 20096 0.06% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 84.40% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead 3160338 8.90% 93.30% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite 2073079 5.84% 99.14% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 305842 0.86% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total 35505021 # Class of committed instruction
system.cpu2.commit.bw_lim_events 872289 # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads 66956679 # The number of ROB reads
system.cpu2.rob.rob_writes 76754434 # The number of ROB writes
system.cpu2.timesIdled 177058 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 1573151 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 1744013124 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 34278550 # Number of Instructions Simulated
system.cpu2.committedOps 34278550 # Number of Ops (including micro ops) Simulated
system.cpu2.cpi 0.927579 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 0.927579 # CPI: Total CPI of All Threads
system.cpu2.ipc 1.078075 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 1.078075 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 46864030 # number of integer regfile reads
system.cpu2.int_regfile_writes 24760821 # number of integer regfile writes
system.cpu2.fp_regfile_reads 71108 # number of floating regfile reads
system.cpu2.fp_regfile_writes 71427 # number of floating regfile writes
system.cpu2.misc_regfile_reads 6062934 # number of misc regfile reads
system.cpu2.misc_regfile_writes 274246 # number of misc regfile writes
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq 7317 # Transaction distribution
system.iobus.trans_dist::ReadResp 7317 # Transaction distribution
system.iobus.trans_dist::WriteReq 51362 # Transaction distribution
system.iobus.trans_dist::WriteResp 51362 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 756 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18256 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 952 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 2232000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 5366000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 1863000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 58000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 7000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 14000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 89821669 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 8844000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 17468000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41685 # number of replacements
system.iocache.tags.tagsinuse 1.254132 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 1693892766000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 1.254132 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.078383 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.078383 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
system.iocache.tags.data_accesses 375525 # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
system.iocache.overall_misses::total 173 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 9418962 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 9418962 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide 2040972707 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 2040972707 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 9418962 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 9418962 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 9418962 # number of overall miss cycles
system.iocache.overall_miss_latency::total 9418962 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54444.867052 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 54444.867052 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 49118.519133 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 49118.519133 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 54444.867052 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 54444.867052 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 54444.867052 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 54444.867052 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17280 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 17280 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5918962 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 5918962 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1176972707 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 1176972707 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 5918962 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 5918962 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 5918962 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 5918962 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 84556.600000 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68111.846470 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68111.846470 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 84556.600000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 84556.600000 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 337470 # number of replacements
system.l2c.tags.tagsinuse 65419.393999 # Cycle average of tags in use
system.l2c.tags.total_refs 4005329 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 402632 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 9.947866 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 54633.992785 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 2282.515139 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2705.284872 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 536.585010 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 602.481810 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 2408.251048 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 2250.283336 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.833649 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.034828 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.041279 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.008188 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.009193 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.036747 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.034337 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.998221 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 997 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 6046 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 2595 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 55346 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 38409794 # Number of tag accesses
system.l2c.tags.data_accesses 38409794 # Number of data accesses
system.l2c.Writeback_hits::writebacks 835650 # number of Writeback hits
system.l2c.Writeback_hits::total 835650 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 10 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 14 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data 9 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 89264 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 25987 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 71674 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 186925 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 499428 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 126587 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 323447 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 949462 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 474572 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 84042 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data 258892 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 817506 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst 499428 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 563836 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 126587 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 110029 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 323447 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 330566 # number of demand (read+write) hits
system.l2c.demand_hits::total 1953893 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 499428 # number of overall hits
system.l2c.overall_hits::cpu0.data 563836 # number of overall hits
system.l2c.overall_hits::cpu1.inst 126587 # number of overall hits
system.l2c.overall_hits::cpu1.data 110029 # number of overall hits
system.l2c.overall_hits::cpu2.inst 323447 # number of overall hits
system.l2c.overall_hits::cpu2.data 330566 # number of overall hits
system.l2c.overall_hits::total 1953893 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 11 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 19 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu2.data 2 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 73154 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 17979 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 24640 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 115773 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 7283 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 2297 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst 4777 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 14357 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 240513 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 15763 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data 16963 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 273239 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst 7283 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 313667 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2297 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 33742 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 4777 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 41603 # number of demand (read+write) misses
system.l2c.demand_misses::total 403369 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 7283 # number of overall misses
system.l2c.overall_misses::cpu0.data 313667 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2297 # number of overall misses
system.l2c.overall_misses::cpu1.data 33742 # number of overall misses
system.l2c.overall_misses::cpu2.inst 4777 # number of overall misses
system.l2c.overall_misses::cpu2.data 41603 # number of overall misses
system.l2c.overall_misses::total 403369 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu2.data 364000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 364000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu2.data 62000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 62000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1368020000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 2194273500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 3562293500 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 188368000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 396841000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 585209000 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 1170378000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data 1263948500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 2434326500 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst 188368000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 2538398000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 396841000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 3458222000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 6581829000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst 188368000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 2538398000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 396841000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 3458222000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 6581829000 # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks 835650 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 835650 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 33 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data 11 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 162418 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 43966 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 96314 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 302698 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 506711 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 128884 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst 328224 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 963819 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 715085 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 99805 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data 275855 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 1090745 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 506711 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 877503 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 128884 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 143771 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 328224 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 372169 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2357262 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 506711 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 877503 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 128884 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 143771 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 328224 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 372169 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2357262 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.523810 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.575758 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.181818 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.181818 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.450406 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.408930 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.255830 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.382470 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014373 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.017822 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.014554 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.014896 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.336342 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.157938 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.061492 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.250507 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014373 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.357454 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.017822 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.234693 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.014554 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.111785 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.171118 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.014373 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.357454 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.017822 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.234693 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.014554 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.111785 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.171118 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 33090.909091 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 19157.894737 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 31000 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 31000 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76089.882641 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 89053.307630 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 30769.639726 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82006.094906 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83073.267741 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 40761.231455 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 74248.429867 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 74512.085126 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 8909.147303 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 82006.094906 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 75229.624800 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 83073.267741 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 83124.341995 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 16317.141377 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 82006.094906 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 75229.624800 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 83073.267741 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 83124.341995 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 16317.141377 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 75401 # number of writebacks
system.l2c.writebacks::total 75401 # number of writebacks
system.l2c.CleanEvict_mshr_misses::writebacks 185 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 185 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 11 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 2 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 17979 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 24640 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 42619 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2297 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 4777 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 7074 # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 15763 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 16963 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 32726 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 2297 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 33742 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 4777 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 41603 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 82419 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 2297 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 33742 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 4777 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 41603 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 82419 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 1107 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data 1558 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 2665 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 1386 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data 2128 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 3514 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2493 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data 3686 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 6179 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 377000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 377000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 42000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 42000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1188230000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1947873500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 3136103500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 165398000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 349071000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 514469000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 1012748000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1095055000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 2107803000 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 165398000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 2200978000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 349071000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 3042928500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 5758375500 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 165398000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 2200978000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 349071000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 3042928500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 5758375500 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 212390000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 314717500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 527107500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 282261000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 426497000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 708758000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 494651000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 741214500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 1235865500 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.523810 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408930 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.255830 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.140797 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017822 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014554 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.007340 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.157938 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.061492 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.030003 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017822 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.234693 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014554 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.111785 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.034964 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017822 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.234693 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014554 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.111785 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.034964 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 34272.727273 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 34272.727273 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 21000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 21000 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66089.882641 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 79053.307630 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 73584.633614 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72006.094906 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73073.267741 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72726.745830 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 64248.429867 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 64555.503154 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 64407.596407 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72006.094906 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65229.624800 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73073.267741 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73142.045045 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 69867.087686 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72006.094906 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65229.624800 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73073.267741 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73142.045045 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 69867.087686 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191860.885276 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 202000.962773 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197788.930582 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203651.515152 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200421.522556 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201695.503699 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 198415.964701 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 201089.120998 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 200010.600421 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 7144 # Transaction distribution
system.membus.trans_dist::ReadResp 294907 # Transaction distribution
system.membus.trans_dist::WriteReq 9810 # Transaction distribution
system.membus.trans_dist::WriteResp 9810 # Transaction distribution
system.membus.trans_dist::Writeback 116913 # Transaction distribution
system.membus.trans_dist::CleanEvict 262319 # Transaction distribution
system.membus.trans_dist::UpgradeReq 141 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 143 # Transaction distribution
system.membus.trans_dist::ReadExReq 115651 # Transaction distribution
system.membus.trans_dist::ReadExResp 115651 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 287769 # Transaction distribution
system.membus.trans_dist::BadAddressError 6 # Transaction distribution
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1144270 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 1178190 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125023 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 125023 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1303213 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30626752 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 30672320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 33336640 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 157 # Total snoops (count)
system.membus.snoop_fanout::samples 841369 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 841369 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 841369 # Request fanout histogram
system.membus.reqLayer0.occupancy 11017000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 393892331 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 7500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 441141955 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 29902743 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2061814 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 883059 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 1572257 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 33 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 44 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 302698 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 302698 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 963876 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 1090815 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 17280 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2890767 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4213603 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 7104370 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61685760 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142710656 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 204396416 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 141516 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 4871742 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.029009 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.167832 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 4730418 97.10% 97.10% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 141324 2.90% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 4871742 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 1371248000 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 82500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 686121188 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 778360963 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu2.kern.mode_switch::kernel 0 # number of protection mode switches
system.cpu2.kern.mode_switch::user 0 # number of protection mode switches
system.cpu2.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu2.kern.mode_good::kernel 0
system.cpu2.kern.mode_good::user 0
system.cpu2.kern.mode_good::idle 0
system.cpu2.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::user nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu2.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu2.kern.swap_context 0 # number of times the context was actually changed
---------- End Simulation Statistics ----------
|