path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.841682                       # Number of seconds simulated
sim_ticks                                1841681669500                       # Number of ticks simulated
final_tick                               1841681669500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 340900                       # Simulator instruction rate (inst/s)
host_op_rate                                   340900                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             9082220288                       # Simulator tick rate (ticks/s)
host_mem_usage                                 309920                       # Number of bytes of host memory used
host_seconds                                   202.78                       # Real time elapsed on the host
sim_insts                                    69127289                       # Number of instructions simulated
sim_ops                                      69127289                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst           474944                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         19316864                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           149888                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          2832832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           295936                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          2722176                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28444928                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       474944                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       149888                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       295936                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          920768                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7479680                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7479680                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst              7421                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            301826                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2342                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             44263                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              4624                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             42534                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                444452                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          116870                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               116870                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              257886                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            10488709                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1440145                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               81386                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1538177                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst              160688                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             1478093                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15445084                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         257886                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          81386                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst         160688                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             499960                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4061332                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4061332                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4061332                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             257886                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           10488709                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1440145                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              81386                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1538177                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst             160688                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            1478093                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19506416                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        111038                       # Total number of read requests seen
system.physmem.writeReqs                        46173                       # Total number of write requests seen
system.physmem.cpureqs                         157553                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                      7106432                       # Total number of bytes read from memory
system.physmem.bytesWritten                   2955072                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                7106432                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                2955072                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        7                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                 41                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                  7075                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                  6835                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                  6921                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                  6580                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                  7013                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                  7160                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                  7199                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                  7176                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                  6821                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                  6547                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                 6956                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                 7030                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                 7021                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                 7068                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                 6779                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                 6850                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  3087                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  2885                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  2926                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  2583                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  2986                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  3014                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  3032                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  2994                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  2761                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  2529                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 2745                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 2938                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 3117                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 3088                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 2763                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 2725                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                         141                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1840669582000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  111038                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                  46314                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                   41                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                     82621                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     10884                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      5829                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1945                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      1200                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       997                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       753                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       844                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       697                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       809                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      664                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      650                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      686                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      750                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      521                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      613                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      369                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      106                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       53                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       38                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      1636                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      1922                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      1953                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      1976                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      2005                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      2005                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      2016                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      2010                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      2008                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      2007                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     2004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     2002                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     2001                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     1999                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     1997                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1996                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1995                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1993                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     1992                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     1989                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     1988                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     1988                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     1986                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                      425                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                     1659441821                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                3549387821                       # Sum of mem lat for all requests
system.physmem.totBusLat                    444124000                       # Total cycles spent in databus access
system.physmem.totBankLat                  1445822000                       # Total cycles spent in bank access
system.physmem.avgQLat                       14945.75                       # Average queueing delay per request
system.physmem.avgBankLat                    13021.79                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  31967.54                       # Average memory access latency
system.physmem.avgRdBW                           3.86                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           1.60                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   3.86                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.60                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                         0.18                       # Average write queue length over time
system.physmem.readRowHits                     102865                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     29619                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   92.65                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  64.15                       # Row buffer hit rate for writes
system.physmem.avgGap                     11708274.75                       # Average gap between requests
system.l2c.replacements                        337510                       # number of replacements
system.l2c.tagsinuse                     65417.862524                       # Cycle average of tags in use
system.l2c.total_refs                         2476071                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        402672                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          6.149102                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                     614754000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        54764.758873                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          2313.964866                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          2687.926844                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst           585.029609                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data           664.408286                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst          2261.220547                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data          2140.553499                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.835644                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.035308                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.041015                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.008927                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.010138                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst            0.034503                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data            0.032662                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.998197                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst             513879                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             491618                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             126890                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              82632                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst             299640                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data             242724                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1757383                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          835771                       # number of Writeback hits
system.l2c.Writeback_hits::total               835771                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   7                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data             1                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 1                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            91841                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            27111                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            67748                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               186700                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              513879                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              583459                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              126890                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              109743                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              299640                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              310472                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1944083                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             513879                       # number of overall hits
system.l2c.overall_hits::cpu0.data             583459                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             126890                       # number of overall hits
system.l2c.overall_hits::cpu1.data             109743                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             299640                       # number of overall hits
system.l2c.overall_hits::cpu2.data             310472                       # number of overall hits
system.l2c.overall_hits::total                1944083                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst             7421                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           224850                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             2342                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data            23206                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst             4624                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data            25196                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               287639                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data             8                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            11                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                19                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          77252                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          21108                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          17439                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             115799                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst              7421                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            302102                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2342                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             44314                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              4624                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             42635                       # number of demand (read+write) misses
system.l2c.demand_misses::total                403438                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst             7421                       # number of overall misses
system.l2c.overall_misses::cpu0.data           302102                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2342                       # number of overall misses
system.l2c.overall_misses::cpu1.data            44314                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             4624                       # number of overall misses
system.l2c.overall_misses::cpu2.data            42635                       # number of overall misses
system.l2c.overall_misses::total               403438                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst    130356500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data   1043168500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst    266603500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data   1103490500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     2543619000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data       292500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       292500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1001535000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   1445654500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2447189500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst    130356500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   2044703500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    266603500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   2549145000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      4990808500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst    130356500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   2044703500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    266603500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   2549145000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     4990808500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         521300                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         716468                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         129232                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         105838                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst         304264                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data         267920                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2045022                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       835771                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           835771                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           11                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data            1                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           14                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              26                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       169093                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        48219                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        85187                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           302499                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          521300                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          885561                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          129232                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          154057                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          304264                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          353107                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2347521                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         521300                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         885561                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         129232                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         154057                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         304264                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         353107                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2347521                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.014236                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.313831                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.018122                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.219260                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.015197                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.094043                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.140653                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.727273                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.785714                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.730769                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.456861                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.437753                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.204714                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.382808                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.014236                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.341142                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.018122                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.287647                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.015197                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.120742                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.171857                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.014236                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.341142                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.018122                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.287647                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.015197                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.120742                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.171857                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55660.333049                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 44952.533827                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 57656.466263                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 43796.257342                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total  8843.094991                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 26590.909091                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 15394.736842                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47448.123934                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82897.786570                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 21133.079733                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 55660.333049                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 46141.253329                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 57656.466263                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 59789.961299                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 12370.695125                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 55660.333049                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 46141.253329                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 57656.466263                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 59789.961299                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 12370.695125                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               75358                       # number of writebacks
system.l2c.writebacks::total                    75358                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu1.inst         2342                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data        23206                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst         4624                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data        25196                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           55368                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           11                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           11                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        21108                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        17439                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         38547                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2342                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        44314                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         4624                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        42635                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            93915                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2342                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        44314                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         4624                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        42635                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           93915                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    100735600                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    741824698                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    208189401                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data    781867294                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1832616993                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       268008                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total       268008                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    729164916                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1230457925                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1959622841                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    100735600                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1470989614                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    208189401                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   2012325219                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   3792239834                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    100735600                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1470989614                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    208189401                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   2012325219                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   3792239834                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    271229500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    318212500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total    589442000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    338412000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    391990000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total    730402000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    609641500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data    710202500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   1319844000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.018122                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.219260                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.015197                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.094043                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.027075                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.785714                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.423077                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.437753                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.204714                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.127429                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.018122                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.287647                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.015197                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.120742                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.040006                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.018122                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.287647                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.015197                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.120742                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.040006                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43012.638770                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 31966.935189                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 45023.659386                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 31031.405541                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 33098.847583                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 24364.363636                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 24364.363636                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34544.481524                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70557.825850                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 50837.233533                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43012.638770                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33194.692738                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 45023.659386                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 47198.902756                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40379.490326                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43012.638770                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33194.692738                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 45023.659386                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 47198.902756                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40379.490326                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41685                       # number of replacements
system.iocache.tagsinuse                     1.255489                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1693868794000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       1.255489                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.078468                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.078468                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide      9177998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total      9177998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide   3943215289                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   3943215289                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide   3952393287                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   3952393287                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide   3952393287                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   3952393287                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 53052.011561                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 94898.327132                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 94898.327132                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 94724.824134                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 94724.824134                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 94724.824134                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 94724.824134                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         78884                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 9633                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.188934                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide           69                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total           69                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        17280                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        17280                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        17349                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        17349                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        17349                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        17349                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5589000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total      5589000                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   3043794338                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   3043794338                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   3049383338                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   3049383338                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   3049383338                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   3049383338                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.398844                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.398844                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide     0.415864                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total     0.415864                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide     0.415794                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.415794                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide     0.415794                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.415794                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide        81000                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total        81000                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176145.505671                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 176145.505671                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175767.095395                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 175767.095395                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175767.095395                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 175767.095395                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     4863195                       # DTB read hits
system.cpu0.dtb.read_misses                      5912                       # DTB read misses
system.cpu0.dtb.read_acv                          109                       # DTB read access violations
system.cpu0.dtb.read_accesses                  426831                       # DTB read accesses
system.cpu0.dtb.write_hits                    3494205                       # DTB write hits
system.cpu0.dtb.write_misses                      658                       # DTB write misses
system.cpu0.dtb.write_acv                          81                       # DTB write access violations
system.cpu0.dtb.write_accesses                 163149                       # DTB write accesses
system.cpu0.dtb.data_hits                     8357400                       # DTB hits
system.cpu0.dtb.data_misses                      6570                       # DTB misses
system.cpu0.dtb.data_acv                          190                       # DTB access violations
system.cpu0.dtb.data_accesses                  589980                       # DTB accesses
system.cpu0.itb.fetch_hits                    2736814                       # ITB hits
system.cpu0.itb.fetch_misses                     2973                       # ITB misses
system.cpu0.itb.fetch_acv                          97                       # ITB acv
system.cpu0.itb.fetch_accesses                2739787                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       928581953                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   32231633                       # Number of instructions committed
system.cpu0.committedOps                     32231633                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             30115221                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                167520                       # Number of float alu accesses
system.cpu0.num_func_calls                     807051                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      4228078                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    30115221                       # number of integer instructions
system.cpu0.num_fp_insts                       167520                       # number of float instructions
system.cpu0.num_int_register_reads           41941415                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          22024555                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads               86513                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes              88077                       # number of times the floating registers were written
system.cpu0.num_mem_refs                      8386802                       # number of memory refs
system.cpu0.num_load_insts                    4883995                       # Number of load instructions
system.cpu0.num_store_insts                   3502807                       # Number of store instructions
system.cpu0.num_idle_cycles              214040611553.999786                       # Number of idle cycles
system.cpu0.num_busy_cycles              -213112029600.999786                       # Number of busy cycles
system.cpu0.not_idle_fraction             -229.502661                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                  230.502661                       # Percentage of idle cycles
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6419                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    211372                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   74800     40.97%     40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1878      1.03%     42.11% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                 105685     57.89%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              182566                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    73433     49.30%     49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1878      1.26%     50.70% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   73433     49.30%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               148947                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1818611622000     98.75%     98.75% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               39272500      0.00%     98.75% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              363381500      0.02%     98.77% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            22666637000      1.23%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1841680913000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.981725                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.694829                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.815853                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      2.45%      2.45% # number of syscalls executed
system.cpu0.kern.syscall::3                        30      9.20%     11.66% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.23%     12.88% # number of syscalls executed
system.cpu0.kern.syscall::6                        42     12.88%     25.77% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.31%     26.07% # number of syscalls executed
system.cpu0.kern.syscall::15                        1      0.31%     26.38% # number of syscalls executed
system.cpu0.kern.syscall::17                       15      4.60%     30.98% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      3.07%     34.05% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      1.84%     35.89% # number of syscalls executed
system.cpu0.kern.syscall::23                        4      1.23%     37.12% # number of syscalls executed
system.cpu0.kern.syscall::24                        6      1.84%     38.96% # number of syscalls executed
system.cpu0.kern.syscall::33                       11      3.37%     42.33% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.61%     42.94% # number of syscalls executed
system.cpu0.kern.syscall::45                       54     16.56%     59.51% # number of syscalls executed
system.cpu0.kern.syscall::47                        6      1.84%     61.35% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      3.07%     64.42% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      3.07%     67.48% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.31%     67.79% # number of syscalls executed
system.cpu0.kern.syscall::59                        7      2.15%     69.94% # number of syscalls executed
system.cpu0.kern.syscall::71                       54     16.56%     86.50% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      0.92%     87.42% # number of syscalls executed
system.cpu0.kern.syscall::74                       16      4.91%     92.33% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.31%     92.64% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      0.92%     93.56% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      2.76%     96.32% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.61%     96.93% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.61%     97.55% # number of syscalls executed
system.cpu0.kern.syscall::132                       4      1.23%     98.77% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.61%     99.39% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.61%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   326                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 4175      2.17%      2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi                      54      0.03%      2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.21% # number of callpals executed
system.cpu0.kern.callpal::swpipl               175309     91.20%     93.41% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6782      3.53%     96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     7      0.00%     96.94% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.00%     96.94% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.95% # number of callpals executed
system.cpu0.kern.callpal::rti                    5175      2.69%     99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys                 515      0.27%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     181      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                192221                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             5922                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1736                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle               2094                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1905                      
system.cpu0.kern.mode_good::user                 1736                      
system.cpu0.kern.mode_good::idle                  169                      
system.cpu0.kern.mode_switch_good::kernel     0.321682                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle      0.080707                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.390689                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel       29776947000      1.62%      1.62% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          2543344500      0.14%      1.75% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle        1809360618000     98.25%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    4176                       # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.icache.replacements                954146                       # number of replacements
system.cpu0.icache.tagsinuse               511.198138                       # Cycle average of tags in use
system.cpu0.icache.total_refs                41733941                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                954657                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                 43.716163                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           10235539000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   257.559886                       # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst    79.204756                       # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu2.inst   174.433495                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.503047                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst     0.154697                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu2.inst     0.340690                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.998434                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst     31717072                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      7719142                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      2297727                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       41733941                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     31717072                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      7719142                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      2297727                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        41733941                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     31717072                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      7719142                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      2297727                       # number of overall hits
system.cpu0.icache.overall_hits::total       41733941                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       521321                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       129232                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       321175                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       971728                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       521321                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       129232                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       321175                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        971728                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       521321                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       129232                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       321175                       # number of overall misses
system.cpu0.icache.overall_misses::total       971728                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1794278000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4429709988                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   6223987988                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   1794278000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   4429709988                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   6223987988                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   1794278000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   4429709988                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   6223987988                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     32238393                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      7848374                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      2618902                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     42705669                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     32238393                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      7848374                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      2618902                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     42705669                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     32238393                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      7848374                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      2618902                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     42705669                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016171                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016466                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122637                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.022754                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016171                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016466                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.122637                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.022754                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016171                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016466                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122637                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.022754                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13884.161818                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13792.200476                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  6405.072189                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13884.161818                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13792.200476                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  6405.072189                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13884.161818                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13792.200476                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  6405.072189                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         1920                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets          179                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              117                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.410256                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          179                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16896                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        16896                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        16896                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        16896                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        16896                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        16896                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       129232                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       304279                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       433511                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       129232                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       304279                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       433511                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       129232                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       304279                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       433511                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1535814000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3651354490                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   5187168490                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1535814000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3651354490                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   5187168490                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1535814000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3651354490                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   5187168490                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016466                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116186                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010151                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016466                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116186                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.010151                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016466                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116186                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.010151                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11884.161818                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12000.021329                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11965.482975                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11884.161818                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12000.021329                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11965.482975                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11884.161818                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12000.021329                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11965.482975                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1392176                       # number of replacements
system.cpu0.dcache.tagsinuse               511.997817                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                13319375                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1392688                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                  9.563790                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              10840000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   250.475263                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data    85.370425                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu2.data   176.152129                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.489209                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data     0.166739                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu2.data     0.344047                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.999996                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      4041121                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      1096850                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      2424578                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        7562549                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3198610                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data       859334                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      1312800                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       5370744                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       116325                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19408                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        49694                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       185427                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       125372                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21487                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data        53741                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       200600                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      7239731                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      1956184                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      3737378                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        12933293                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      7239731                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      1956184                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      3737378                       # number of overall hits
system.cpu0.dcache.overall_hits::total       12933293                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       706861                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       103630                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       548850                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1359341                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       169104                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        48220                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       560755                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       778079                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9607                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2208                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7000                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        18815                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       875965                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       151850                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data      1109605                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2137420                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       875965                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       151850                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1109605                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2137420                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2161032000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9421132500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  11582164500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1417971000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  15685694174                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  17103665174                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     29185500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    103516500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    132702000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        13000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total        13000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   3579003000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  25106826674                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  28685829674                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   3579003000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  25106826674                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  28685829674                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      4747982                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      1200480                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      2973428                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8921890                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      3367714                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data       907554                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      1873555                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      6148823                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       125932                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21616                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        56694                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       204242                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       125372                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21487                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        53742                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       200601                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data      8115696                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      2108034                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      4846983                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     15070713                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data      8115696                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      2108034                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      4846983                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     15070713                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.148876                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.086324                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.184585                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.152360                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.050213                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.053132                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.299300                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.126541                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.076287                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.102147                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.123470                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.092121                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000019                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000005                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.107935                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.072034                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.228927                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.141826                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.107935                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.072034                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.228927                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.141826                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 20853.343626                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17165.222738                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total  8520.426074                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29406.283700                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27972.455304                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 21981.913371                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13218.070652                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14788.071429                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  7052.989636                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23569.331577                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 22626.814654                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13420.773490                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23569.331577                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22626.814654                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13420.773490                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       505614                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets          672                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            16873                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    29.965863                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets           96                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       835771                       # number of writebacks
system.cpu0.dcache.writebacks::total           835771                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       286220                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       286220                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       475804                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       475804                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1462                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1462                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       762024                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       762024                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       762024                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       762024                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       103630                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       262630                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       366260                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        48220                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        84951                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       133171                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2208                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5538                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7746                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       151850                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       347581                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       499431                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       151850                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       347581                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       499431                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1953772000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4295599000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6249371000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1321531000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2301660126                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   3623191126                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     24769500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     70346000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     95115500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        11000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        11000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3275303000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   6597259126                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   9872562126                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3275303000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   6597259126                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   9872562126                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    289521000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    340019500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    629540500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    358537000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    415967500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    774504500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    648058000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    755987000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1404045000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.086324                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.088326                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.041052                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.053132                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.045342                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.021658                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.102147                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.097682                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.037926                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000019                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.072034                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.071711                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.033139                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.072034                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.071711                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.033139                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18853.343626                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16356.086510                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17062.663135                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27406.283700                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27093.973302                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27207.058038                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11218.070652                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12702.419646                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12279.305448                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21569.331577                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18980.494118                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19767.619803                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21569.331577                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18980.494118                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19767.619803                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1219761                       # DTB read hits
system.cpu1.dtb.read_misses                      1488                       # DTB read misses
system.cpu1.dtb.read_acv                           40                       # DTB read access violations
system.cpu1.dtb.read_accesses                  143779                       # DTB read accesses
system.cpu1.dtb.write_hits                     929431                       # DTB write hits
system.cpu1.dtb.write_misses                      201                       # DTB write misses
system.cpu1.dtb.write_acv                          24                       # DTB write access violations
system.cpu1.dtb.write_accesses                  59743                       # DTB write accesses
system.cpu1.dtb.data_hits                     2149192                       # DTB hits
system.cpu1.dtb.data_misses                      1689                       # DTB misses
system.cpu1.dtb.data_acv                           64                       # DTB access violations
system.cpu1.dtb.data_accesses                  203522                       # DTB accesses
system.cpu1.itb.fetch_hits                     873235                       # ITB hits
system.cpu1.itb.fetch_misses                      756                       # ITB misses
system.cpu1.itb.fetch_acv                          43                       # ITB acv
system.cpu1.itb.fetch_accesses                 873991                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                       953535739                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                    7846620                       # Number of instructions committed
system.cpu1.committedOps                      7846620                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses              7299077                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                 45739                       # Number of float alu accesses
system.cpu1.num_func_calls                     212215                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts       957639                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                     7299077                       # number of integer instructions
system.cpu1.num_fp_insts                        45739                       # number of float instructions
system.cpu1.num_int_register_reads           10142741                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           5309758                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads               24689                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              24953                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      2156913                       # number of memory refs
system.cpu1.num_load_insts                    1225031                       # Number of load instructions
system.cpu1.num_store_insts                    931882                       # Number of store instructions
system.cpu1.num_idle_cycles              -1658749274.077502                       # Number of idle cycles
system.cpu1.num_busy_cycles              2612285013.077502                       # Number of busy cycles
system.cpu1.not_idle_fraction                2.739577                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                   -1.739577                       # Percentage of idle cycles
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                         0                       # number of hwrei instructions executed
system.cpu1.kern.mode_switch::kernel                0                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                  0                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                  0                      
system.cpu1.kern.mode_good::user                    0                      
system.cpu1.kern.mode_good::idle                    0                      
system.cpu1.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
system.cpu2.dtb.fetch_hits                          0                       # ITB hits
system.cpu2.dtb.fetch_misses                        0                       # ITB misses
system.cpu2.dtb.fetch_acv                           0                       # ITB acv
system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu2.dtb.read_hits                     3234016                       # DTB read hits
system.cpu2.dtb.read_misses                     12170                       # DTB read misses
system.cpu2.dtb.read_acv                          136                       # DTB read access violations
system.cpu2.dtb.read_accesses                  218383                       # DTB read accesses
system.cpu2.dtb.write_hits                    2000862                       # DTB write hits
system.cpu2.dtb.write_misses                     2630                       # DTB write misses
system.cpu2.dtb.write_acv                         139                       # DTB write access violations
system.cpu2.dtb.write_accesses                  81465                       # DTB write accesses
system.cpu2.dtb.data_hits                     5234878                       # DTB hits
system.cpu2.dtb.data_misses                     14800                       # DTB misses
system.cpu2.dtb.data_acv                          275                       # DTB access violations
system.cpu2.dtb.data_accesses                  299848                       # DTB accesses
system.cpu2.itb.fetch_hits                     374542                       # ITB hits
system.cpu2.itb.fetch_misses                     5731                       # ITB misses
system.cpu2.itb.fetch_acv                         284                       # ITB acv
system.cpu2.itb.fetch_accesses                 380273                       # ITB accesses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.read_acv                            0                       # DTB read access violations
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.write_acv                           0                       # DTB write access violations
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.data_hits                           0                       # DTB hits
system.cpu2.itb.data_misses                         0                       # DTB misses
system.cpu2.itb.data_acv                            0                       # DTB access violations
system.cpu2.itb.data_accesses                       0                       # DTB accesses
system.cpu2.numCycles                        30548805                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.BPredUnit.lookups                 8364028                       # Number of BP lookups
system.cpu2.BPredUnit.condPredicted           7669410                       # Number of conditional branches predicted
system.cpu2.BPredUnit.condIncorrect            129868                       # Number of conditional branches incorrect
system.cpu2.BPredUnit.BTBLookups              6711241                       # Number of BTB lookups
system.cpu2.BPredUnit.BTBHits                 5709819                       # Number of BTB hits
system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.BPredUnit.usedRAS                  287796                       # Number of times the RAS was used to get a target.
system.cpu2.BPredUnit.RASInCorrect              15290                       # Number of incorrect RAS predictions.
system.cpu2.fetch.icacheStallCycles           8565342                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                      34820498                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                    8364028                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches           5997615                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                      8085140                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                 623390                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles               9684769                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles               10169                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles             1946                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        65267                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles        78430                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          219                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  2618903                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                90402                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples          26897224                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.294576                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.310232                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                18812084     69.94%     69.94% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  275091      1.02%     70.96% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                  443313      1.65%     72.61% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                 4200168     15.62%     88.23% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  736557      2.74%     90.97% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  167312      0.62%     91.59% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  197037      0.73%     92.32% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  432029      1.61%     93.93% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                 1633633      6.07%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total            26897224                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.273792                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.139832                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                 8682356                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles              9793254                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                  7488405                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles               293704                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                393556                       # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved              170875                       # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred                13042                       # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts              34420320                       # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts                40663                       # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles                393556                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                 9037496                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                2819097                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles       5808677                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                  7346220                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles              1246237                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts              33260279                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents                 2326                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents                233903                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents               407997                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands           22331754                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups             41424509                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups        41259136                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups           165373                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps             20496437                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                 1835317                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            510420                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts         61593                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                  3691952                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             3399315                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            2093436                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           371907                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          254715                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                  30727225                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             632539                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                 30272118                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued            35753                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        2189784                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined      1100567                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved        445757                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples     26897224                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.125474                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.564893                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           15350394     57.07%     57.07% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            3115885     11.58%     68.65% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            1557090      5.79%     74.44% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            5021564     18.67%     93.11% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4             911830      3.39%     96.50% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5             491728      1.83%     98.33% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6             288005      1.07%     99.40% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             142453      0.53%     99.93% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8              18275      0.07%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total       26897224                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                  35285     14.01%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     14.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                113269     44.96%     58.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite               103382     41.04%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass             2456      0.01%      0.01% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu             24555706     81.12%     81.12% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               20320      0.07%     81.19% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     81.19% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd               8506      0.03%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv               1228      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead             3366886     11.12%     92.35% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            2024055      6.69%     99.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess            292961      0.97%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total              30272118                       # Type of FU issued
system.cpu2.iq.rate                          0.990943                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                     251936                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.008322                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads          87492046                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes         33437480                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses     29866501                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads             237103                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes            115982                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses       112325                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses              30398156                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                 123442                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          190063                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads       422258                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses          952                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         4004                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       162752                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads         4980                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked        23112                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                393556                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                2038103                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles               212197                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts           32647760                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts           228888                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              3399315                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             2093436                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            561709                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                150503                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                 2400                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          4004                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect         66845                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       130356                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              197201                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts             30107405                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts              3254707                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           164713                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                      1287996                       # number of nop insts executed
system.cpu2.iew.exec_refs                     5262746                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                 6765344                       # Number of branches executed
system.cpu2.iew.exec_stores                   2008039                       # Number of stores executed
system.cpu2.iew.exec_rate                    0.985551                       # Inst execution rate
system.cpu2.iew.wb_sent                      30012235                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                     29978826                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                 17295143                       # num instructions producing a value
system.cpu2.iew.wb_consumers                 20538847                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      0.981342                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.842070                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        2374409                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         186782                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           183048                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples     26503668                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.140514                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.850633                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     16405527     61.90%     61.90% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      2337415      8.82%     70.72% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1218938      4.60%     75.32% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3      4753611     17.94%     93.25% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       502619      1.90%     95.15% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       186793      0.70%     95.85% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       180491      0.68%     96.54% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7       181897      0.69%     97.22% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8       736377      2.78%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total     26503668                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts            30227806                       # Number of instructions committed
system.cpu2.commit.committedOps              30227806                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       4907741                       # Number of memory references committed
system.cpu2.commit.loads                      2977057                       # Number of loads committed
system.cpu2.commit.membars                      65125                       # Number of memory barriers committed
system.cpu2.commit.branches                   6615814                       # Number of branches committed
system.cpu2.commit.fp_insts                    111064                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                 28762873                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              231817                       # Number of function calls committed.
system.cpu2.commit.bw_lim_events               736377                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                    58294713                       # The number of ROB reads
system.cpu2.rob.rob_writes                   65597739                       # The number of ROB writes
system.cpu2.timesIdled                         244101                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                        3651581                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  1745276463                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                   29049036                       # Number of Instructions Simulated
system.cpu2.committedOps                     29049036                       # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total             29049036                       # Number of Instructions Simulated
system.cpu2.cpi                              1.051629                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        1.051629                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.950906                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.950906                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                39585060                       # number of integer regfile reads
system.cpu2.int_regfile_writes               21198431                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    68487                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   68830                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                4557721                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                264115                       # number of misc regfile writes
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei                         0                       # number of hwrei instructions executed
system.cpu2.kern.mode_switch::kernel                0                       # number of protection mode switches
system.cpu2.kern.mode_switch::user                  0                       # number of protection mode switches
system.cpu2.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu2.kern.mode_good::kernel                  0                      
system.cpu2.kern.mode_good::user                    0                      
system.cpu2.kern.mode_good::idle                    0                      
system.cpu2.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
system.cpu2.kern.swap_context                       0                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------