path: root/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.841612                       # Number of seconds simulated
sim_ticks                                1841612285000                       # Number of ticks simulated
final_tick                               1841612285000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 168459                       # Simulator instruction rate (inst/s)
host_op_rate                                   168459                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4750760669                       # Simulator tick rate (ticks/s)
host_mem_usage                                 319468                       # Number of bytes of host memory used
host_seconds                                   387.65                       # Real time elapsed on the host
sim_insts                                    65302548                       # Number of instructions simulated
sim_ops                                      65302548                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst           475840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         19999104                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           147008                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          2248128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           298624                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          2645376                       # Number of bytes read from this memory
system.physmem.bytes_read::total             25815040                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       475840                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       147008                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       298624                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          921472                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4825408                       # Number of bytes written to this memory
system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7484736                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst              7435                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            312486                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2297                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             35127                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              4666                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             41334                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                403360                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           75397                       # Number of write requests responded to by this memory
system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               116949                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              258382                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            10859563                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               521                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               79826                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1220739                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst              162154                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             1436446                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                14017630                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         258382                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          79826                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst         162154                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             500362                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2620208                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::tsunami.ide          1444022                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4064230                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2620208                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             258382                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           10859563                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1444543                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              79826                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1220739                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst             162154                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            1436446                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               18081860                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         83439                       # Number of read requests accepted
system.physmem.writeReqs                        46740                       # Number of write requests accepted
system.physmem.readBursts                       83439                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      46740                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  5337024                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      3072                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   2989888                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   5340096                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                2991360                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       48                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs             52                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                5256                       # Per bank write bursts
system.physmem.perBankRdBursts::1                5087                       # Per bank write bursts
system.physmem.perBankRdBursts::2                5115                       # Per bank write bursts
system.physmem.perBankRdBursts::3                5179                       # Per bank write bursts
system.physmem.perBankRdBursts::4                5173                       # Per bank write bursts
system.physmem.perBankRdBursts::5                5205                       # Per bank write bursts
system.physmem.perBankRdBursts::6                5267                       # Per bank write bursts
system.physmem.perBankRdBursts::7                5273                       # Per bank write bursts
system.physmem.perBankRdBursts::8                5423                       # Per bank write bursts
system.physmem.perBankRdBursts::9                5013                       # Per bank write bursts
system.physmem.perBankRdBursts::10               5464                       # Per bank write bursts
system.physmem.perBankRdBursts::11               5273                       # Per bank write bursts
system.physmem.perBankRdBursts::12               4813                       # Per bank write bursts
system.physmem.perBankRdBursts::13               5124                       # Per bank write bursts
system.physmem.perBankRdBursts::14               5602                       # Per bank write bursts
system.physmem.perBankRdBursts::15               5124                       # Per bank write bursts
system.physmem.perBankWrBursts::0                2825                       # Per bank write bursts
system.physmem.perBankWrBursts::1                2787                       # Per bank write bursts
system.physmem.perBankWrBursts::2                2858                       # Per bank write bursts
system.physmem.perBankWrBursts::3                3069                       # Per bank write bursts
system.physmem.perBankWrBursts::4                3024                       # Per bank write bursts
system.physmem.perBankWrBursts::5                2822                       # Per bank write bursts
system.physmem.perBankWrBursts::6                3224                       # Per bank write bursts
system.physmem.perBankWrBursts::7                2821                       # Per bank write bursts
system.physmem.perBankWrBursts::8                3331                       # Per bank write bursts
system.physmem.perBankWrBursts::9                2683                       # Per bank write bursts
system.physmem.perBankWrBursts::10               3131                       # Per bank write bursts
system.physmem.perBankWrBursts::11               2953                       # Per bank write bursts
system.physmem.perBankWrBursts::12               2475                       # Per bank write bursts
system.physmem.perBankWrBursts::13               2748                       # Per bank write bursts
system.physmem.perBankWrBursts::14               3227                       # Per bank write bursts
system.physmem.perBankWrBursts::15               2739                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
system.physmem.totGap                    1840600008500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   83439                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  46740                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     66354                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      7773                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      7422                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1810                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        22                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                        77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        43                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        40                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        37                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        37                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      767                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1047                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1667                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     1853                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     2167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     2639                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     2784                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     3311                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     3494                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     3486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     3386                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     3454                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     2908                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     2754                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     2263                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     2169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     2170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     2109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       43                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       39                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        2                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        21530                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      386.758569                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     220.447203                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     381.120515                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127           7019     32.60%     32.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         4847     22.51%     55.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         1849      8.59%     63.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1051      4.88%     68.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639          911      4.23%     72.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          506      2.35%     75.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          375      1.74%     76.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          418      1.94%     78.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         4554     21.15%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          21530                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          2040                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        40.873529                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     1027.655163                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           2038     99.90%     99.90% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.05%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.05%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            2040                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          2040                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.900490                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.614282                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       22.575456                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                33      1.62%      1.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 7      0.34%      1.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                1      0.05%      2.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15               5      0.25%      2.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            1695     83.09%     85.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              37      1.81%     87.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27               5      0.25%     87.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             107      5.25%     92.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35               7      0.34%     92.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39               2      0.10%     93.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43               1      0.05%     93.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               3      0.15%     93.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51               8      0.39%     93.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               1      0.05%     93.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               1      0.05%     93.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67               2      0.10%     93.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               1      0.05%     93.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               2      0.10%     94.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               2      0.10%     94.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               8      0.39%     94.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               3      0.15%     94.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               3      0.15%     94.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.10%     94.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99              78      3.82%     98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.05%     98.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.10%     98.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.05%     98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             7      0.34%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             2      0.10%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             3      0.15%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.05%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             3      0.15%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.05%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.05%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227             4      0.20%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            2040                       # Writes before turning the bus around for reads
system.physmem.totQLat                      869064750                       # Total ticks spent queuing
system.physmem.totMemAccLat                2432646000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    416955000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10421.57                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29171.57                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.90                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.62                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.90                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.62                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.19                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         8.28                       # Average write queue length when enqueuing
system.physmem.readRowHits                      71609                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     36969                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   85.87                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  79.09                       # Row buffer hit rate for writes
system.physmem.avgGap                     14138993.30                       # Average gap between requests
system.physmem.pageHitRate                      83.44                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     1766589196000                       # Time in different power states
system.physmem.memoryStateTime::REF       61495460000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       13527240250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                     18112095                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq               44765                       # Transaction distribution
system.membus.trans_dist::ReadResp              44760                       # Transaction distribution
system.membus.trans_dist::WriteReq               3528                       # Transaction distribution
system.membus.trans_dist::WriteResp              3528                       # Transaction distribution
system.membus.trans_dist::Writeback             29460                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        17280                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        17280                       # Transaction distribution
system.membus.trans_dist::UpgradeReq               50                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              52                       # Transaction distribution
system.membus.trans_dist::ReadExReq             41656                       # Transaction distribution
system.membus.trans_dist::ReadExResp            41656                       # Transaction distribution
system.membus.trans_dist::BadAddressError            5                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        12900                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       196412                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       209322                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        34645                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        34645                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 243967                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        15792                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      7224576                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total      7240368                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      1106880                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      1106880                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total             8347248                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               33351936                       # Total data (bytes)
system.membus.snoop_data_through_bus             3520                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            11434500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           517398750                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy                6500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy          783386948                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy           17911250                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                   337577                       # number of replacements
system.l2c.tags.tagsinuse                65421.096735                       # Cycle average of tags in use
system.l2c.tags.total_refs                    2486717                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   402739                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     6.174513                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                614754000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   54723.362784                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     2335.935658                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2702.236553                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      571.913553                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      605.884543                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     2280.035703                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     2201.727940                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.835012                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.035644                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.041233                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.008727                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.009245                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.034791                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.033596                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.998247                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1         1013                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         5951                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         2686                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        55344                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 26259828                       # Number of tag accesses
system.l2c.tags.data_accesses                26259828                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst             505337                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             482025                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             122124                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              80194                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst             322880                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data             255461                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1768021                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          835818                       # number of Writeback hits
system.l2c.Writeback_hits::total               835818                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              10                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  14                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data             7                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 7                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            90680                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            25236                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            70985                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               186901                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              505337                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              572705                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              122124                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              105430                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              322880                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              326446                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1954922                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             505337                       # number of overall hits
system.l2c.overall_hits::cpu0.data             572705                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             122124                       # number of overall hits
system.l2c.overall_hits::cpu1.data             105430                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             322880                       # number of overall hits
system.l2c.overall_hits::cpu2.data             326446                       # number of overall hits
system.l2c.overall_hits::total                1954922                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst             7435                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           238426                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             2297                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data            16796                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst             4666                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data            18014                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               287634                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data             9                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            13                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                22                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu2.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          74147                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          18341                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          23352                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             115840                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst              7435                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            312573                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2297                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             35137                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              4666                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             41366                       # number of demand (read+write) misses
system.l2c.demand_misses::total                403474                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst             7435                       # number of overall misses
system.l2c.overall_misses::cpu0.data           312573                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2297                       # number of overall misses
system.l2c.overall_misses::cpu1.data            35137                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             4666                       # number of overall misses
system.l2c.overall_misses::cpu2.data            41366                       # number of overall misses
system.l2c.overall_misses::total               403474                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst    172633500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data   1120486500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst    352018500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data   1205249000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     2850387500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data       166993                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       166993                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu2.data        45998                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total        45998                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1259361990                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   1949459473                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   3208821463                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst    172633500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   2379848490                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    352018500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   3154708473                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      6059208963                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst    172633500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   2379848490                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    352018500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   3154708473                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     6059208963                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         512772                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         720451                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         124421                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          96990                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst         327546                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data         273475                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2055655                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       835818                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           835818                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           12                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data            1                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           23                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              36                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data            9                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             9                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       164827                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        43577                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        94337                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           302741                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          512772                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          885278                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          124421                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          140567                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          327546                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          367812                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2358396                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         512772                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         885278                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         124421                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         140567                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         327546                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         367812                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2358396                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.014500                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.330940                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.018462                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.173172                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.014245                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.065871                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.139923                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.750000                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.565217                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.611111                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu2.data     0.222222                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.222222                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.449847                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.420887                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.247538                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.382637                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.014500                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.353079                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.018462                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.249966                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.014245                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.112465                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.171080                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.014500                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.353079                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.018462                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.249966                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.014245                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.112465                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.171080                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75156.073139                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 66711.508693                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75443.313330                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 66906.239591                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total  9909.772489                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12845.615385                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  7590.590909                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data        22999                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        22999                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68663.758247                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83481.477946                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 27700.461525                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 75156.073139                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 67730.554401                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 75443.313330                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 76263.319465                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 15017.594598                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 75156.073139                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 67730.554401                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 75443.313330                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 76263.319465                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 15017.594598                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               75397                       # number of writebacks
system.l2c.writebacks::total                    75397                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu1.inst         2297                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data        16796                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst         4666                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data        18014                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           41773                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           13                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu2.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        18341                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        23352                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         41693                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2297                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        35137                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         4666                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        41366                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            83466                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2297                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        35137                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         4666                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        41366                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           83466                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    143376000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    910203000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    293289500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data    980286500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   2327155000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       134513                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total       134513                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data        20002                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total        20002                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1028930510                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1664066027                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2692996537                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    143376000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1939133510                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    293289500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   2644352527                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   5020151537                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    143376000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1939133510                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    293289500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   2644352527                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   5020151537                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    234017000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    320664000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total    554681000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    302737500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    395422000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total    698159500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    536754500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data    716086000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   1252840500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.018462                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.173172                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.014245                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.065871                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.020321                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.565217                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.361111                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.222222                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.222222                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.420887                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.247538                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.137718                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.018462                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.249966                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014245                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.112465                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.035391                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.018462                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.249966                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014245                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.112465                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.035391                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62418.807140                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54191.652774                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 62856.729533                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54418.035972                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 55709.549230                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10347.153846                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10347.153846                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56100.022354                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71260.107357                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 64591.095316                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62418.807140                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55187.793779                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 62856.729533                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63925.748852                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 60146.065907                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62418.807140                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55187.793779                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 62856.729533                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63925.748852                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 60146.065907                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                41685                       # number of replacements
system.iocache.tags.tagsinuse                1.254802                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1693889914000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.254802                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.078425                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.078425                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
system.iocache.tags.data_accesses              375525                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
system.iocache.overall_misses::total              173                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide      9417462                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total      9417462                       # number of ReadReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide      9417462                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total      9417462                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide      9417462                       # number of overall miss cycles
system.iocache.overall_miss_latency::total      9417462                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 54436.196532                       # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 54436.196532                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 54436.196532                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 54436.196532                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                      41552                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_misses::tsunami.ide           70                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total           70                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        17280                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        17280                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide           70                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total           70                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide           70                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total           70                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5776462                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total      5776462                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   1039320090                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   1039320090                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide      5776462                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total      5776462                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide      5776462                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total      5776462                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.404624                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide     0.415864                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.415864                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.404624                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.404624                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60145.838542                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60145.838542                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 82520.885714                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 82520.885714                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     4820184                       # DTB read hits
system.cpu0.dtb.read_misses                      5970                       # DTB read misses
system.cpu0.dtb.read_acv                          109                       # DTB read access violations
system.cpu0.dtb.read_accesses                  427969                       # DTB read accesses
system.cpu0.dtb.write_hits                    3428698                       # DTB write hits
system.cpu0.dtb.write_misses                      674                       # DTB write misses
system.cpu0.dtb.write_acv                          81                       # DTB write access violations
system.cpu0.dtb.write_accesses                 164325                       # DTB write accesses
system.cpu0.dtb.data_hits                     8248882                       # DTB hits
system.cpu0.dtb.data_misses                      6644                       # DTB misses
system.cpu0.dtb.data_acv                          190                       # DTB access violations
system.cpu0.dtb.data_accesses                  592294                       # DTB accesses
system.cpu0.itb.fetch_hits                    2727685                       # ITB hits
system.cpu0.itb.fetch_misses                     3015                       # ITB misses
system.cpu0.itb.fetch_acv                          97                       # ITB acv
system.cpu0.itb.fetch_accesses                2730700                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       929885466                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   30965233                       # Number of instructions committed
system.cpu0.committedOps                     30965233                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             28877959                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                164894                       # Number of float alu accesses
system.cpu0.num_func_calls                     798570                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      3871145                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    28877959                       # number of integer instructions
system.cpu0.num_fp_insts                       164894                       # number of float instructions
system.cpu0.num_int_register_reads           39995093                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          21215374                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads               85232                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes              86749                       # number of times the floating registers were written
system.cpu0.num_mem_refs                      8278255                       # number of memory refs
system.cpu0.num_load_insts                    4840998                       # Number of load instructions
system.cpu0.num_store_insts                   3437257                       # Number of store instructions
system.cpu0.num_idle_cycles              908001022.276160                       # Number of idle cycles
system.cpu0.num_busy_cycles              21884443.723840                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.023535                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.976465                       # Percentage of idle cycles
system.cpu0.Branches                          4926958                       # Number of branches fetched
system.cpu0.op_class::No_OpClass              1578460      5.10%      5.10% # Class of executed instruction
system.cpu0.op_class::IntAlu                 20418617     65.93%     71.02% # Class of executed instruction
system.cpu0.op_class::IntMult                   31850      0.10%     71.13% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     71.13% # Class of executed instruction
system.cpu0.op_class::FloatAdd                  12902      0.04%     71.17% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::FloatDiv                   1598      0.01%     71.17% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.17% # Class of executed instruction
system.cpu0.op_class::MemRead                 4971884     16.05%     87.22% # Class of executed instruction
system.cpu0.op_class::MemWrite                3440357     11.11%     98.33% # Class of executed instruction
system.cpu0.op_class::IprAccess                516399      1.67%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  30972067                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6423                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    211353                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   74794     40.97%     40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1878      1.03%     42.11% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                 105680     57.89%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              182555                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    73427     49.30%     49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1878      1.26%     50.70% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   73427     49.30%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               148935                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1818769989500     98.76%     98.76% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               39220500      0.00%     98.76% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              357294000      0.02%     98.78% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            22445011500      1.22%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1841611515500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.981723                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.694805                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.815836                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      2.45%      2.45% # number of syscalls executed
system.cpu0.kern.syscall::3                        30      9.20%     11.66% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.23%     12.88% # number of syscalls executed
system.cpu0.kern.syscall::6                        42     12.88%     25.77% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.31%     26.07% # number of syscalls executed
system.cpu0.kern.syscall::15                        1      0.31%     26.38% # number of syscalls executed
system.cpu0.kern.syscall::17                       15      4.60%     30.98% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      3.07%     34.05% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      1.84%     35.89% # number of syscalls executed
system.cpu0.kern.syscall::23                        4      1.23%     37.12% # number of syscalls executed
system.cpu0.kern.syscall::24                        6      1.84%     38.96% # number of syscalls executed
system.cpu0.kern.syscall::33                       11      3.37%     42.33% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.61%     42.94% # number of syscalls executed
system.cpu0.kern.syscall::45                       54     16.56%     59.51% # number of syscalls executed
system.cpu0.kern.syscall::47                        6      1.84%     61.35% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      3.07%     64.42% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      3.07%     67.48% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.31%     67.79% # number of syscalls executed
system.cpu0.kern.syscall::59                        7      2.15%     69.94% # number of syscalls executed
system.cpu0.kern.syscall::71                       54     16.56%     86.50% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      0.92%     87.42% # number of syscalls executed
system.cpu0.kern.syscall::74                       16      4.91%     92.33% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.31%     92.64% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      0.92%     93.56% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      2.76%     96.32% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.61%     96.93% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.61%     97.55% # number of syscalls executed
system.cpu0.kern.syscall::132                       4      1.23%     98.77% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.61%     99.39% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.61%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   326                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 4174      2.17%      2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi                      54      0.03%      2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.21% # number of callpals executed
system.cpu0.kern.callpal::swpipl               175298     91.20%     93.41% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6782      3.53%     96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     7      0.00%     96.94% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.00%     96.94% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.95% # number of callpals executed
system.cpu0.kern.callpal::rti                    5175      2.69%     99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys                 515      0.27%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     181      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                192209                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             5922                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1737                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle               2093                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1906                      
system.cpu0.kern.mode_good::user                 1737                      
system.cpu0.kern.mode_good::idle                  169                      
system.cpu0.kern.mode_switch_good::kernel     0.321851                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle      0.080745                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.390894                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel       29707694000      1.61%      1.61% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          2577107000      0.14%      1.75% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle        1809326710000     98.25%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    4175                       # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.toL2Bus.throughput                   112481926                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq             825463                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            825443                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq              3528                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp             3528                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           385263                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        17281                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq              24                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             9                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp             33                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           137914                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          137914                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError            5                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       903973                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1415042                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               2319015                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     28925888                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     57212080                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total           86137968                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             204476224                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus         2671872                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         2218881500                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           247500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2036319024                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        2306325269                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.iobus.throughput                       1470003                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq                 2992                       # Transaction distribution
system.iobus.trans_dist::ReadResp                2992                       # Transaction distribution
system.iobus.trans_dist::WriteReq               20808                       # Transaction distribution
system.iobus.trans_dist::WriteResp              20808                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         2342                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          140                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio         7420                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         2926                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf           18                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        12900                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        34700                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        34700                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                   47600                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio         9368                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio          560                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio           55                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         3710                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         2083                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf           16                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total        15792                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      1107376                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      1107376                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              1123168                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 2707176                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              2208000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               105000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy               48000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5525000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             2081000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           155677802                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy             9372000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            17532750                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.cpu0.icache.tags.replacements           964098                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.196429                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           40281211                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           964609                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            41.759108                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      10190294250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   265.809335                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst    64.640468                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst   180.746626                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.519159                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.126251                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.353021                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998431                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         42226967                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        42226967                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     30459275                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      7343645                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      2478291                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       40281211                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     30459275                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      7343645                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      2478291                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        40281211                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     30459275                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      7343645                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      2478291                       # number of overall hits
system.cpu0.icache.overall_hits::total       40281211                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       512792                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       124421                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       343745                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       980958                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       512792                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       124421                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       343745                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        980958                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       512792                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       124421                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       343745                       # number of overall misses
system.cpu0.icache.overall_misses::total       980958                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1775017500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4831640896                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   6606658396                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   1775017500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   4831640896                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   6606658396                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   1775017500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   4831640896                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   6606658396                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     30972067                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      7468066                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      2822036                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     41262169                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     30972067                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      7468066                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      2822036                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     41262169                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     30972067                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      7468066                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      2822036                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     41262169                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016557                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016660                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.121807                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.023774                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016557                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016660                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.121807                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.023774                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016557                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016660                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.121807                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.023774                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14266.221136                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14055.887056                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  6734.904446                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14266.221136                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14055.887056                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  6734.904446                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14266.221136                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14055.887056                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  6734.904446                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         3704                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              169                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    21.917160                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16160                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        16160                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        16160                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        16160                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        16160                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        16160                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       124421                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       327585                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       452006                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       124421                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       327585                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       452006                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       124421                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       327585                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       452006                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1525261500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3997287463                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   5522548963                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1525261500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3997287463                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   5522548963                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1525261500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3997287463                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   5522548963                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016660                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116081                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010954                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016660                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116081                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.010954                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016660                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116081                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.010954                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.875110                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12202.290895                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.866495                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.875110                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12202.290895                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.866495                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.875110                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12202.290895                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.866495                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements          1393139                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.997816                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           13262993                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1393651                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs             9.516725                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   260.896843                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data    74.443174                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data   176.657800                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.509564                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.145397                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.345035                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          267                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         63351520                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        63351520                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      3995753                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      1055109                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      2515938                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        7566800                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3139218                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data       809021                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      1363953                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       5312192                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       114493                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        18830                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        51280                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       184603                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       123317                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data        20808                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data        55196                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       199321                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      7134971                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      1864130                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      3879891                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        12878992                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      7134971                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      1864130                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      3879891                       # number of overall hits
system.cpu0.dcache.overall_hits::total       12878992                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       711080                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data        94884                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       563934                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1369898                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       164839                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        43578                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       629063                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       837480                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9371                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2106                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7687                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        19164                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data            9                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            9                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       875919                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       138462                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data      1192997                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2207378                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       875919                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       138462                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1192997                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2207378                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2196286000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9809622346                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  12005908346                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1651405510                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  20350366997                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  22001772507                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     27755500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    126986999                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    154742499                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       143002                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       143002                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   3847691510                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  30159989343                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  34007680853                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   3847691510                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  30159989343                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  34007680853                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      4706833                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      1149993                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      3079872                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8936698                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      3304057                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data       852599                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      1993016                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      6149672                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       123864                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        20936                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        58967                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       203767                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       123317                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        20808                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        55205                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       199330                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data      8010890                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      2002592                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      5072888                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     15086370                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data      8010890                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      2002592                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      5072888                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     15086370                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.151074                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.082508                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.183103                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.153289                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049890                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.051112                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.315634                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.136183                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.075656                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.100592                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.130361                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.094049                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000163                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000045                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.109341                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.069141                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.235171                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.146316                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.109341                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.069141                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.235171                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.146316                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23147.063783                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17394.983005                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total  8764.089258                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37895.394695                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32350.284466                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 26271.400519                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13179.249763                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16519.708469                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  8074.645116                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 15889.111111                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15889.111111                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27788.790498                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25280.859334                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15406.369391                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27788.790498                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25280.859334                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 15406.369391                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       895030                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         1251                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            63218                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets             11                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.157835                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   113.727273                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       835818                       # number of writebacks
system.cpu0.dcache.writebacks::total           835818                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       296217                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       296217                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       534994                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       534994                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1640                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1640                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       831211                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       831211                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       831211                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       831211                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        94884                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       267717                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       362601                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        43578                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        94069                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       137647                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2106                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         6047                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8153                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            9                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            9                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       138462                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       361786                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       500248                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       138462                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       361786                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       500248                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1998980000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4480743134                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6479723134                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1555929490                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2922490326                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4478419816                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     23542500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     72865001                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     96407501                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       124998                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       124998                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3554909490                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7403233460                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  10958142950                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3554909490                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   7403233460                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  10958142950                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    249968500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    342709000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    592677500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    320834500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    419662000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    740496500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    570803000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    762371000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1333174000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.082508                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086925                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.040574                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.051112                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.047199                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022383                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.100592                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.102549                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.040011                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000163                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000045                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.069141                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.071318                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.033159                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.069141                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.071318                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.033159                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21067.619409                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16736.864428                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17870.119316                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35704.472211                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31067.517737                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32535.542482                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11178.774929                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12049.776914                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11824.788544                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13888.666667                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13888.666667                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25674.260736                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20463.018083                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21905.420811                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25674.260736                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20463.018083                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21905.420811                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1168812                       # DTB read hits
system.cpu1.dtb.read_misses                      1325                       # DTB read misses
system.cpu1.dtb.read_acv                           34                       # DTB read access violations
system.cpu1.dtb.read_accesses                  141647                       # DTB read accesses
system.cpu1.dtb.write_hits                     873733                       # DTB write hits
system.cpu1.dtb.write_misses                      170                       # DTB write misses
system.cpu1.dtb.write_acv                          22                       # DTB write access violations
system.cpu1.dtb.write_accesses                  57095                       # DTB write accesses
system.cpu1.dtb.data_hits                     2042545                       # DTB hits
system.cpu1.dtb.data_misses                      1495                       # DTB misses
system.cpu1.dtb.data_acv                           56                       # DTB access violations
system.cpu1.dtb.data_accesses                  198742                       # DTB accesses
system.cpu1.itb.fetch_hits                     849434                       # ITB hits
system.cpu1.itb.fetch_misses                      664                       # ITB misses
system.cpu1.itb.fetch_acv                          34                       # ITB acv
system.cpu1.itb.fetch_accesses                 850098                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                       953402608                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                    7466514                       # Number of instructions committed
system.cpu1.committedOps                      7466514                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses              6940405                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                 43972                       # Number of float alu accesses
system.cpu1.num_func_calls                     203873                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts       905018                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                     6940405                       # number of integer instructions
system.cpu1.num_fp_insts                        43972                       # number of float instructions
system.cpu1.num_int_register_reads            9656232                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           5062933                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads               23750                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              24129                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      2049510                       # number of memory refs
system.cpu1.num_load_insts                    1173515                       # Number of load instructions
system.cpu1.num_store_insts                    875995                       # Number of store instructions
system.cpu1.num_idle_cycles              923975227.132686                       # Number of idle cycles
system.cpu1.num_busy_cycles              29427380.867314                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.030866                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.969134                       # Percentage of idle cycles
system.cpu1.Branches                          1173577                       # Number of branches fetched
system.cpu1.op_class::No_OpClass               399506      5.35%      5.35% # Class of executed instruction
system.cpu1.op_class::IntAlu                  4845173     64.88%     70.23% # Class of executed instruction
system.cpu1.op_class::IntMult                    8216      0.11%     70.34% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     70.34% # Class of executed instruction
system.cpu1.op_class::FloatAdd                   5112      0.07%     70.41% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     70.41% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     70.41% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     70.41% # Class of executed instruction
system.cpu1.op_class::FloatDiv                    810      0.01%     70.42% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     70.42% # Class of executed instruction
system.cpu1.op_class::MemRead                 1201694     16.09%     86.51% # Class of executed instruction
system.cpu1.op_class::MemWrite                 877208     11.75%     98.25% # Class of executed instruction
system.cpu1.op_class::IprAccess                130346      1.75%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                   7468065                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                         0                       # number of hwrei instructions executed
system.cpu1.kern.mode_switch::kernel                0                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                  0                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                  0                      
system.cpu1.kern.mode_good::user                    0                      
system.cpu1.kern.mode_good::idle                    0                      
system.cpu1.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
system.cpu2.branchPred.lookups                9007020                       # Number of BP lookups
system.cpu2.branchPred.condPredicted          8266685                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           125563                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups             6913379                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                4889018                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            70.718212                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 301119                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect              7670                       # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits                          0                       # ITB hits
system.cpu2.dtb.fetch_misses                        0                       # ITB misses
system.cpu2.dtb.fetch_acv                           0                       # ITB acv
system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu2.dtb.read_hits                     3485225                       # DTB read hits
system.cpu2.dtb.read_misses                     12620                       # DTB read misses
system.cpu2.dtb.read_acv                          152                       # DTB read access violations
system.cpu2.dtb.read_accesses                  227645                       # DTB read accesses
system.cpu2.dtb.write_hits                    2140940                       # DTB write hits
system.cpu2.dtb.write_misses                     2817                       # DTB write misses
system.cpu2.dtb.write_acv                         139                       # DTB write access violations
system.cpu2.dtb.write_accesses                  85106                       # DTB write accesses
system.cpu2.dtb.data_hits                     5626165                       # DTB hits
system.cpu2.dtb.data_misses                     15437                       # DTB misses
system.cpu2.dtb.data_acv                          291                       # DTB access violations
system.cpu2.dtb.data_accesses                  312751                       # DTB accesses
system.cpu2.itb.fetch_hits                     539657                       # ITB hits
system.cpu2.itb.fetch_misses                     5944                       # ITB misses
system.cpu2.itb.fetch_acv                         165                       # ITB acv
system.cpu2.itb.fetch_accesses                 545601                       # ITB accesses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.read_acv                            0                       # DTB read access violations
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.write_acv                           0                       # DTB write access violations
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.data_hits                           0                       # DTB hits
system.cpu2.itb.data_misses                         0                       # DTB misses
system.cpu2.itb.data_acv                            0                       # DTB access violations
system.cpu2.itb.data_accesses                       0                       # DTB accesses
system.cpu2.numCycles                        29515720                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles           9404916                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                      35474807                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                    9007020                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches           5190137                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                     18003717                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                 410566                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                       517                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles                9775                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles             1999                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles       235781                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles        98995                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          442                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  2822037                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                92550                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples          27961187                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.268716                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.388099                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                20241670     72.39%     72.39% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  312691      1.12%     73.51% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                  474251      1.70%     75.21% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                 3278987     11.73%     86.93% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  837934      3.00%     89.93% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  194435      0.70%     90.63% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  239683      0.86%     91.48% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  437644      1.57%     93.05% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                 1943892      6.95%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total            27961187                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.305160                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.201895                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                 7704419                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             13193149                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                  6090024                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles               535254                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                192290                       # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved              176132                       # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred                13346                       # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts              32094888                       # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts                42715                       # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles                192290                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                 7987526                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                4830275                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles       6354829                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                  6312082                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles              2038145                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts              31271508                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents                68877                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents                405466                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                 55957                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents                963204                       # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands           20931686                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups             38638449                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups        38578281                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups            56251                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps             19026086                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                 1905600                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            533120                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts         63723                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                  3942739                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             3510198                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            2234995                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           462280                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          329256                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                  28739879                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             680947                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                 28391596                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued            17529                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        2438506                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined      1151582                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved        487021                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples     27961187                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.015393                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.594251                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           17574861     62.85%     62.85% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            2788082      9.97%     72.83% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            1379347      4.93%     77.76% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            4037262     14.44%     92.20% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4            1018579      3.64%     95.84% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5             572705      2.05%     97.89% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6             385941      1.38%     99.27% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             155733      0.56%     99.83% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8              48677      0.17%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total       27961187                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                  82533     21.35%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     21.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                178965     46.29%     67.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite               125088     32.36%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass             2456      0.01%      0.01% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu             22261960     78.41%     78.42% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               21111      0.07%     78.49% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     78.49% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd              20516      0.07%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv               1228      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     78.57% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead             3614417     12.73%     91.30% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            2165470      7.63%     98.93% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess            304438      1.07%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total              28391596                       # Type of FU issued
system.cpu2.iq.rate                          0.961914                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                     386586                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.013616                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads          84894790                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes         31745632                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses     27810644                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads             253704                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes            119619                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses       117118                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses              28639647                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                 136079                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          206810                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads       438537                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         1486                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         6057                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       183313                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads         5003                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked       177760                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                192290                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                4010862                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles               349296                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts           30806306                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            54542                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              3510198                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             2234995                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            606167                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                 15566                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents               285460                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          6057                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect         62858                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       135105                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              197963                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts             28193561                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts              3506622                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           198035                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                      1385480                       # number of nop insts executed
system.cpu2.iew.exec_refs                     5655108                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                 5954900                       # Number of branches executed
system.cpu2.iew.exec_stores                   2148486                       # Number of stores executed
system.cpu2.iew.exec_rate                    0.955205                       # Inst execution rate
system.cpu2.iew.wb_sent                      27969918                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                     27927762                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                 15888662                       # num instructions producing a value
system.cpu2.iew.wb_consumers                 19538696                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      0.946200                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.813189                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        2672008                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         193926                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           180997                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples     27494343                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.021637                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.858517                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     18377188     66.84%     66.84% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      2251123      8.19%     75.03% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1180007      4.29%     79.32% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3      3743706     13.62%     92.94% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       543464      1.98%     94.91% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       201872      0.73%     95.65% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       166281      0.60%     96.25% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7       179533      0.65%     96.90% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8       851169      3.10%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total     27494343                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts            28089240                       # Number of instructions committed
system.cpu2.commit.committedOps              28089240                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       5123343                       # Number of memory references committed
system.cpu2.commit.loads                      3071661                       # Number of loads committed
system.cpu2.commit.membars                      68272                       # Number of memory barriers committed
system.cpu2.commit.branches                   5784239                       # Number of branches committed
system.cpu2.commit.fp_insts                    115390                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                 26574373                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              240380                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass      1220895      4.35%      4.35% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu        21328709     75.93%     80.28% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult          20651      0.07%     80.35% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv               0      0.00%     80.35% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd         20067      0.07%     80.42% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     80.42% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     80.42% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     80.42% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv          1228      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     80.43% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead        3139933     11.18%     91.61% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite       2053319      7.31%     98.92% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess       304438      1.08%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total         28089240                       # Class of committed instruction
system.cpu2.commit.bw_lim_events               851169                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                    57327258                       # The number of ROB reads
system.cpu2.rob.rob_writes                   61989353                       # The number of ROB writes
system.cpu2.timesIdled                         175568                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                        1554533                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  1746289037                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                   26870801                       # Number of Instructions Simulated
system.cpu2.committedOps                     26870801                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              1.098431                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        1.098431                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.910389                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.910389                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                36957190                       # number of integer regfile reads
system.cpu2.int_regfile_writes               19824047                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    70953                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   70972                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                3637810                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                273227                       # number of misc regfile writes
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei                         0                       # number of hwrei instructions executed
system.cpu2.kern.mode_switch::kernel                0                       # number of protection mode switches
system.cpu2.kern.mode_switch::user                  0                       # number of protection mode switches
system.cpu2.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu2.kern.mode_good::kernel                  0                      
system.cpu2.kern.mode_good::user                    0                      
system.cpu2.kern.mode_good::idle                    0                      
system.cpu2.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
system.cpu2.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
system.cpu2.kern.swap_context                       0                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------