path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.843718                       # Number of seconds simulated
sim_ticks                                2843718094000                       # Number of ticks simulated
final_tick                               2843718094000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 161241                       # Simulator instruction rate (inst/s)
host_op_rate                                   195251                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3650642703                       # Simulator tick rate (ticks/s)
host_mem_usage                                 606904                       # Number of bytes of host memory used
host_seconds                                   778.96                       # Real time elapsed on the host
sim_insts                                   125601128                       # Number of instructions simulated
sim_ops                                     152093417                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker        10240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1341052                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     10709120                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           541088                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher      1237760                       # Number of bytes read from this memory
system.physmem.bytes_read::total             13841180                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       411264                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        31936                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          443200                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7176832                       # Number of bytes written to this memory
system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.inst         17704                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.inst            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9512912                       # Number of bytes written to this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker          160                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             21479                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       167330                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           14                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              8478                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher        19340                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                216817                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          112138                       # Number of write requests responded to by this memory
system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.inst             4426                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.inst               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               152798                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.ide              338                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker          3601                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              471584                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      3765887                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           315                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              190275                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       435261                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4867283                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         144622                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          11230                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             155852                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2523749                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::realview.ide          815248                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.inst               6226                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.inst                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3345237                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2523749                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide          815586                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3601                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             477810                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      3765887                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          315                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             190289                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       435261                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                8212520                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        216817                       # Number of read requests accepted
system.physmem.writeReqs                       152798                       # Number of write requests accepted
system.physmem.readBursts                      216817                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     152798                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 13860672                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     15616                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9527424                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  13841180                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                9512912                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      244                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3916                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          13461                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               14081                       # Per bank write bursts
system.physmem.perBankRdBursts::1               13907                       # Per bank write bursts
system.physmem.perBankRdBursts::2               14464                       # Per bank write bursts
system.physmem.perBankRdBursts::3               13988                       # Per bank write bursts
system.physmem.perBankRdBursts::4               16210                       # Per bank write bursts
system.physmem.perBankRdBursts::5               13087                       # Per bank write bursts
system.physmem.perBankRdBursts::6               13697                       # Per bank write bursts
system.physmem.perBankRdBursts::7               13930                       # Per bank write bursts
system.physmem.perBankRdBursts::8               13098                       # Per bank write bursts
system.physmem.perBankRdBursts::9               13410                       # Per bank write bursts
system.physmem.perBankRdBursts::10              13015                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11706                       # Per bank write bursts
system.physmem.perBankRdBursts::12              12947                       # Per bank write bursts
system.physmem.perBankRdBursts::13              13659                       # Per bank write bursts
system.physmem.perBankRdBursts::14              12722                       # Per bank write bursts
system.physmem.perBankRdBursts::15              12652                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9756                       # Per bank write bursts
system.physmem.perBankWrBursts::1               10039                       # Per bank write bursts
system.physmem.perBankWrBursts::2               10215                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9785                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9214                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9161                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9492                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9434                       # Per bank write bursts
system.physmem.perBankWrBursts::8                9026                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9356                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9095                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8550                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9129                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9225                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8893                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8496                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
system.physmem.totGap                    2843715756500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     559                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  216230                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4436                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 148362                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     79662                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     62454                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     17878                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     12202                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     10651                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      9329                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      8314                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      7470                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      6044                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1174                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      438                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      316                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      218                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      169                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      140                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      109                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2965                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3559                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4302                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5372                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6291                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     7531                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     8122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     8991                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     9788                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    10919                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    10684                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10534                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    10395                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    10863                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9042                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8791                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8805                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     8230                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      564                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      399                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      299                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      157                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       75                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       74                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        92355                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      253.241254                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     143.538036                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     308.020470                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          46699     50.56%     50.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18860     20.42%     70.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6817      7.38%     78.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3583      3.88%     82.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3053      3.31%     85.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2112      2.29%     87.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1277      1.38%     89.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1140      1.23%     90.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8814      9.54%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          92355                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7471                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.988355                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      530.902810                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7470     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7471                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7471                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.925847                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.607688                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       10.837629                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            6200     82.99%     82.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             464      6.21%     89.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              76      1.02%     90.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             210      2.81%     93.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             192      2.57%     95.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              15      0.20%     95.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              27      0.36%     96.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              15      0.20%     96.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              29      0.39%     96.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              10      0.13%     96.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               9      0.12%     97.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               6      0.08%     97.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             163      2.18%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               4      0.05%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               5      0.07%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               4      0.05%     99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              14      0.19%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.01%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.03%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.03%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             4      0.05%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.01%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             3      0.04%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.03%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.03%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             2      0.03%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             8      0.11%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7471                       # Writes before turning the bus around for reads
system.physmem.totQLat                     7621074500                       # Total ticks spent queuing
system.physmem.totMemAccLat               11681818250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1082865000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       35189.40                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  53939.40                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.87                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.35                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.87                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.35                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.99                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.13                       # Average write queue length when enqueuing
system.physmem.readRowHits                     183248                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     89836                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   84.61                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  60.34                       # Row buffer hit rate for writes
system.physmem.avgGap                      7693723.89                       # Average gap between requests
system.physmem.pageHitRate                      74.72                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2710028687250                       # Time in different power states
system.physmem.memoryStateTime::REF       94957980000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       38731176500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 365654520                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 332549280                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 199513875                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 181450500                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0                884239200                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1                805030200                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               499582080                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               465069600                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          185737808880                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          185737808880                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0           82126203345                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1           81336736530                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          1634190168750                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          1634882683500                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            1904003170650                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            1903741328490                       # Total energy per rank (pJ)
system.physmem.averagePower::0             669.547151                       # Core power per rank (mW)
system.physmem.averagePower::1             669.455073                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1280                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1280                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             20                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          180                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          270                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              450                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          180                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          270                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          450                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          180                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          270                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             450                       # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq              238282                       # Transaction distribution
system.membus.trans_dist::ReadResp             238282                       # Transaction distribution
system.membus.trans_dist::WriteReq              31054                       # Transaction distribution
system.membus.trans_dist::WriteResp             31054                       # Transaction distribution
system.membus.trans_dist::Writeback            112138                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            80328                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40430                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           13461                       # Transaction distribution
system.membus.trans_dist::ReadExReq             30145                       # Transaction distribution
system.membus.trans_dist::ReadExResp            13182                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107970                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           40                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14040                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       705796                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       827846                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72718                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72718                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 900564                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162850                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1280                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28080                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     21034796                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     21227006                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                23546302                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           124500                       # Total snoops (count)
system.membus.snoop_fanout::samples            499399                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  499399    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              499399                       # Request fanout histogram
system.membus.reqLayer0.occupancy            87896996                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               23828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            12141500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1620346498                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2120331885                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer3.occupancy           38636884                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                   151104                       # number of replacements
system.l2c.tags.tagsinuse                64343.342453                       # Cycle average of tags in use
system.l2c.tags.total_refs                     537709                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   215892                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.490639                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   13312.566907                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    81.661228                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.033237                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3627.484276                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 40388.691608                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    10.364745                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      878.502916                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  6044.037536                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.203134                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001246                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.055351                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.616283                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000158                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.013405                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.092225                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.981801                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        46495                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           34                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        18259                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          432                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         6889                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        39173                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           34                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          282                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         2341                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        15618                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.709457                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000519                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.278610                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6702696                       # Number of tag accesses
system.l2c.tags.data_accesses                 6702696                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker          575                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker          122                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst              36632                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       209337                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker          139                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker           45                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst              12148                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher        48809                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 307807                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          253703                       # number of Writeback hits
system.l2c.Writeback_hits::total               253703                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.inst           11935                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.inst            1029                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               12964                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.inst           208                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.inst           174                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               382                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.inst             3683                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.inst             1200                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 4883                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker           575                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker           122                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               40315                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       209337                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker           139                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            45                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               13348                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher        48809                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  312690                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          575                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker          122                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              40315                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       209337                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker          139                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           45                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              13348                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher        48809                       # number of overall hits
system.l2c.overall_hits::total                 312690                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker          160                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            11021                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       167331                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           14                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             2011                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher        19340                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               199878                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.inst          8877                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.inst          2752                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11629                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.inst          464                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.inst         1248                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1712                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.inst           6943                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.inst           6359                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              13302                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker          160                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             17964                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       167331                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           14                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              8370                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher        19340                       # number of demand (read+write) misses
system.l2c.demand_misses::total                213180                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker          160                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            17964                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       167331                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           14                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             8370                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher        19340                       # number of overall misses
system.l2c.overall_misses::total               213180                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker     13245499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        75000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    927632991                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  17938370695                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1117750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    171510999                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher   2176490172                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    21228443106                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.inst     10247078                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.inst      3439358                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     13686436                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.inst      1071455                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.inst      1047955                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      2119410                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.inst    585218901                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.inst    465754979                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1050973880                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker     13245499                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        75000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1512851892                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  17938370695                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1117750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    637265978                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   2176490172                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     22279416986                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker     13245499                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        75000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1512851892                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  17938370695                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1117750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    637265978                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   2176490172                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    22279416986                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker          735                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker          123                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst          47653                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       376668                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker          153                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker           45                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst          14159                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher        68149                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             507685                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       253703                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           253703                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.inst        20812                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.inst         3781                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           24593                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.inst          672                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.inst         1422                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2094                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.inst        10626                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.inst         7559                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            18185                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          735                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker          123                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           58279                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       376668                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker          153                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           45                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           21718                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        68149                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              525870                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          735                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker          123                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          58279                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       376668                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker          153                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           45                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          21718                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        68149                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             525870                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.217687                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.008130                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.231276                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.444240                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.091503                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.142030                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.283790                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.393705                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.inst     0.426533                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.inst     0.727850                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.472858                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.inst     0.690476                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.inst     0.877637                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.817574                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.inst     0.653397                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.inst     0.841249                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.731482                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.217687                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.008130                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.308241                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.444240                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.091503                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.385395                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.283790                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.405385                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.217687                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.008130                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.308241                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.444240                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.091503                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.385395                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.283790                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.405385                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 82784.368750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        75000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84169.584520                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107202.913357                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79839.285714                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85286.424167                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 112538.271562                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 106207.001801                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst  1154.340205                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst  1249.766715                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1176.922865                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst  2309.170259                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst   839.707532                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1237.973131                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84289.053867                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 73243.431200                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 79008.711472                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 82784.368750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 84215.758851                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107202.913357                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79839.285714                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 76136.914934                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112538.271562                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 104509.883601                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 82784.368750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 84215.758851                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107202.913357                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79839.285714                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 76136.914934                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112538.271562                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 104509.883601                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                27                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        2                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     13.500000                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              112138                       # number of writebacks
system.l2c.writebacks::total                   112138                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 2                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  2                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 2                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker          160                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        11020                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       167330                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           14                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         2011                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher        19340                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          199876                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.inst         8877                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.inst         2752                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        11629                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst          464                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst         1248                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1712                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.inst         6943                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.inst         6359                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         13302                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker          160                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        17963                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       167330                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         8370                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher        19340                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           213178                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker          160                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        17963                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       167330                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         8370                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher        19340                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          213178                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker     11265999                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    790589241                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  15877737945                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       946250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    146552499                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1940375672                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  18767530106                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst     89623803                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst     27822731                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    117446534                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst      4677961                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst     12575743                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     17253704                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst    498567599                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst    385443021                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total    884010620                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     11265999                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1289156840                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  15877737945                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       946250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    531995520                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   1940375672                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  19651540726                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     11265999                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1289156840                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  15877737945                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       946250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    531995520                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1940375672                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  19651540726                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   5455196250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    328328000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5783524250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst   4031988000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst    216852500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4248840500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   9487184250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    545180500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10032364750                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.217687                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.008130                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.231255                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.444237                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.091503                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.142030                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.283790                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.393701                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst     0.426533                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.727850                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.472858                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.690476                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.877637                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.817574                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst     0.653397                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.841249                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.731482                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.217687                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.008130                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.308224                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.444237                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.091503                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.385395                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.283790                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.405382                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.217687                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.008130                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.308224                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.444237                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.091503                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.385395                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.283790                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.405382                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71741.310436                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72875.434610                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 93895.865967                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10096.181480                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10110.003997                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10099.452575                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10081.812500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10076.717147                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.098131                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 71808.670459                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60613.779053                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 66456.970380                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71767.346212                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63559.799283                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 92183.718423                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71767.346212                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63559.799283                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 92183.718423                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq             675950                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            675935                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             31054                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            31054                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           253703                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        36227                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           93172                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         40812                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         133984                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           10                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           10                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            39254                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           39254                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1372089                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       383613                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1755702                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     42006746                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8315748                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               50322494                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          294957                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          1100978                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.033136                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.178992                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                1064496     96.69%     96.69% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  36482      3.31%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            1100978                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         1599263913                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1080000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2370465695                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         831346703                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31024                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31024                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59407                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59440                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateReq           33                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56656                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107970                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180928                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71600                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162850                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484122                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40136000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           326680325                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84754000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36847116                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.cpu0.branchPred.lookups               34854856                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         17109626                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          1616877                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            20006820                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               14503231                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            72.491435                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               10748202                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            771222                       # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    23968692                       # DTB read hits
system.cpu0.dtb.read_misses                     61651                       # DTB read misses
system.cpu0.dtb.write_hits                   17871018                       # DTB write hits
system.cpu0.dtb.write_misses                     6619                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3502                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1211                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1921                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      566                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                24030343                       # DTB read accesses
system.cpu0.dtb.write_accesses               17877637                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         41839710                       # DTB hits
system.cpu0.dtb.misses                          68270                       # DTB misses
system.cpu0.dtb.accesses                     41907980                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                    70097291                       # ITB inst hits
system.cpu0.itb.inst_misses                      3844                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2220                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     7362                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                70101135                       # ITB inst accesses
system.cpu0.itb.hits                         70097291                       # DTB hits
system.cpu0.itb.misses                           3844                       # DTB misses
system.cpu0.itb.accesses                     70101135                       # DTB accesses
system.cpu0.numCycles                       227722348                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  109201964                       # Number of instructions committed
system.cpu0.committedOps                    132004483                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                      8817575                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     1858                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                  5459726684                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.085332                       # CPI: cycles per instruction
system.cpu0.ipc                              0.479540                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1864                       # number of quiesce instructions executed
system.cpu0.tickCycles                      192189087                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                       35533261                       # Total number of cycles that the object has spent stopped
system.cpu0.icache.tags.replacements          1960423                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.796865                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           68128653                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1960935                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            34.742943                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6227191000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.796865                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999603                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999603                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          184                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          231                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           97                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        142140155                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       142140155                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     68128653                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       68128653                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     68128653                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        68128653                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     68128653                       # number of overall hits
system.cpu0.icache.overall_hits::total       68128653                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1960950                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1960950                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1960950                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1960950                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1960950                       # number of overall misses
system.cpu0.icache.overall_misses::total      1960950                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  16347715808                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  16347715808                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  16347715808                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  16347715808                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  16347715808                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  16347715808                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     70089603                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     70089603                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     70089603                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     70089603                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     70089603                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     70089603                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.027978                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.027978                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.027978                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.027978                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.027978                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.027978                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8336.630617                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8336.630617                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8336.630617                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8336.630617                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8336.630617                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8336.630617                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1960950                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1960950                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1960950                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1960950                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1960950                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1960950                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  13404270692                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  13404270692                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  13404270692                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  13404270692                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  13404270692                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  13404270692                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    276968500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    276968500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    276968500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    276968500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027978                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027978                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027978                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.027978                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027978                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.027978                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  6835.600445                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  6835.600445                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  6835.600445                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  6835.600445                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  6835.600445                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  6835.600445                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq       2745512                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      2644445                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28520                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28520                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       513053                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       701523                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36227                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        70947                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43092                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp        94006                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            7                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           10                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       290299                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       280446                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3928023                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2381529                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11804                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       166842                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          6488198                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    125696704                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     86351322                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17688                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       313268                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         212378982                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    1094951                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      4365889                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       5.223377                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.416509                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5           3390648     77.66%     77.66% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6            975241     22.34%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       4365889                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    2254798560                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    118870000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   2947700808                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1230574902                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      7385992                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     88548223                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     17144913                       # number of hwpf identified
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       425558                       # number of hwpf that were already in mshr
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     16187872                       # number of hwpf that were already in the cache
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         8427                       # number of hwpf that were already in the prefetch queue
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         6267                       # number of hwpf removed because MSHR allocated
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       516786                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page      1326511                       # number of hwpf spanning a virtual page
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l2cache.tags.replacements          410501                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16214.104593                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           2982888                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          426752                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            6.989746                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle    2824483316500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  4342.913069                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    47.461328                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.076713                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  2208.018647                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  9615.634836                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.265070                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002897                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000005                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.134767                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.586892                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.989630                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8959                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            9                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024         7283                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           66                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          107                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         2957                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         5162                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          667                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          268                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3107                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         3633                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          224                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.546814                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000549                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.444519                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        54811525                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       54811525                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        77296                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4241                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      2365837                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       2447374                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       513053                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       513053                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst         4545                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total         4545                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst         2277                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         2277                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.inst       221177                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       221177                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        77296                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4241                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      2587014                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        2668551                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        77296                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4241                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      2587014                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       2668551                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker         1021                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          181                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst        94620                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        95822                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst        28011                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        28011                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst        18233                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        18233                       # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.inst        46900                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        46900                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker         1021                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          181                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       141520                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       142722                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker         1021                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          181                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       141520                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       142722                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     34165499                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      4027498                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   2870753873                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   2908946870                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst    500227988                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    500227988                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst    361106760                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    361106760                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst        90500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total        90500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst   1915708255                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   1915708255                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     34165499                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      4027498                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4786462128                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   4824655125                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     34165499                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      4027498                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4786462128                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   4824655125                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        78317                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4422                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      2460457                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total      2543196                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       513053                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       513053                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst        32556                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        32556                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst        20510                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        20510                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst       268077                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       268077                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        78317                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4422                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      2728534                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2811273                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        78317                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4422                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      2728534                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2811273                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.013037                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.040932                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.038456                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.037678                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst     0.860394                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.860394                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst     0.888981                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.888981                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst     0.174950                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.174950                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.013037                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.040932                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.051867                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.050768                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.013037                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.040932                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.051867                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.050768                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33462.780607                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22251.370166                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30339.821105                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30357.818351                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17858.269537                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17858.269537                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19805.120386                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19805.120386                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst          inf                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 40846.657889                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 40846.657889                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33462.780607                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22251.370166                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33821.807010                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 33804.564993                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33462.780607                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22251.370166                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33821.807010                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 33804.564993                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs        27297                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs             390                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    69.992308                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       214261                       # number of writebacks
system.cpu0.l2cache.writebacks::total          214261                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst         7719                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total         7719                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst         3119                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         3119                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst        10838                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        10838                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst        10838                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        10838                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker         1021                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          181                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        86901                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        88103                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       516784                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       516784                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst        28011                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        28011                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst        18233                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18233                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst        43781                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        43781                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker         1021                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          181                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       130682                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       131884                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker         1021                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          181                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       130682                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       516784                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       648668                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     26999003                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2760498                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   2099218995                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   2128978496                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21179021871                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21179021871                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst    474290503                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    474290503                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst    241043533                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    241043533                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst        69500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total        69500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst   1189749710                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1189749710                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     26999003                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2760498                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3288968705                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   3318728206                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     26999003                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2760498                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3288968705                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21179021871                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  24497750077                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6107809749                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6107809749                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst   4518638513                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4518638513                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst  10626448262                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10626448262                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.013037                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.040932                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.035319                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.034643                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst     0.860394                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.860394                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.888981                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.888981                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst     0.163315                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.163315                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.013037                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.040932                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.047895                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.046913                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.013037                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.040932                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.047895                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.230738                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26443.685602                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15251.370166                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24156.442331                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24164.653826                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40982.348275                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40982.348275                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16932.294563                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16932.294563                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13220.179510                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13220.179510                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27175.023640                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27175.023640                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26443.685602                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15251.370166                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25167.725509                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25163.994162                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26443.685602                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15251.370166                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25167.725509                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40982.348275                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37766.238009                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           712097                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          497.191982                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           40404438                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           712609                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            56.699309                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        306793500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.inst   497.191982                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.971078                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.971078                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          129                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          343                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           40                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         83631959                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        83631959                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.inst     22807107                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       22807107                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.inst     16791710                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      16791710                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst       380026                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       380026                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.inst       361110                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       361110                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.inst     39598817                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        39598817                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.inst     39598817                       # number of overall hits
system.cpu0.dcache.overall_hits::total       39598817                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.inst       535335                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       535335                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.inst       529873                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       529873                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst         6515                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         6515                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.inst        20510                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        20510                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.inst      1065208                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1065208                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.inst      1065208                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1065208                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst   6583386279                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   6583386279                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst   7974270273                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   7974270273                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst    107544752                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    107544752                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst    444281550                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    444281550                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst        99500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total        99500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.inst  14557656552                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  14557656552                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.inst  14557656552                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  14557656552                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.inst     23342442                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     23342442                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.inst     17321583                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     17321583                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst       386541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       386541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst       381620                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       381620                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.inst     40664025                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     40664025                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.inst     40664025                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     40664025                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.022934                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.022934                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.030590                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.030590                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.016855                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.016855                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.053745                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053745                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.026195                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.026195                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.026195                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.026195                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12297.694488                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12297.694488                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15049.399145                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15049.399145                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16507.252801                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16507.252801                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21661.704047                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21661.704047                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13666.491945                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13666.491945                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13666.491945                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13666.491945                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       513055                       # number of writebacks
system.cpu0.dcache.writebacks::total           513055                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst        42339                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        42339                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       229244                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       229244                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.inst       271583                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       271583                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.inst       271583                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       271583                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst       492996                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       492996                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst       300629                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       300629                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst         6515                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6515                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst        20510                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        20510                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.inst       793625                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       793625                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.inst       793625                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       793625                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst   5093716162                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5093716162                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst   4246170249                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4246170249                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst     94499248                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     94499248                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst    402814450                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    402814450                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst        93500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total        93500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst   9339886411                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   9339886411                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst   9339886411                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   9339886411                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6120470998                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6120470998                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   4732689487                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4732689487                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst  10853160485                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10853160485                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.021120                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.021120                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.017356                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017356                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.016855                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016855                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.053745                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053745                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.019517                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.019517                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.019517                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.019517                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10332.165295                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10332.165295                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14124.286908                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14124.286908                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14504.873062                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14504.873062                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19639.904924                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19639.904924                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11768.639359                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11768.639359                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11768.639359                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11768.639359                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                4191050                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          2447557                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           261619                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             2683528                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                1692147                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            63.056804                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 827495                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             59633                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     4177995                       # DTB read hits
system.cpu1.dtb.read_misses                     21525                       # DTB read misses
system.cpu1.dtb.write_hits                    3468676                       # DTB write hits
system.cpu1.dtb.write_misses                     1889                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2064                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      236                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   360                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      285                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 4199520                       # DTB read accesses
system.cpu1.dtb.write_accesses                3470565                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          7646671                       # DTB hits
system.cpu1.dtb.misses                          23414                       # DTB misses
system.cpu1.dtb.accesses                      7670085                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                     7954981                       # ITB inst hits
system.cpu1.itb.inst_misses                      2237                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1156                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1936                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 7957218                       # ITB inst accesses
system.cpu1.itb.hits                          7954981                       # DTB hits
system.cpu1.itb.misses                           2237                       # DTB misses
system.cpu1.itb.accesses                      7957218                       # DTB accesses
system.cpu1.numCycles                        42108230                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   16399164                       # Number of instructions committed
system.cpu1.committedOps                     20088934                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                      1607897                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     2744                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                  5644728223                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.567706                       # CPI: cycles per instruction
system.cpu1.ipc                              0.389453                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2745                       # number of quiesce instructions executed
system.cpu1.tickCycles                       30601119                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                       11507111                       # Total number of cycles that the object has spent stopped
system.cpu1.icache.tags.replacements           921368                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.459165                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            7030999                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           921880                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs             7.626805                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      71222254500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.459165                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975506                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975506                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          466                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           46                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         16827638                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        16827638                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      7030999                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        7030999                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      7030999                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         7030999                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      7030999                       # number of overall hits
system.cpu1.icache.overall_hits::total        7030999                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       921880                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       921880                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       921880                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        921880                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       921880                       # number of overall misses
system.cpu1.icache.overall_misses::total       921880                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7511609427                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   7511609427                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   7511609427                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   7511609427                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   7511609427                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   7511609427                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      7952879                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      7952879                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      7952879                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      7952879                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      7952879                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      7952879                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.115918                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.115918                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.115918                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.115918                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.115918                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.115918                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8148.142304                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8148.142304                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8148.142304                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8148.142304                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8148.142304                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8148.142304                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       921880                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       921880                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       921880                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       921880                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       921880                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       921880                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   6126335573                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   6126335573                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   6126335573                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   6126335573                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   6126335573                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   6126335573                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10451250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10451250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10451250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     10451250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.115918                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.115918                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.115918                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.115918                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.115918                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.115918                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6645.480510                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6645.480510                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6645.480510                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  6645.480510                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6645.480510                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  6645.480510                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq       1617912                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      1172300                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         2534                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2534                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       119069                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       160310                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36227                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        84990                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41555                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        86189                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           10                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        79780                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        67226                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1843990                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       788213                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6991                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        54848                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2694042                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     59007680                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25579748                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        10764                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       100400                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          84698592                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     851885                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      2136582                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       5.360548                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.480160                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5           1366242     63.95%     63.95% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6            770340     36.05%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       2136582                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy     806533923                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     80269000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   1384243177                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    391135835                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      4300499                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     29750249                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      7297386                       # number of hwpf identified
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr        43768                       # number of hwpf that were already in mshr
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      7137149                       # number of hwpf that were already in the cache
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         1402                       # number of hwpf that were already in the prefetch queue
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         2677                       # number of hwpf removed because MSHR allocated
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued       112390                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       731398                       # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l2cache.tags.replacements           85101                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15525.587179                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1172424                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs          100275                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           11.692087                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  5967.757550                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    26.503310                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.105046                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2342.307731                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  7188.913541                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.364243                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001618                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000006                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.142963                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.438776                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.947607                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022        10134                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           34                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024         5006                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          136                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         6712                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         3286                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           11                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           18                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          243                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2980                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1783                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.618530                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002075                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.305542                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        22015192                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       22015192                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        24492                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2447                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst      1023306                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total       1050245                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       119069                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       119069                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst         1895                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         1895                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst          736                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total          736                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.inst        30109                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        30109                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        24492                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2447                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      1053415                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        1080354                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        24492                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2447                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      1053415                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       1080354                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          608                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          244                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst        73509                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        74361                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst        28314                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        28314                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst        22589                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22589                       # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.inst        32639                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        32639                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          608                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          244                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       106148                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       107000                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          608                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          244                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       106148                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       107000                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     13309748                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4879000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst   1671503870                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   1689692618                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst    534018919                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    534018919                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst    443647551                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    443647551                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst       303500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       303500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst   1129954380                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1129954380                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     13309748                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4879000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst   2801458250                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   2819646998                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     13309748                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4879000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst   2801458250                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   2819646998                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        25100                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2691                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      1096815                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total      1124606                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       119069                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       119069                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst        30209                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        30209                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst        23325                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23325                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst        62748                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        62748                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        25100                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2691                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      1159563                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      1187354                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        25100                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2691                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      1159563                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      1187354                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.024223                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.090673                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.067020                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.066122                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst     0.937270                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.937270                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst     0.968446                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.968446                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst     0.520160                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.520160                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.024223                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.090673                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.091541                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.090116                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.024223                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.090673                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.091541                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.090116                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21891.032895                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19995.901639                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22738.764913                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22722.833448                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18860.596136                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18860.596136                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19639.981894                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19639.981894                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 34619.761022                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 34619.761022                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21891.032895                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19995.901639                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26392.002204                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 26351.841103                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21891.032895                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19995.901639                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26392.002204                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 26351.841103                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs         5254                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs             187                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    28.096257                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        39442                       # number of writebacks
system.cpu1.l2cache.writebacks::total           39442                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst         1735                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total         1735                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst          340                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          340                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst         2075                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         2075                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst         2075                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         2075                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          608                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          244                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst        71774                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        72626                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       112390                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       112390                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst        28314                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28314                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst        22589                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22589                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst        32299                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        32299                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          608                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          244                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       104073                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       104925                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          608                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          244                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       104073                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       112390                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       217315                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      9050252                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3171000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst   1134657222                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1146878474                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   3172675528                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   3172675528                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst    408265220                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    408265220                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst    310198725                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    310198725                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst       254500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       254500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst    858509328                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    858509328                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      9050252                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3171000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   1993166550                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   2005387802                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      9050252                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3171000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   1993166550                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   3172675528                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   5178063330                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst    388960005                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    388960005                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst    260468006                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    260468006                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst    649428011                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    649428011                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.024223                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.090673                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.065439                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.064579                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst     0.937270                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.937270                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.968446                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.968446                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst     0.514742                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.514742                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.024223                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.090673                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.089752                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.088369                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.024223                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.090673                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.089752                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.183025                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14885.282895                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12995.901639                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15808.749993                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15791.568777                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28229.162096                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 28229.162096                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14419.199689                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14419.199689                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13732.291159                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13732.291159                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 26580.059073                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 26580.059073                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14885.282895                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12995.901639                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19151.620017                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19112.583293                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14885.282895                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12995.901639                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19151.620017                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28229.162096                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23827.454755                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           193696                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          469.979850                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            7249545                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           194043                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            37.360508                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     107387908500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.inst   469.979850                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.917929                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.917929                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          347                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          280                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           67                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.677734                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         15373685                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        15373685                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.inst      3863317                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3863317                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.inst      3184030                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       3184030                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst        91016                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        91016                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.inst        71184                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        71184                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.inst      7047347                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         7047347                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.inst      7047347                       # number of overall hits
system.cpu1.dcache.overall_hits::total        7047347                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.inst       184713                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       184713                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.inst       145139                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       145139                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst         5273                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         5273                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.inst        23325                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23325                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.inst       329852                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        329852                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.inst       329852                       # number of overall misses
system.cpu1.dcache.overall_misses::total       329852                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst   2791622179                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2791622179                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst   3393821873                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   3393821873                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst     95816000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     95816000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst    543674761                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    543674761                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst       324500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total       324500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.inst   6185444052                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   6185444052                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.inst   6185444052                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   6185444052                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.inst      4048030                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      4048030                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.inst      3329169                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      3329169                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst        96289                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        96289                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst        94509                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        94509                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.inst      7377199                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      7377199                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.inst      7377199                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      7377199                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.045630                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.045630                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.043596                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.043596                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.054762                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.054762                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.246802                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.246802                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.044712                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.044712                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.044712                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.044712                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15113.295648                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15113.295648                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23383.252420                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 23383.252420                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18171.060118                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18171.060118                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23308.671426                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23308.671426                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18752.179923                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 18752.179923                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18752.179923                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18752.179923                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       119069                       # number of writebacks
system.cpu1.dcache.writebacks::total           119069                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst        15047                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        15047                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst        52186                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total        52186                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.inst        67233                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        67233                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.inst        67233                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        67233                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst       169666                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       169666                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst        92953                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        92953                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst         5273                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5273                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst        23325                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23325                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.inst       262619                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       262619                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.inst       262619                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       262619                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst   2247676267                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2247676267                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst   2022089921                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2022089921                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst     85260000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     85260000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst    495802239                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    495802239                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst       310500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       310500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst   4269766188                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4269766188                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst   4269766188                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4269766188                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst    405245745                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    405245745                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst    279561993                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    279561993                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst    684807738                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    684807738                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.041913                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.041913                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.027921                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027921                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.054762                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.054762                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.246802                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.246802                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.035599                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.035599                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.035599                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035599                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13247.652841                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13247.652841                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 21753.896281                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21753.896281                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16169.163664                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16169.163664                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21256.258907                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21256.258907                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16258.405477                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16258.405477                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16258.405477                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16258.405477                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                36445                       # number of replacements
system.iocache.tags.tagsinuse               14.485749                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36461                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         268964842000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.485749                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.905359                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.905359                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328575                       # Number of tag accesses
system.iocache.tags.data_accesses              328575                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ide          255                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              255                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide           33                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total           33                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          255                       # number of demand (read+write) misses
system.iocache.demand_misses::total               255                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          255                       # number of overall misses
system.iocache.overall_misses::total              255                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     31822377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     31822377                       # number of ReadReq miss cycles
system.iocache.demand_miss_latency::realview.ide     31822377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     31822377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     31822377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     31822377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36257                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36257                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          255                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             255                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          255                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            255                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000910                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total     0.000910                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124793.635294                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124793.635294                       # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124793.635294                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124793.635294                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124793.635294                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124793.635294                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                      36224                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_misses::realview.ide          255                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          255                       # number of ReadReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          255                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          255                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          255                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          255                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     18561377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     18561377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2257984064                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2257984064                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     18561377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     18561377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     18561377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     18561377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72789.713725                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 72789.713725                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 72789.713725                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 72789.713725                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 72789.713725                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 72789.713725                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------