path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.846117                       # Number of seconds simulated
sim_ticks                                2846117015000                       # Number of ticks simulated
final_tick                               2846117015000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 113156                       # Simulator instruction rate (inst/s)
host_op_rate                                   137057                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2513496102                       # Simulator tick rate (ticks/s)
host_mem_usage                                 647580                       # Number of bytes of host memory used
host_seconds                                  1132.33                       # Real time elapsed on the host
sim_insts                                   128130877                       # Number of instructions simulated
sim_ops                                     155193960                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         7296                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1474816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1242668                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8247680                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         2432                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           378112                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           721620                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       564672                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12640384                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1474816                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       378112                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1852928                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8933696                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8951260                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker          114                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             23044                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             19938                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       128870                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           38                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              5908                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             11296                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         8823                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                198048                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          139589                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               143980                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2563                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              518185                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              436619                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2897871                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           854                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              132852                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              253545                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       198401                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4441273                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         518185                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         132852                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             651037                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3138907                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6157                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3145078                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3138907                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2563                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             518185                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             442776                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2897871                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          854                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             132852                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             253559                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       198401                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7586351                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        198048                       # Number of read requests accepted
system.physmem.writeReqs                       143980                       # Number of write requests accepted
system.physmem.readBursts                      198048                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     143980                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12666176                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8896                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8963584                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12640384                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8951260                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      139                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3897                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          51245                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12439                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12567                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12508                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12584                       # Per bank write bursts
system.physmem.perBankRdBursts::4               14823                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11920                       # Per bank write bursts
system.physmem.perBankRdBursts::6               13135                       # Per bank write bursts
system.physmem.perBankRdBursts::7               13383                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12319                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12338                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11698                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11134                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11462                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11917                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11661                       # Per bank write bursts
system.physmem.perBankRdBursts::15              12021                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8771                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9038                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9230                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8945                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8307                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8620                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9591                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9703                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8875                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8727                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8430                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8199                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8380                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8472                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8531                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8237                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
system.physmem.totGap                    2846116455500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     552                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  197468                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 139589                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     85140                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     62378                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     11568                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9695                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7750                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      6201                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5246                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4552                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3838                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       742                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      263                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      234                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      161                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      136                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2706                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4888                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5603                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6092                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6675                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7058                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     8476                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     9015                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    10231                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9841                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9581                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8847                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9302                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10565                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8547                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7994                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7600                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      422                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      278                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       39                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       40                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       33                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        91138                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      237.329061                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     134.886171                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     298.768529                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          49038     53.81%     53.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17709     19.43%     73.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6298      6.91%     80.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3704      4.06%     84.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2913      3.20%     87.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1386      1.52%     88.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          897      0.98%     89.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1023      1.12%     91.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8170      8.96%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          91138                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6991                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.308683                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      556.324450                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6990     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6991                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6991                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.033758                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.625060                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       11.557866                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5837     83.49%     83.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             357      5.11%     88.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             222      3.18%     91.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              60      0.86%     92.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              64      0.92%     93.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             166      2.37%     95.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              20      0.29%     96.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               6      0.09%     96.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              14      0.20%     96.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              10      0.14%     96.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               5      0.07%     96.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               9      0.13%     96.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             167      2.39%     99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               8      0.11%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               8      0.11%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               7      0.10%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               3      0.04%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               3      0.04%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.04%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.01%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.01%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.01%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            14      0.20%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             2      0.03%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.03%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6991                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5451252873                       # Total ticks spent queuing
system.physmem.totMemAccLat                9162046623                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    989545000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       27544.24                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  46294.24                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.45                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.15                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.44                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.15                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.56                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.87                       # Average write queue length when enqueuing
system.physmem.readRowHits                     164305                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     82521                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.02                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  58.91                       # Row buffer hit rate for writes
system.physmem.avgGap                      8321296.66                       # Average gap between requests
system.physmem.pageHitRate                      73.03                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  359440200                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  196123125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 806200200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                467888400                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           185894445360                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            83210904225                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1634677575750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1905612577260                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.548459                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2719308511052                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95038060000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     31769437698                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  329563080                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  179821125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 737482200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                439674480                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           185894445360                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            82251132525                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1635519480750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1905351599520                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.456762                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2720714979061                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95038060000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     30363879439                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          832                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1344                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          832                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1344                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           13                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             21                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          180                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          292                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              472                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          180                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          292                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          472                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          180                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          292                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             472                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               34784409                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         16478031                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          1480168                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            19725615                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               14342133                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            72.708167                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               11162624                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            702720                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    65972                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               65972                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        43486                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        22486                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples        65972                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0          65972    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        65972                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         6612                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 10372.504537                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  9312.931281                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  6218.139441                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         6425     97.17%     97.17% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767          170      2.57%     99.74% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151            7      0.11%     99.85% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303            5      0.08%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687            4      0.06%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         6612                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    327753000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      327753000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    327753000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5105     77.21%     77.21% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1507     22.79%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6612                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        65972                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        65972                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6612                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6612                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        72584                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    23562231                       # DTB read hits
system.cpu0.dtb.read_misses                     59962                       # DTB read misses
system.cpu0.dtb.write_hits                   17431474                       # DTB write hits
system.cpu0.dtb.write_misses                     6010                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3494                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1076                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1600                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      577                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                23622193                       # DTB read accesses
system.cpu0.dtb.write_accesses               17437484                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         40993705                       # DTB hits
system.cpu0.dtb.misses                          65972                       # DTB misses
system.cpu0.dtb.accesses                     41059677                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3855                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3855                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          305                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3550                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3855                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3855    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3855                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2424                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 10979.785479                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean  9797.993767                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  8035.967164                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767         2422     99.92%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2424                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    327059500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      327059500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    327059500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2124     87.62%     87.62% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          300     12.38%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2424                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3855                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3855                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2424                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2424                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         6279                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    68397916                       # ITB inst hits
system.cpu0.itb.inst_misses                      3855                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2226                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     7522                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                68401771                       # ITB inst accesses
system.cpu0.itb.hits                         68397916                       # DTB hits
system.cpu0.itb.misses                           3855                       # DTB misses
system.cpu0.itb.accesses                     68401771                       # DTB accesses
system.cpu0.numCycles                       225406925                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  107236402                       # Number of instructions committed
system.cpu0.committedOps                    129680129                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                      8567834                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     2087                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                  5466862375                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.101963                       # CPI: cycles per instruction
system.cpu0.ipc                              0.475746                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    2088                       # number of quiesce instructions executed
system.cpu0.tickCycles                      187552407                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                       37854518                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements           678280                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          485.010035                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           39540240                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           678792                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            58.250893                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        345600000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   485.010035                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.947285                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.947285                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          326                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         81933612                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        81933612                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     22071197                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       22071197                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     16340314                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      16340314                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       307086                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       307086                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       357744                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       357744                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       352756                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       352756                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     38411511                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        38411511                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     38718597                       # number of overall hits
system.cpu0.dcache.overall_hits::total       38718597                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       442022                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       442022                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       555005                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       555005                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       131972                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       131972                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20768                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        20768                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21303                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        21303                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       997027                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        997027                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1128999                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1128999                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5846536500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5846536500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   8888918500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   8888918500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    319234500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    319234500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    481221000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    481221000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       684000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       684000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  14735455000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  14735455000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  14735455000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  14735455000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     22513219                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     22513219                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     16895319                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     16895319                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       439058                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       439058                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       378512                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       378512                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       374059                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       374059                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     39408538                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     39408538                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     39847596                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     39847596                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.019634                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.019634                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.032850                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.032850                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.300580                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.300580                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054867                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054867                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.056951                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.056951                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.025300                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.025300                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028333                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.028333                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13226.799797                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13226.799797                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16015.925082                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 16015.925082                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15371.460901                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15371.460901                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22589.353612                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22589.353612                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14779.394139                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14779.394139                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13051.787468                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13051.787468                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       490245                       # number of writebacks
system.cpu0.dcache.writebacks::total           490245                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        69954                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        69954                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       243081                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       243081                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14749                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14749                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data       313035                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       313035                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data       313035                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       313035                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       372068                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       372068                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       311924                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       311924                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        99410                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        99410                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6019                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6019                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21303                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        21303                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       683992                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       683992                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       783402                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       783402                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        29426                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        29426                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        26162                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        26162                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        55588                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        55588                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4399139000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4399139000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4959161000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4959161000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1608557500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1608557500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     92509500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     92509500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    459936000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    459936000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       666000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       666000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9358300000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   9358300000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10966857500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  10966857500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5696567000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5696567000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4315116500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4315116500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10011683500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10011683500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016527                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016527                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018462                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018462                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.226417                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.226417                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.015902                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.015902                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.056951                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.056951                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.017356                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.017356                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019660                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.019660                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11823.481192                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11823.481192                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15898.619536                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15898.619536                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16181.043155                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16181.043155                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15369.579664                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15369.579664                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21590.198564                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21590.198564                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13681.885168                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13681.885168                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13999.016469                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13999.016469                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193589.580643                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193589.580643                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164938.326581                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 164938.326581                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 180105.121609                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 180105.121609                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1886353                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.780174                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           66503170                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1886865                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            35.245325                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6541312000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.780174                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999571                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999571                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          180                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          216                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          116                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        138666991                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       138666991                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     66503170                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       66503170                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     66503170                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        66503170                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     66503170                       # number of overall hits
system.cpu0.icache.overall_hits::total       66503170                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1886884                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1886884                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1886884                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1886884                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1886884                       # number of overall misses
system.cpu0.icache.overall_misses::total      1886884                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  17552107500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  17552107500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  17552107500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  17552107500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  17552107500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  17552107500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     68390054                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     68390054                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     68390054                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     68390054                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     68390054                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     68390054                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.027590                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.027590                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.027590                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.027590                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.027590                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.027590                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9302.165634                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9302.165634                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9302.165634                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9302.165634                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9302.165634                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9302.165634                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1886884                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1886884                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1886884                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1886884                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1886884                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1886884                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3426                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         3426                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3426                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         3426                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  16608666000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  16608666000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  16608666000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  16608666000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  16608666000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  16608666000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    314279000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    314279000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    314279000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    314279000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027590                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027590                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027590                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.027590                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027590                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.027590                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8802.165899                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8802.165899                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8802.165899                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  8802.165899                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8802.165899                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  8802.165899                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91733.508465                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91733.508465                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1753692                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1753724                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           28                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       222140                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          284631                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16080.562269                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           4811395                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          300867                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs           15.991767                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  8557.843574                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    57.688699                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.065125                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4677.760567                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1660.845415                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1126.358889                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.522329                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003521                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.285508                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.101370                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.068747                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.981480                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1014                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15208                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           12                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          351                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          393                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          258                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           11                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          273                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4117                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7919                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2851                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.061890                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000854                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.928223                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        85529410                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       85529410                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        77804                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4292                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         82096                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       490243                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       490243                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28207                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        28207                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1765                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         1765                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       212310                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       212310                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1823174                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1823174                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       376441                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       376441                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        77804                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4292                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1823174                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       588751                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        2494021                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        77804                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4292                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1823174                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       588751                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       2494021                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          777                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          131                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          908                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        27955                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        27955                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19533                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        19533                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            5                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        43457                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        43457                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        63710                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        63710                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101052                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       101052                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          777                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          131                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        63710                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       144509                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       209127                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          777                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          131                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        63710                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       144509                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       209127                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     26295000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3189000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total     29484000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    514165000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    514165000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    396282000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    396282000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       637497                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       637497                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2195149500                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2195149500                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   2860433500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   2860433500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   2915473994                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   2915473994                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     26295000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3189000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2860433500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   5110623494                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   8000540994                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     26295000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3189000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2860433500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   5110623494                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   8000540994                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        78581                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4423                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        83004                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       490243                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       490243                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56162                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        56162                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        21298                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        21298                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       255767                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       255767                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1886884                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      1886884                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       477493                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       477493                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        78581                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4423                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1886884                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       733260                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2703148                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        78581                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4423                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1886884                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       733260                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2703148                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.009888                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.029618                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.010939                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.497756                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.497756                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.917128                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.917128                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.169909                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.169909                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.033765                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.033765                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.211630                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.211630                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.009888                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.029618                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.033765                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.197077                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.077364                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.009888                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.029618                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.033765                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.197077                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.077364                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33841.698842                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24343.511450                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32471.365639                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18392.595242                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18392.595242                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20287.820611                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20287.820611                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 127499.400000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 127499.400000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50513.139425                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50513.139425                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44897.716214                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44897.716214                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28851.225052                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28851.225052                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33841.698842                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24343.511450                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44897.716214                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35365.433945                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 38256.853462                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33841.698842                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24343.511450                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44897.716214                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35365.433945                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 38256.853462                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs           59                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    29.500000                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       195819                       # number of writebacks
system.cpu0.l2cache.writebacks::total          195819                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         2770                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         2770                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           71                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           71                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          354                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          354                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           71                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3124                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         3195                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           71                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         3124                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         3195                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          777                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          131                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          908                       # number of ReadReq MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks         9247                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::total         9247                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       232905                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       232905                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        27955                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27955                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19533                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19533                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        40687                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        40687                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        63639                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        63639                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       100698                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       100698                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          777                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          131                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        63639                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       141385                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       205932                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          777                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          131                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        63639                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       141385                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       232905                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       438837                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3426                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        29426                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        32852                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        26162                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        26162                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3426                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        55588                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        59014                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     21633000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2403000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     24036000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13888716397                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  13888716397                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    558509999                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    558509999                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    298853000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    298853000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       529497                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       529497                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1645934000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1645934000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2476915500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2476915500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2292009994                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2292009994                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     21633000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2403000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2476915500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3937943994                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   6438895494                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     21633000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2403000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2476915500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3937943994                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13888716397                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  20327611891                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    286870500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5461072000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5747942500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4118636500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4118636500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    286870500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   9579708500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   9866579000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009888                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.029618                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.010939                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.497756                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.497756                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.917128                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.917128                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.159078                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.159078                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.033727                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.033727                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.210889                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.210889                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009888                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.029618                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.033727                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.192817                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.076182                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009888                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.029618                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.033727                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.192817                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.162343                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27841.698842                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18343.511450                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26471.365639                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59632.538576                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59632.538576                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19978.894616                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19978.894616                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15299.902729                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15299.902729                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 105899.400000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 105899.400000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40453.560105                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40453.560105                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38921.345401                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38921.345401                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22761.226578                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22761.226578                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27841.698842                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18343.511450                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38921.345401                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27852.629303                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31267.095420                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27841.698842                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18343.511450                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38921.345401                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27852.629303                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59632.538576                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46321.554224                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185586.624074                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174964.766224                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157428.197386                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157428.197386                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 172334.109880                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 167190.480225                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq        134550                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      2542059                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        31171                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        26162                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       862676                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      2186135                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       279695                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        92964                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43745                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       114531                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           26                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       284097                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       270085                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1886884                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       603437                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      5633887                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2503276                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11828                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       167039                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          8316030                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    120979776                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     82538715                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17692                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       314324                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         203850507                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    1178802                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      6482684                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       1.179159                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.383485                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           5321256     82.08%     82.08% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2           1161428     17.92%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       6482684                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    3211889987                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    113481999                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   2835744437                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1181675942                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      7408493                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     88460994                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups                5445699                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          3358034                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           328537                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             3334781                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                2260975                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            67.799805                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 969415                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             68088                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    29420                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               29420                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        21788                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         7632                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples        29420                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0          29420    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        29420                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         2708                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 10739.844904                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean  9761.358244                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  6619.660152                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-16383         2565     94.72%     94.72% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-32767          128      4.73%     99.45% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-49151            8      0.30%     99.74% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-65535            1      0.04%     99.78% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::81920-98303            4      0.15%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-114687            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         2708                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1720699264                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1720699264    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1720699264                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         2021     74.63%     74.63% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          687     25.37%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2708                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        29420                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        29420                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2708                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2708                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        32128                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     5163963                       # DTB read hits
system.cpu1.dtb.read_misses                     27269                       # DTB read misses
system.cpu1.dtb.write_hits                    4235498                       # DTB write hits
system.cpu1.dtb.write_misses                     2151                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2054                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      296                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   518                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      294                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 5191232                       # DTB read accesses
system.cpu1.dtb.write_accesses                4237649                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          9399461                       # DTB hits
system.cpu1.dtb.misses                          29420                       # DTB misses
system.cpu1.dtb.accesses                      9428881                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     2244                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                2244                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          181                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2063                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         2244                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           2244    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         2244                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1123                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 10959.928762                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 10069.580655                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  5627.290327                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191          289     25.73%     25.73% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383          792     70.53%     96.26% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575            4      0.36%     96.62% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767           34      3.03%     99.64% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151            3      0.27%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::90112-98303            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1123                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1720133764                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1720133764    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1720133764                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          954     84.95%     84.95% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          169     15.05%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1123                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2244                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2244                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1123                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1123                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         3367                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    10150571                       # ITB inst hits
system.cpu1.itb.inst_misses                      2244                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1161                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1947                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                10152815                       # ITB inst accesses
system.cpu1.itb.hits                         10150571                       # DTB hits
system.cpu1.itb.misses                           2244                       # DTB misses
system.cpu1.itb.accesses                     10152815                       # DTB accesses
system.cpu1.numCycles                        54273174                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   20894475                       # Number of instructions committed
system.cpu1.committedOps                     25513831                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                      1850967                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     2736                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                  5637336830                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.597489                       # CPI: cycles per instruction
system.cpu1.ipc                              0.384987                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2738                       # number of quiesce instructions executed
system.cpu1.tickCycles                       38589177                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                       15683997                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements           232297                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          482.192292                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            8906174                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           232671                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            38.277972                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      90623150500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   482.192292                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.941782                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.941782                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          374                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          316                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           58                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.730469                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         18859700                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        18859700                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      4719301                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        4719301                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      3908024                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       3908024                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        65371                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        65371                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        88156                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        88156                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        80067                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        80067                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      8627325                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         8627325                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      8692696                       # number of overall hits
system.cpu1.dcache.overall_hits::total        8692696                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       183894                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       183894                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       168264                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       168264                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        35705                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        35705                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17716                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        17716                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23526                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23526                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       352158                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        352158                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       387863                       # number of overall misses
system.cpu1.dcache.overall_misses::total       387863                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2718275000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2718275000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4151672000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   4151672000                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    326404500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    326404500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    549519500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    549519500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       392000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total       392000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   6869947000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   6869947000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   6869947000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   6869947000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      4903195                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      4903195                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      4076288                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      4076288                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       101076                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       101076                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       105872                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       105872                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       103593                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       103593                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      8979483                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      8979483                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      9080559                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      9080559                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.037505                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.037505                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.041279                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.041279                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.353249                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.353249                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.167334                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.167334                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.227100                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.227100                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.039218                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.039218                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.042714                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.042714                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14781.749269                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14781.749269                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24673.560595                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 24673.560595                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18424.277489                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18424.277489                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23357.965655                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23357.965655                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19508.138392                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19508.138392                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17712.303055                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 17712.303055                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       139329                       # number of writebacks
system.cpu1.dcache.writebacks::total           139329                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        18066                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        18066                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        62670                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total        62670                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12262                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12262                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        80736                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        80736                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        80736                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        80736                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       165828                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       165828                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       105594                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       105594                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        34258                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        34258                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5454                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5454                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23526                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23526                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       271422                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       271422                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       305680                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       305680                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         5722                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         5722                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         5009                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         5009                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        10731                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        10731                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2294657000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2294657000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2511298500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2511298500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    559951000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    559951000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     93173500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     93173500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    526001500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    526001500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       384000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       384000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4805955500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4805955500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5365906500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   5365906500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    990469500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    990469500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    857774500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    857774500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1848244000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1848244000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033820                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.033820                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.025904                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.025904                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.338933                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.338933                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051515                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051515                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.227100                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.227100                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030227                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.030227                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033663                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.033663                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13837.572666                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13837.572666                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23782.587079                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23782.587079                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16345.116469                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16345.116469                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17083.516685                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17083.516685                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22358.305704                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22358.305704                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17706.580528                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17706.580528                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17553.999280                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17553.999280                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173098.479553                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173098.479553                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171246.656019                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171246.656019                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 172234.088156                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 172234.088156                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          1036067                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.306675                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            9111880                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          1036579                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs             8.790338                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      72226761500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.306675                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975208                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975208                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          457                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           55                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         21333497                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        21333497                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      9111880                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        9111880                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      9111880                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         9111880                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      9111880                       # number of overall hits
system.cpu1.icache.overall_hits::total        9111880                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      1036579                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      1036579                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      1036579                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       1036579                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      1036579                       # number of overall misses
system.cpu1.icache.overall_misses::total      1036579                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   9180202500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   9180202500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   9180202500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   9180202500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   9180202500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   9180202500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     10148459                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     10148459                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     10148459                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     10148459                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     10148459                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     10148459                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.102142                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.102142                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.102142                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.102142                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.102142                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.102142                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8856.249741                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8856.249741                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8856.249741                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8856.249741                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8856.249741                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8856.249741                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      1036579                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      1036579                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      1036579                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      1036579                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      1036579                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      1036579                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          113                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          113                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          113                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          113                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8661913000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   8661913000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8661913000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   8661913000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8661913000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   8661913000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10059500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10059500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10059500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     10059500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.102142                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.102142                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.102142                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.102142                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.102142                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.102142                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8356.249741                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8356.249741                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8356.249741                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8356.249741                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8356.249741                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8356.249741                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89022.123894                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89022.123894                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89022.123894                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89022.123894                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued       272165                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       272190                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           22                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        68922                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           69326                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15661.573061                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           2410564                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           84006                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           28.695141                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  6188.157881                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    52.165341                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.100614                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  5579.436781                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2277.975966                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1563.736478                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.377695                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003184                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000006                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.340542                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.139037                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.095443                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.955907                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1195                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           50                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13435                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          666                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          525                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           12                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           21                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           17                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          301                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5728                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         7406                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.072937                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003052                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.820007                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        42699170                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       42699170                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        32497                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2653                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total         35150                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       139329                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       139329                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         2011                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         2011                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data         1071                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total         1071                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        38166                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        38166                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      1009291                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      1009291                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       131481                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total       131481                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        32497                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2653                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      1009291                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       169647                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        1214088                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        32497                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2653                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      1009291                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       169647                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       1214088                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          719                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          229                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          948                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29485                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        29485                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22454                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22454                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        35935                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        35935                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        27288                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        27288                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        74058                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        74058                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          719                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          229                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        27288                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       109993                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       138229                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          719                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          229                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        27288                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       109993                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       138229                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     17830000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4703000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     22533000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    557854000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    557854000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    449261000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    449261000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       372000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       372000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1407590499                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1407590499                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst   1060250500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total   1060250500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1775396994                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1775396994                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     17830000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4703000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst   1060250500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3182987493                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   4265770993                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     17830000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4703000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst   1060250500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3182987493                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   4265770993                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        33216                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2882                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total        36098                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       139329                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       139329                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31496                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        31496                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23525                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23525                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        74101                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        74101                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      1036579                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      1036579                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       205539                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       205539                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        33216                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2882                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      1036579                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       279640                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      1352317                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        33216                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2882                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      1036579                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       279640                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      1352317                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021646                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.079459                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.026262                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.936151                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.936151                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.954474                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.954474                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.484946                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.484946                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.026325                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.026325                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.360311                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.360311                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021646                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.079459                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.026325                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.393338                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.102216                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021646                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.079459                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.026325                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.393338                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.102216                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 24798.331015                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20537.117904                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23768.987342                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18919.925386                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18919.925386                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20008.060925                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20008.060925                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       372000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       372000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39170.460526                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39170.460526                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38854.093374                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38854.093374                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23973.061573                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23973.061573                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 24798.331015                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20537.117904                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38854.093374                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28938.091451                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 30860.174008                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 24798.331015                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20537.117904                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38854.093374                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28938.091451                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 30860.174008                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs           56                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           28                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        37014                       # number of writebacks
system.cpu1.l2cache.writebacks::total           37014                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          288                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          288                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           20                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           20                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          127                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          127                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           20                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          415                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          435                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           20                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          415                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          435                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          719                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          229                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          948                       # number of ReadReq MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         3215                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total         3215                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        35422                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        35422                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29485                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29485                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22454                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22454                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        35647                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        35647                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        27268                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        27268                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        73931                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        73931                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          719                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          229                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        27268                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       109578                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       137794                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          719                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          229                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        27268                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       109578                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        35422                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       173216                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          113                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         5722                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         5835                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         5009                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         5009                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          113                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        10731                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        10844                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     13516000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3329000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     16845000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1189902692                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1189902692                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    503727499                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    503727499                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    348590500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    348590500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       324000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       324000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1162178500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1162178500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    895970500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    895970500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1327142494                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1327142494                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     13516000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3329000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    895970500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2489320994                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   3402136494                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     13516000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3329000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    895970500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2489320994                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1189902692                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   4592039186                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9155500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    944653500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    953809000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    820084500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    820084500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9155500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1764738000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1773893500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021646                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.079459                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.026262                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.936151                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.936151                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.954474                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.954474                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.481060                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.481060                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.026306                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.026306                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.359693                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.359693                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021646                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.079459                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.026306                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.391854                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.101895                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021646                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.079459                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.026306                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.391854                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.128088                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17768.987342                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33592.193891                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33592.193891                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17084.195320                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17084.195320                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15524.650396                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15524.650396                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       324000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       324000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32602.420961                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32602.420961                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32857.947044                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32857.947044                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17951.096211                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17951.096211                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32857.947044                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22717.342843                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24690.019115                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32857.947044                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22717.342843                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33592.193891                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26510.479321                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81022.123894                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165091.488990                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163463.410454                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163722.200040                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163722.200040                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81022.123894                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 164452.334358                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163582.949096                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq         80046                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      1329975                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        31171                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         5009                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       511761                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      1258534                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        43565                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        76909                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        43045                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        89356                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           19                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           26                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        97332                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        80052                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      1036579                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       560078                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      3090316                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side      1000986                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7189                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        70268                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          4168759                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     66348288                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29828599                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        11528                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       132864                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          96321279                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    1191896                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      3797471                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       1.302048                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.459146                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1           2650451     69.80%     69.80% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2           1147020     30.20%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       3797471                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    1487742991                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     87115499                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   1555110854                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    456039835                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      4307000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     37064974                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                30994                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30994                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59422                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          846                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107912                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72920                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72920                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180832                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          447                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162794                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2483914                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40091000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               504000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           187482956                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84714000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36744000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36426                       # number of replacements
system.iocache.tags.tagsinuse                1.010803                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36442                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         270452648000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.010803                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.063175                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.063175                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328140                       # Number of tag accesses
system.iocache.tags.data_accesses              328140                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          236                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              236                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          236                       # number of demand (read+write) misses
system.iocache.demand_misses::total               236                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          236                       # number of overall misses
system.iocache.overall_misses::total              236                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     30330877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     30330877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4273955079                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4273955079                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     30330877                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     30330877                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     30330877                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     30330877                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          236                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            236                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          236                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             236                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          236                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            236                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 128520.665254                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 128520.665254                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117986.834116                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 117986.834116                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 128520.665254                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 128520.665254                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 128520.665254                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 128520.665254                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs            17                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.500000                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          236                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          236                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          236                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          236                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          236                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          236                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     18530877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     18530877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2462755079                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2462755079                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     18530877                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     18530877                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     18530877                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     18530877                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78520.665254                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 78520.665254                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67986.834116                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67986.834116                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 78520.665254                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 78520.665254                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 78520.665254                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 78520.665254                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   135428                       # number of replacements
system.l2c.tags.tagsinuse                64138.208301                       # Cycle average of tags in use
system.l2c.tags.total_refs                     442739                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   199807                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.215833                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   12941.285088                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    69.276334                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.031468                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     7274.373268                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2166.846690                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 31945.045858                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    24.318023                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.851962                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     4022.114049                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     1496.265741                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  4197.799819                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.197468                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001057                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.110998                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.033063                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.487443                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000371                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000013                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.061373                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.022831                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.064053                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.978671                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        29250                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           92                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        35037                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          144                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         5264                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        23842                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           91                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          315                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         3030                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        31679                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.446320                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.001404                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.534622                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  5824693                       # Number of tag accesses
system.l2c.tags.data_accesses                 5824693                       # Number of data accesses
system.l2c.Writeback_hits::writebacks          232832                       # number of Writeback hits
system.l2c.Writeback_hits::total               232832                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            3079                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             930                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                4009                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           233                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            92                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               325                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4022                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             2114                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 6136                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          393                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           81                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        44006                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        47229                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        46346                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker          166                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           37                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst        21446                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data        11079                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         8110                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           178893                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker           393                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            81                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               44006                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               51251                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        46346                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker           166                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            37                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               21446                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               13193                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         8110                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  185029                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          393                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           81                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              44006                       # number of overall hits
system.l2c.overall_hits::cpu0.data              51251                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        46346                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker          166                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           37                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              21446                       # number of overall hits
system.l2c.overall_hits::cpu1.data              13193                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         8110                       # number of overall hits
system.l2c.overall_hits::total                 185029                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          8747                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          4112                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             12859                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          835                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1227                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            2062                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          10918                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8428                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19346                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          114                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        19630                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         8718                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       129027                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker           38                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         5812                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         2889                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         8839                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         175069                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker          114                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             19630                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             19636                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       129027                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           38                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              5812                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             11317                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         8839                       # number of demand (read+write) misses
system.l2c.demand_misses::total                194415                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker          114                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            19630                       # number of overall misses
system.l2c.overall_misses::cpu0.data            19636                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       129027                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           38                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             5812                       # number of overall misses
system.l2c.overall_misses::cpu1.data            11317                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         8839                       # number of overall misses
system.l2c.overall_misses::total               194415                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data      8346500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      5785000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     14131500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1392500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1414500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      2807000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1077000000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    690485000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1767485000                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     10253000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       303000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1569061500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data    759147500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  13107894109                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker      3343000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker        83000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    479575000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    252543500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher   1024779080                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  17206982689                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker     10253000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       303000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1569061500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   1836147500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  13107894109                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      3343000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        83000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    479575000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    943028500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1024779080                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     18974467689                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker     10253000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       303000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1569061500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   1836147500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13107894109                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      3343000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        83000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    479575000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    943028500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1024779080                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    18974467689                       # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks       232832                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           232832                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        11826                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5042                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           16868                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         1068                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         1319                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2387                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        14940                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        10542                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            25482                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          507                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           82                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        63636                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        55947                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       175373                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker          204                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           38                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        27258                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        13968                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        16949                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       353962                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          507                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           82                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           63636                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           70887                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       175373                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker          204                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           38                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           27258                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           24510                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        16949                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              379444                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          507                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           82                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          63636                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          70887                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       175373                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker          204                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           38                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          27258                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          24510                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        16949                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             379444                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.739641                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.815549                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.762331                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.781835                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.930250                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.863846                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.730790                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.799469                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.759203                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.224852                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.012195                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.308473                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.155826                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.735729                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.186275                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.026316                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.213222                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.206830                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.521506                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.494598                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.224852                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.012195                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.308473                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.277004                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.735729                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.186275                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.026316                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.213222                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.461730                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.521506                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.512368                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.224852                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.012195                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.308473                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.277004                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.735729                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.186275                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.026316                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.213222                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.461730                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.521506                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.512368                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   954.212873                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1406.857977                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1098.957928                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1667.664671                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1152.811736                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1361.299709                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 98644.440374                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81927.503560                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 91361.780213                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 89938.596491                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       303000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 79931.813551                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87078.171599                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 101590.319150                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 87973.684211                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker        83000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82514.624914                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 87415.541710                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 115938.350492                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 98286.862260                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89938.596491                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       303000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 79931.813551                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 93509.243227                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101590.319150                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87973.684211                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        83000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 82514.624914                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 83328.488115                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 115938.350492                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 97597.755775                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89938.596491                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       303000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 79931.813551                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 93509.243227                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101590.319150                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87973.684211                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        83000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 82514.624914                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 83328.488115                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 115938.350492                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 97597.755775                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              103399                       # number of writebacks
system.l2c.writebacks::total                   103399                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            1                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            4                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  5                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 5                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         3802                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         3802                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         8747                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         4112                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        12859                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          835                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1227                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         2062                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        10918                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8428                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19346                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          114                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19629                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8718                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       129027                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker           38                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         5808                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         2889                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         8839                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       175064                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker          114                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        19629                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        19636                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       129027                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           38                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         5808                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        11317                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         8839                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           194410                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker          114                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        19629                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        19636                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       129027                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           38                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         5808                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        11317                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         8839                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          194410                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3426                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        29426                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          113                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         5718                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        38683                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        26162                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         5009                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        31171                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3426                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        55588                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          113                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        10727                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        69854                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    181705001                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     86116001                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    267821002                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     17444000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     25472500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     42916500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    967820000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    606205000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1574025000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      9113000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       293000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1372734500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    671967500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  11817624109                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker      2963000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker        73000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    421007000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    223653500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    936389080                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  15455817689                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      9113000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       293000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1372734500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   1639787500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  11817624109                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      2963000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        73000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    421007000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    829858500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    936389080                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  17029842689                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      9113000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       293000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1372734500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   1639787500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  11817624109                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      2963000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        73000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    421007000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    829858500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    936389080                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  17029842689                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    214924500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4931392500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6782000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    841666000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5994765000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3673788500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    734928500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4408717000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    214924500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   8605181000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6782000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1576594500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10403482000                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.739641                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.815549                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.762331                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.781835                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.930250                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.863846                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.730790                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.799469                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.759203                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.224852                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.012195                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.308457                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.155826                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735729                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.186275                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.026316                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.213075                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.206830                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.521506                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.494584                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.224852                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.012195                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.308457                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.277004                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735729                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.186275                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.026316                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.213075                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.461730                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.521506                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.512355                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.224852                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.012195                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.308457                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.277004                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735729                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.186275                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.026316                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.213075                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.461730                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.521506                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.512355                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20773.408140                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20942.607247                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20827.513959                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20891.017964                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20759.983700                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20813.045587                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 88644.440374                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71927.503560                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 81361.780213                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79938.596491                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       293000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 69934.000713                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77078.171599                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91590.319150                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 77973.684211                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker        73000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72487.431129                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 77415.541710                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105938.350492                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88286.670526                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79938.596491                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       293000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69934.000713                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83509.243227                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91590.319150                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77973.684211                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        73000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72487.431129                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73328.488115                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105938.350492                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 87597.565398                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79938.596491                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       293000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69934.000713                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83509.243227                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91590.319150                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77973.684211                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        73000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72487.431129                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73328.488115                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105938.350492                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 87597.565398                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167586.233263                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60017.699115                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147195.872683                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154971.563736                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 140424.604388                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146721.601118                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141436.495461                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154802.853134                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60017.699115                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 146974.410366                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 148931.800613                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               38683                       # Transaction distribution
system.membus.trans_dist::ReadResp             213983                       # Transaction distribution
system.membus.trans_dist::WriteReq              31171                       # Transaction distribution
system.membus.trans_dist::WriteResp             31171                       # Transaction distribution
system.membus.trans_dist::Writeback            139589                       # Transaction distribution
system.membus.trans_dist::CleanEvict            18226                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            78324                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          41642                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           15039                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
system.membus.trans_dist::ReadExReq             39751                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19228                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        175300                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107912                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           42                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14776                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       682330                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       805060                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108902                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108902                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 913962                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162794                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1344                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        29552                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19274524                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     19468214                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21785334                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           126049                       # Total snoops (count)
system.membus.snoop_fanout::samples            599148                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  599148    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              599148                       # Request fanout histogram
system.membus.reqLayer0.occupancy            91414000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               24328                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            12977999                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1005422091                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1166590180                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64371509                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.trans_dist::ReadReq              38687                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            518927                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             31171                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            31171                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           372432                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict           99547                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           82215                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         41967                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         124182                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           26                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           26                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            51561                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           51561                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       480255                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1133004                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       361504                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1494508                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     32818575                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6820071                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               39638646                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          465665                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          1285667                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.162057                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.368503                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                1077316     83.79%     83.79% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 208351     16.21%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            1285667                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          860205550                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           331500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         646726661                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         269148617                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------