path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.146775                       # Number of seconds simulated
sim_ticks                                1146774863500                       # Number of ticks simulated
final_tick                               1146774863500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  52366                       # Simulator instruction rate (inst/s)
host_op_rate                                    67406                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              970268509                       # Simulator tick rate (ticks/s)
host_mem_usage                                 448492                       # Number of bytes of host memory used
host_seconds                                  1181.92                       # Real time elapsed on the host
sim_insts                                    61892059                       # Number of instructions simulated
sim_ops                                      79667620                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.clcd     50331648                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker         2560                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          7022076                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          576                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3606712                       # Number of bytes read from this memory
system.physmem.bytes_read::total             60963700                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       763904                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       275840                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1039744                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4294592                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.inst         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.inst       3010344                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7321936                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd       6291456                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           40                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst            109794                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            9                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             56383                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               6457684                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           67103                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.inst             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.inst           752586                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               823939                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        43889738                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker          2232                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker           112                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst             6123326                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           502                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst             3145092                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                53161001                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         666132                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         240535                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             906668                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3744930                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.inst              14824                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.inst            2625052                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                6384807                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3744930                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       43889738                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2232                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker          112                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst            6138150                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          502                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst            5770144                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               59545808                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       6457684                       # Number of read requests accepted
system.physmem.writeReqs                       823939                       # Number of write requests accepted
system.physmem.readBursts                     6457684                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     823939                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                413268352                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     23424                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7334336                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  60963700                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7321936                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      366                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  709320                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          12375                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              403317                       # Per bank write bursts
system.physmem.perBankRdBursts::1              403674                       # Per bank write bursts
system.physmem.perBankRdBursts::2              403089                       # Per bank write bursts
system.physmem.perBankRdBursts::3              403454                       # Per bank write bursts
system.physmem.perBankRdBursts::4              406236                       # Per bank write bursts
system.physmem.perBankRdBursts::5              403730                       # Per bank write bursts
system.physmem.perBankRdBursts::6              403529                       # Per bank write bursts
system.physmem.perBankRdBursts::7              403381                       # Per bank write bursts
system.physmem.perBankRdBursts::8              403672                       # Per bank write bursts
system.physmem.perBankRdBursts::9              404158                       # Per bank write bursts
system.physmem.perBankRdBursts::10             403104                       # Per bank write bursts
system.physmem.perBankRdBursts::11             402562                       # Per bank write bursts
system.physmem.perBankRdBursts::12             403651                       # Per bank write bursts
system.physmem.perBankRdBursts::13             403575                       # Per bank write bursts
system.physmem.perBankRdBursts::14             403252                       # Per bank write bursts
system.physmem.perBankRdBursts::15             402934                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7008                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7418                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6865                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7084                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7615                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7300                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7325                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7167                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7323                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7753                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6901                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6492                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7387                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7157                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7029                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6775                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    1146771945000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     109                       # Read request sizes (log2)
system.physmem.readPktSize::3                 6291456                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  166119                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 756836                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  67103                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    558746                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    398674                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    399850                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    441647                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    404684                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                    430598                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   1121698                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                   1089151                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                   1417401                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     50859                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    42455                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    39349                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    37752                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     8359                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     8007                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     7903                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      180                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     3958                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3977                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6613                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6665                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6671                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6670                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6668                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6668                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6670                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6670                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6677                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     6672                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6683                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6670                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6668                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6670                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6669                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6665                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       461513                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      911.356100                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     779.117173                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     292.189115                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24977      5.41%      5.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        21582      4.68%     10.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5972      1.29%     11.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2646      0.57%     11.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2555      0.55%     12.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1574      0.34%     12.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         4102      0.89%     13.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          979      0.21%     13.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       397126     86.05%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         461513                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6665                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean       968.839160                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev    26148.924018                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-65535          6658     99.89%     99.89% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-262143            3      0.05%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::589824-655359            1      0.02%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::786432-851967            1      0.02%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6665                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6665                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.194149                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.165520                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.984786                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               2686     40.30%     40.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 20      0.30%     40.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               3941     59.13%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                 15      0.23%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                  3      0.05%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6665                       # Writes before turning the bus around for reads
system.physmem.totQLat                   165007028750                       # Total ticks spent queuing
system.physmem.totMemAccLat              286081741250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  32286590000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25553.49                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44303.49                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         360.37                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           6.40                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       53.16                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        6.38                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.87                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.82                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         4.16                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.54                       # Average write queue length when enqueuing
system.physmem.readRowHits                    6015984                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     94420                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.17                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  82.38                       # Row buffer hit rate for writes
system.physmem.avgGap                       157488.51                       # Average gap between requests
system.physmem.pageHitRate                      92.98                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     908124290750                       # Time in different power states
system.physmem.memoryStateTime::REF       38293320000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      200357121750                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          256                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          256                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            4                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            7                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             11                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          223                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          391                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              614                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          223                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          391                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          614                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          223                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          391                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             614                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     61651742                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq             7506663                       # Transaction distribution
system.membus.trans_dist::ReadResp            7506663                       # Transaction distribution
system.membus.trans_dist::WriteReq             767825                       # Transaction distribution
system.membus.trans_dist::WriteResp            767825                       # Transaction distribution
system.membus.trans_dist::Writeback             67103                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            33483                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          17276                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           12375                       # Transaction distribution
system.membus.trans_dist::ReadExReq            137796                       # Transaction distribution
system.membus.trans_dist::ReadExResp           137454                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382664                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           22                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        11280                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          874                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1976707                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4371551                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     12582912                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     12582912                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               16954463                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390012                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port          704                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        22560                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1748                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17953988                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     20369020                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port     50331648                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total     50331648                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            70700668                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               70700668                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1725618000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               16500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            10203000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy              700000                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy          8808401000                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.8                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4909176600                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
system.membus.respLayer2.occupancy        15579623500                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                    73595                       # number of replacements
system.l2c.tags.tagsinuse                53913.869309                       # Cycle average of tags in use
system.l2c.tags.total_refs                    2430089                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   138750                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    17.514155                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   38825.506974                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    30.840279                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.001297                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     8944.299229                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     7.867460                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     6105.354070                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.592430                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000471                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.136479                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000120                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.093160                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.822660                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65141                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2303                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         8599                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        54129                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000214                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.993973                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 23296068                       # Number of tag accesses
system.l2c.tags.data_accesses                23296068                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        29004                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         6772                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             959141                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        26476                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         5085                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             968677                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1995155                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          576981                       # number of Writeback hits
system.l2c.Writeback_hits::total               576981                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.inst             913                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.inst             959                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1872                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.inst           209                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.inst           100                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               309                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.inst            58748                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.inst            50778                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               109526                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         29004                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          6772                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             1017889                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         26476                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          5085                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             1019455                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2104681                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        29004                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         6772                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            1017889                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        26476                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         5085                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            1019455                       # number of overall hits
system.l2c.overall_hits::total                2104681                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           40                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            16374                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            9                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             9914                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                26339                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.inst          4863                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.inst          4102                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              8965                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.inst          683                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.inst          310                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             993                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.inst          92483                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.inst          47388                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             139871                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           40                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst            108857                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            9                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             57302                       # number of demand (read+write) misses
system.l2c.demand_misses::total                166210                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           40                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst           108857                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            9                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            57302                       # number of overall misses
system.l2c.overall_misses::total               166210                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      3039250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       149500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst   1157856000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       661250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    747415749                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1909121749                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.inst      8211643                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.inst     13589417                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     21801060                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.inst       673971                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.inst      2091409                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      2765380                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.inst   6321431326                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.inst   3362017496                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   9683448822                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      3039250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       149500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   7479287326                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       661250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   4109433245                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     11592570571                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      3039250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       149500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   7479287326                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       661250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   4109433245                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    11592570571                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        29044                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         6774                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         975515                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        26485                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         5085                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         978591                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2021494                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       576981                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           576981                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.inst         5776                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.inst         5061                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           10837                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.inst          892                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.inst          410                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1302                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.inst       151231                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.inst        98166                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           249397                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        29044                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6774                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         1126746                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        26485                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5085                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         1076757                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2270891                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        29044                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6774                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        1126746                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        26485                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5085                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        1076757                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2270891                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001377                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000295                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.016785                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000340                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010131                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.013029                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.inst     0.841932                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.inst     0.810512                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.827258                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.inst     0.765695                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.inst     0.756098                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.762673                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.inst     0.611535                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.inst     0.482733                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.560837                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001377                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000295                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.096612                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000340                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.053217                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.073192                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001377                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000295                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.096612                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000340                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.053217                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.073192                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 75981.250000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70713.081715                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 73472.222222                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75389.928283                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 72482.696723                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst  1688.596134                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst  3312.875914                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2431.796988                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst   986.780381                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst  6746.480645                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  2784.874119                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 68352.360174                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 70946.600321                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 69231.283268                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 75981.250000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 68707.454054                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 73472.222222                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 71715.354525                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 69746.528915                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 75981.250000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 68707.454054                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 73472.222222                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 71715.354525                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 69746.528915                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               67103                       # number of writebacks
system.l2c.writebacks::total                    67103                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst            49                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst            19                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                68                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst             49                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             19                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 68                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst            49                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            19                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                68                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           40                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        16325                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            9                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         9895                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           26271                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.inst         4863                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.inst         4102                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         8965                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst          683                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst          310                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          993                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.inst        92483                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.inst        47388                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        139871                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           40                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst       108808                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            9                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        57283                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           166142                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           40                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst       108808                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            9                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        57283                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          166142                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      2549250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       125000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    950227250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       549750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    622555749                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1576006999                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst     48716838                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst     41086590                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     89803428                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst      6847181                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst      3100809                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      9947990                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst   5160123162                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst   2766953994                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   7927077156                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2549250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   6110350412                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       549750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   3389509743                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   9503084155                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2549250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       125000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   6110350412                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       549750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   3389509743                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   9503084155                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 156402291235                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst  10978060744                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167380351979                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst   1364398990                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst  15414990793                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  16779389783                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 157766690225                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst  26393051537                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 184159741762                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001377                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000295                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.016735                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000340                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010111                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.012996                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst     0.841932                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.810512                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.827258                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.765695                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.756098                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.762673                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst     0.611535                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.482733                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.560837                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001377                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000295                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.096568                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000340                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.053200                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.073162                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001377                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000295                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.096568                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000340                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.053200                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.073162                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63731.250000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58206.875957                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62916.194947                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 59990.369571                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10017.856878                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10016.233545                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10017.114110                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10025.155198                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10002.609677                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10018.116818                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 55795.369549                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58389.338947                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56674.200914                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63731.250000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56157.179729                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59171.302882                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 57198.566016                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63731.250000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56157.179729                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59171.302882                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 57198.566016                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                   164548117                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            3298522                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           3298521                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            767825                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           767825                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           576981                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           32938                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         17585                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          50523                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           260723                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          260723                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1574360                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3288712                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        16464                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        66826                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1600801                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      2571055                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side        13478                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        62668                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               9194364                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     50355392                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     43867388                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        27096                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       116176                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     51198592                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     38125568                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side        20340                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side       105940                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          183816492                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             183816492                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus         4883152                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         5169541990                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.5                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        3546630183                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        2800512724                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           9693493                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          37783748                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy        3604679924                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy        1938501968                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer8.occupancy           8396493                       # Layer occupancy (ticks)
system.toL2Bus.respLayer8.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer9.occupancy          36187242                       # Layer occupancy (ticks)
system.toL2Bus.respLayer9.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      45973854                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq              7474822                       # Transaction distribution
system.iobus.trans_dist::ReadResp             7474822                       # Transaction distribution
system.iobus.trans_dist::WriteReq                7966                       # Transaction distribution
system.iobus.trans_dist::WriteResp               7966                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30566                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8050                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          732                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          498                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2382664                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     12582912                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     12582912                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                14965576                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40335                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16100                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         1464                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          273                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2390012                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side     50331648                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total     50331648                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total             52721660                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                52721660                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21429000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              4031000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               372000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               299000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.1                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy          6291456000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.5                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374698000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.2                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         15850285500                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.4                       # Layer utilization (%)
system.cpu0.branchPred.lookups                6861856                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          5181081                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           652173                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             4714052                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                3350352                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            71.071596                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 844036                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             70439                       # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     8249046                       # DTB read hits
system.cpu0.dtb.read_misses                     22426                       # DTB read misses
system.cpu0.dtb.write_hits                    6048331                       # DTB write hits
system.cpu0.dtb.write_misses                     1452                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1952                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1134                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   199                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      288                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 8271472                       # DTB read accesses
system.cpu0.dtb.write_accesses                6049783                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         14297377                       # DTB hits
system.cpu0.dtb.misses                          23878                       # DTB misses
system.cpu0.dtb.accesses                     14321255                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                    12515958                       # ITB inst hits
system.cpu0.itb.inst_misses                      4886                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1295                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     2118                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                12520844                       # ITB inst accesses
system.cpu0.itb.hits                         12515958                       # DTB hits
system.cpu0.itb.misses                           4886                       # DTB misses
system.cpu0.itb.accesses                     12520844                       # DTB accesses
system.cpu0.numCycles                       433909161                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   29915294                       # Number of instructions committed
system.cpu0.committedOps                     39343022                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                      1900672                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                    39481                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                  1859706962                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                             14.504593                       # CPI: cycles per instruction
system.cpu0.ipc                              0.068944                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   50347                       # number of quiesce instructions executed
system.cpu0.tickCycles                      353761855                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                       80147306                       # Total number of cycles that the object has spent stopped
system.cpu0.icache.tags.replacements           784713                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.784867                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           11728456                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           785225                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            14.936427                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      10280766000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   510.784867                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.997627                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.997627                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          506                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         13298912                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        13298912                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     11728456                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       11728456                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     11728456                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        11728456                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     11728456                       # number of overall hits
system.cpu0.icache.overall_hits::total       11728456                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       785228                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       785228                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       785228                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        785228                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       785228                       # number of overall misses
system.cpu0.icache.overall_misses::total       785228                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10819127683                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  10819127683                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  10819127683                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  10819127683                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  10819127683                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  10819127683                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     12513684                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     12513684                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     12513684                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     12513684                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     12513684                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     12513684                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.062750                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.062750                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.062750                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.062750                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.062750                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.062750                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13778.326401                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13778.326401                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13778.326401                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13778.326401                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13778.326401                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13778.326401                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       785228                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       785228                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       785228                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       785228                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       785228                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       785228                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9244507317                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   9244507317                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9244507317                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   9244507317                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9244507317                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   9244507317                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    171313500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    171313500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    171313500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    171313500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.062750                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.062750                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.062750                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.062750                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.062750                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.062750                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11773.023016                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11773.023016                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11773.023016                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11773.023016                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11773.023016                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11773.023016                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           332522                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          495.116335                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           12493941                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           332889                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            37.531853                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        236260250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.inst   495.116335                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.967024                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.967024                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          367                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          367                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.716797                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         52581205                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        52581205                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.inst      6652234                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6652234                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.inst      5513247                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       5513247                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst       152467                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       152467                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.inst       153686                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       153686                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.inst     12165481                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        12165481                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.inst     12165481                       # number of overall hits
system.cpu0.dcache.overall_hits::total       12165481                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.inst       257861                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       257861                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.inst       307489                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       307489                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst         8753                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         8753                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.inst         7461                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7461                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.inst       565350                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        565350                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.inst       565350                       # number of overall misses
system.cpu0.dcache.overall_misses::total       565350                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst   3878128215                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   3878128215                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst  15135680350                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  15135680350                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst     89040000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     89040000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst     47241681                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     47241681                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.inst  19013808565                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  19013808565                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.inst  19013808565                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  19013808565                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.inst      6910095                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6910095                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.inst      5820736                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5820736                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst       161220                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       161220                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst       161147                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       161147                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.inst     12730831                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     12730831                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.inst     12730831                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     12730831                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.037317                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.037317                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.052826                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.052826                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.054292                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054292                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.046299                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.046299                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.044408                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.044408                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.044408                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.044408                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 15039.607444                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15039.607444                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 49223.485556                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 49223.485556                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 10172.512282                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10172.512282                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst  6331.816244                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6331.816244                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 33631.924587                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33631.924587                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 33631.924587                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33631.924587                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       307804                       # number of writebacks
system.cpu0.dcache.writebacks::total           307804                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst        51446                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        51446                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       139700                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       139700                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst           20                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total           20                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.inst       191146                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       191146                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.inst       191146                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       191146                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst       206415                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       206415                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst       167789                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       167789                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst         8733                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8733                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst         7461                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7461                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.inst       374204                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       374204                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.inst       374204                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       374204                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst   2545797312                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2545797312                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst   7212492893                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7212492893                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst     71207000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     71207000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst     32318319                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     32318319                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst   9758290205                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   9758290205                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst   9758290205                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   9758290205                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170750199252                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170750199252                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   1513150500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1513150500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 172263349752                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 172263349752                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.029872                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.029872                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.028826                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.028826                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.054168                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.054168                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.046299                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.046299                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.029394                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.029394                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.029394                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.029394                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12333.392980                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12333.392980                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 42985.493048                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42985.493048                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst  8153.784496                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8153.784496                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst  4331.633695                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4331.633695                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26077.460970                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26077.460970                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26077.460970                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26077.460970                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                6346953                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          4931527                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           433505                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             4095605                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                3083437                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            75.286484                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 663921                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             63861                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     7581512                       # DTB read hits
system.cpu1.dtb.read_misses                     20239                       # DTB read misses
system.cpu1.dtb.write_hits                    5551171                       # DTB write hits
system.cpu1.dtb.write_misses                     2521                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1717                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     2404                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   233                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      237                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 7601751                       # DTB read accesses
system.cpu1.dtb.write_accesses                5553692                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         13132683                       # DTB hits
system.cpu1.dtb.misses                          22760                       # DTB misses
system.cpu1.dtb.accesses                     13155443                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                    11349850                       # ITB inst hits
system.cpu1.itb.inst_misses                      4207                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1191                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     2046                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                11354057                       # ITB inst accesses
system.cpu1.itb.hits                         11349850                       # DTB hits
system.cpu1.itb.misses                           4207                       # DTB misses
system.cpu1.itb.accesses                     11354057                       # DTB accesses
system.cpu1.numCycles                       149527233                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   31976765                       # Number of instructions committed
system.cpu1.committedOps                     40324598                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                      1783017                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                    39969                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                  2144960974                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              4.676121                       # CPI: cycles per instruction
system.cpu1.ipc                              0.213852                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   40497                       # number of quiesce instructions executed
system.cpu1.tickCycles                      120083069                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                       29444164                       # Total number of cycles that the object has spent stopped
system.cpu1.icache.tags.replacements           800234                       # number of replacements
system.cpu1.icache.tags.tagsinuse          480.617194                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           10546899                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           800746                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            13.171341                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      82063984250                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   480.617194                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.938705                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.938705                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          194                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3            8                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         12148392                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        12148392                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     10546899                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       10546899                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     10546899                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        10546899                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     10546899                       # number of overall hits
system.cpu1.icache.overall_hits::total       10546899                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       800747                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       800747                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       800747                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        800747                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       800747                       # number of overall misses
system.cpu1.icache.overall_misses::total       800747                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  10721128674                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  10721128674                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  10721128674                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  10721128674                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  10721128674                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  10721128674                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     11347646                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     11347646                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     11347646                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     11347646                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     11347646                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     11347646                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.070565                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.070565                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.070565                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.070565                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.070565                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.070565                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13388.908949                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13388.908949                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13388.908949                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13388.908949                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13388.908949                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13388.908949                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       800747                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       800747                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       800747                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       800747                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       800747                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       800747                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   9117705326                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   9117705326                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   9117705326                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   9117705326                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   9117705326                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   9117705326                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5654750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5654750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5654750                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      5654750                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.070565                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.070565                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.070565                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.070565                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.070565                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.070565                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11386.499514                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11386.499514                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11386.499514                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11386.499514                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11386.499514                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11386.499514                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           301108                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          446.775625                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           11731236                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           301620                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            38.894092                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      76702840250                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.inst   446.775625                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.872609                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.872609                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          344                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           61                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         49070289                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        49070289                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.inst      7114972                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        7114972                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.inst      4425981                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4425981                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst        78462                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        78462                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.inst        79072                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        79072                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.inst     11540953                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        11540953                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.inst     11540953                       # number of overall hits
system.cpu1.dcache.overall_hits::total       11540953                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.inst       243175                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       243175                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.inst       224036                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       224036                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst        10782                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        10782                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.inst        10124                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10124                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.inst       467211                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        467211                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.inst       467211                       # number of overall misses
system.cpu1.dcache.overall_misses::total       467211                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst   3616409978                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   3616409978                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst   8727689439                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   8727689439                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst     90341500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     90341500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst     50520310                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     50520310                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.inst  12344099417                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  12344099417                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.inst  12344099417                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  12344099417                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.inst      7358147                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      7358147                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.inst      4650017                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      4650017                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst        89244                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        89244                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst        89196                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        89196                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.inst     12008164                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     12008164                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.inst     12008164                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     12008164                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.033048                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.033048                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.048180                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.048180                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.120815                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.120815                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.113503                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.113503                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.038908                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.038908                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.038908                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.038908                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14871.635563                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14871.635563                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 38956.638393                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 38956.638393                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst  8378.918568                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8378.918568                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst  4990.153102                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  4990.153102                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26420.823604                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 26420.823604                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26420.823604                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 26420.823604                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       269177                       # number of writebacks
system.cpu1.dcache.writebacks::total           269177                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst        37509                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        37509                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst        98167                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total        98167                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst           30                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total           30                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.inst       135676                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       135676                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.inst       135676                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       135676                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst       205666                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       205666                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst       125869                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       125869                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst        10752                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        10752                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst        10124                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10124                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.inst       331535                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       331535                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.inst       331535                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       331535                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst   2422782037                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2422782037                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst   4131508096                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   4131508096                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst     68345000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     68345000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst     30271690                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     30271690                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst   6554290133                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   6554290133                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst   6554290133                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   6554290133                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst  11992419500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total  11992419500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst  24672512707                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  24672512707                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst  36664932207                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total  36664932207                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.027951                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.027951                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.027069                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027069                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.120479                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.120479                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.113503                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.113503                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.027609                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027609                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.027609                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.027609                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11780.177749                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11780.177749                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 32823.873202                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32823.873202                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst  6356.491815                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6356.491815                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst  2990.091861                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  2990.091861                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19769.526997                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19769.526997                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19769.526997                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19769.526997                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 721880739500                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 721880739500                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 721880739500                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 721880739500                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------