path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.848599                       # Number of seconds simulated
sim_ticks                                2848598682500                       # Number of ticks simulated
final_tick                               2848598682500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 262669                       # Simulator instruction rate (inst/s)
host_op_rate                                   318064                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5881753499                       # Simulator tick rate (ticks/s)
host_mem_usage                                 626168                       # Number of bytes of host memory used
host_seconds                                   484.31                       # Real time elapsed on the host
sim_insts                                   127213455                       # Number of instructions simulated
sim_ops                                     154041729                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker         9280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1663936                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1359352                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8597824                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         1280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           234560                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           659412                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       325376                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12852044                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1663936                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       234560                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1898496                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8978368                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8995932                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker          145                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             25999                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             21764                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       134341                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           20                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              3665                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             10324                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         5084                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                201358                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          140287                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               144678                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3258                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              584124                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              477200                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      3018264                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           449                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               82342                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              231486                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       114223                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4511707                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         584124                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          82342                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             666467                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3151854                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6152                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3158020                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3151854                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3258                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             584124                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             483352                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      3018264                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          449                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              82342                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             231500                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       114223                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7669728                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        201358                       # Number of read requests accepted
system.physmem.writeReqs                       144678                       # Number of write requests accepted
system.physmem.readBursts                      201358                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     144678                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12877760                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9152                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9008896                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12852044                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8995932                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      143                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12337                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12726                       # Per bank write bursts
system.physmem.perBankRdBursts::2               13547                       # Per bank write bursts
system.physmem.perBankRdBursts::3               13037                       # Per bank write bursts
system.physmem.perBankRdBursts::4               15119                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12845                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12657                       # Per bank write bursts
system.physmem.perBankRdBursts::7               13022                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12280                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12341                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11583                       # Per bank write bursts
system.physmem.perBankRdBursts::11              10739                       # Per bank write bursts
system.physmem.perBankRdBursts::12              12026                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12946                       # Per bank write bursts
system.physmem.perBankRdBursts::14              12179                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11831                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8873                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9291                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9856                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9274                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8405                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8988                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8961                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9107                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8695                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8769                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8272                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7845                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8751                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8985                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8630                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8062                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          74                       # Number of times write queue was full causing retry
system.physmem.totGap                    2848598144000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     555                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  200775                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 140287                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     85113                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     63389                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     11790                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9690                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      8148                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      6744                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5598                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4878                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      4009                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1035                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      281                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      239                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      165                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      134                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2537                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3403                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4421                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5052                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6454                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7065                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7505                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8553                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8479                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9706                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8910                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8556                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8923                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     9945                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8410                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     8137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      883                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      583                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      405                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      317                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      271                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      267                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      284                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      263                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      264                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      283                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      208                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      184                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      225                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      216                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        88566                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      247.121830                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     141.476955                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     302.598654                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          44693     50.46%     50.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18724     21.14%     71.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6637      7.49%     79.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3795      4.28%     83.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2919      3.30%     86.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1572      1.77%     88.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          960      1.08%     89.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1024      1.16%     90.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8242      9.31%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          88566                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6985                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.806586                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      558.021687                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6983     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6985                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6985                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.152326                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.495944                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       14.110349                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5869     84.02%     84.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             441      6.31%     90.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              79      1.13%     91.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              44      0.63%     92.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             241      3.45%     95.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              25      0.36%     95.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              15      0.21%     96.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              10      0.14%     96.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              17      0.24%     96.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               8      0.11%     96.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               3      0.04%     96.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               7      0.10%     96.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             146      2.09%     98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               4      0.06%     98.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.06%     98.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               6      0.09%     99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               7      0.10%     99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.01%     99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.03%     99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.04%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             3      0.04%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111            11      0.16%     99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.03%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.03%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            10      0.14%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             2      0.03%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             3      0.04%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             3      0.04%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             3      0.04%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             2      0.03%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             3      0.04%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             2      0.03%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             2      0.03%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             3      0.04%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-243             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6985                       # Writes before turning the bus around for reads
system.physmem.totQLat                     9483410947                       # Total ticks spent queuing
system.physmem.totMemAccLat               13256192197                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1006075000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       47130.74                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  65880.74                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.52                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.16                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.51                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.16                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.98                       # Average write queue length when enqueuing
system.physmem.readRowHits                     166670                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     86742                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.83                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  61.61                       # Row buffer hit rate for writes
system.physmem.avgGap                      8232086.10                       # Average gap between requests
system.physmem.pageHitRate                      74.10                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  334044900                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  177549075                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 751770600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                379781100                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           5711234880.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             5249821980                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy              307614240                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       11585671230                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        8434613280                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       670304268120                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             703238620035                       # Total energy per rank (pJ)
system.physmem_0.averagePower              246.871777                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           2836104738853                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE      545953693                       # Time in different power states
system.physmem_0.memoryStateTime::REF      2426690000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   2788907518000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN  21965166332                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      9346009704                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  25407344771                       # Time in different power states
system.physmem_1.actEnergy                  298323480                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  158558895                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 684904500                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                355006980                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           5713078800.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             5198973990                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy              317598720                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       10947475860                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        8696180160                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       670560217290                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             702932935245                       # Total energy per rank (pJ)
system.physmem_1.averagePower              246.764467                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           2836364452001                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE      573854684                       # Time in different power states
system.physmem_1.memoryStateTime::REF      2428124000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   2789710596750                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN  22646269258                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      9232187315                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN  24007650493                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          832                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1344                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          832                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1344                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           13                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             21                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          180                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          292                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              472                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          180                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          292                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          472                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          180                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          292                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             472                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               21387746                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         14055793                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          1067110                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            13655999                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                8982856                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            65.779560                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                3510572                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            218030                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups         788067                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits            592988                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses          195079                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted       105213                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                    69629                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               69629                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        46094                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        23535                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples        69629                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0          69629    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        69629                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         7649                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12135.050333                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 10988.955041                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 11832.363963                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535         7639     99.87%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071            6      0.08%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143            2      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            2      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         7649                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    338892000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      338892000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    338892000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5959     77.91%     77.91% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1690     22.09%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         7649                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        69629                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        69629                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7649                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7649                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        77278                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    17966885                       # DTB read hits
system.cpu0.dtb.read_misses                     63028                       # DTB read misses
system.cpu0.dtb.write_hits                   15039551                       # DTB write hits
system.cpu0.dtb.write_misses                     6601                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3754                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1491                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  2059                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      586                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                18029913                       # DTB read accesses
system.cpu0.dtb.write_accesses               15046152                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         33006436                       # DTB hits
system.cpu0.dtb.misses                          69629                       # DTB misses
system.cpu0.dtb.accesses                     33076065                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                     4318                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                4318                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          325                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3993                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         4318                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           4318    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         4318                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2683                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12304.137160                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11560.884208                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  4695.711947                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          502     18.71%     18.71% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1984     73.95%     92.66% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575          147      5.48%     98.14% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           31      1.16%     99.29% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959           18      0.67%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-106495            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2683                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    338263500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      338263500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    338263500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2363     88.07%     88.07% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          320     11.93%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2683                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         4318                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         4318                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2683                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2683                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         7001                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    39752533                       # ITB inst hits
system.cpu0.itb.inst_misses                      4318                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2396                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     7865                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                39756851                       # ITB inst accesses
system.cpu0.itb.hits                         39752533                       # DTB hits
system.cpu0.itb.misses                           4318                       # DTB misses
system.cpu0.itb.accesses                     39756851                       # DTB accesses
system.cpu0.numPwrStateTransitions               3708                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         1854                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    1488611861.955232                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   23946276211.601498                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         1085     58.52%     58.52% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10          762     41.10%     99.62% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11            1      0.05%     99.68% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.05%     99.73% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.05%     99.78% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            4      0.22%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 499963838164                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           1854                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON    88712290435                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 2759886392065                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                       177427128                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   82154396                       # Number of instructions committed
system.cpu0.committedOps                     98918766                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                      5358225                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     1854                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                  5519798084                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.159679                       # CPI: cycles per instruction
system.cpu0.ipc                              0.463032                       # IPC: instructions per cycle
system.cpu0.op_class_0::No_OpClass               2315      0.00%      0.00% # Class of committed instruction
system.cpu0.op_class_0::IntAlu               65610842     66.33%     66.33% # Class of committed instruction
system.cpu0.op_class_0::IntMult                 94061      0.10%     66.43% # Class of committed instruction
system.cpu0.op_class_0::IntDiv                      0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::FloatAdd                    0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::FloatCmp                    0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::FloatCvt                    0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::FloatMult                   0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::FloatMultAcc                0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::FloatDiv                    0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::FloatMisc                   0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::FloatSqrt                   0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdAdd                     0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdAddAcc                  0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdAlu                     0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdCmp                     0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdCvt                     0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdMisc                    0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdMult                    0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdMultAcc                 0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdShift                   0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdShiftAcc                0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdSqrt                    0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAdd                0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAlu                0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCmp                0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCvt                0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatDiv                0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMisc            8175      0.01%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMult               0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMultAcc            0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatSqrt               0      0.00%     66.43% # Class of committed instruction
system.cpu0.op_class_0::MemRead              17407324     17.60%     84.03% # Class of committed instruction
system.cpu0.op_class_0::MemWrite             15784753     15.96%     99.99% # Class of committed instruction
system.cpu0.op_class_0::FloatMemRead             2708      0.00%     99.99% # Class of committed instruction
system.cpu0.op_class_0::FloatMemWrite            8588      0.01%    100.00% # Class of committed instruction
system.cpu0.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
system.cpu0.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
system.cpu0.op_class_0::total                98918766                       # Class of committed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1854                       # number of quiesce instructions executed
system.cpu0.tickCycles                      124478065                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                       52949063                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements           756000                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          495.989536                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           31503611                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           756512                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            41.643240                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        356904000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   495.989536                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.968730                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.968730                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          355                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           44                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         66089687                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        66089687                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     16428136                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       16428136                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     13890443                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      13890443                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       328324                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       328324                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       374119                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       374119                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       370195                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       370195                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     30318579                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        30318579                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     30646903                       # number of overall hits
system.cpu0.dcache.overall_hits::total       30646903                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       460755                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       460755                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       603639                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       603639                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       141924                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       141924                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21489                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21489                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20512                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        20512                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1064394                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1064394                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1206318                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1206318                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6676359500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   6676359500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  11544866500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  11544866500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    336675500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    336675500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    485473000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    485473000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       539500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       539500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  18221226000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  18221226000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  18221226000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  18221226000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     16888891                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     16888891                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     14494082                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     14494082                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       470248                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       470248                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       395608                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       395608                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       390707                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       390707                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     31382973                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     31382973                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     31853221                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     31853221                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.027282                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.027282                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.041647                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.041647                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.301807                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.301807                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054319                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054319                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052500                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052500                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.033916                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.033916                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.037871                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.037871                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14490.042430                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14490.042430                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19125.448323                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19125.448323                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15667.341430                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15667.341430                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23667.755460                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23667.755460                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17118.873274                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 17118.873274                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15104.828080                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 15104.828080                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       756000                       # number of writebacks
system.cpu0.dcache.writebacks::total           756000                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        45822                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        45822                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       266133                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       266133                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14947                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14947                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data       311955                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       311955                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data       311955                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       311955                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       414933                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       414933                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       337506                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       337506                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       108299                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       108299                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6542                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6542                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20512                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        20512                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       752439                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       752439                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       860738                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       860738                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20603                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20603                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19302                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19302                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        39905                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        39905                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5470255000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5470255000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6299771000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6299771000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1751643500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1751643500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    104376500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    104376500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    464977000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    464977000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       523500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       523500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  11770026000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  11770026000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13521669500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  13521669500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4611679000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4611679000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4611679000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4611679000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024568                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024568                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023286                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023286                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.230302                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.230302                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016537                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016537                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052500                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052500                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023976                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.023976                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027022                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.027022                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13183.465764                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13183.465764                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18665.656314                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18665.656314                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16174.142882                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16174.142882                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15954.830327                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15954.830327                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22668.535491                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22668.535491                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15642.498595                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15642.498595                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15709.390662                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15709.390662                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223835.315245                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223835.315245                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115566.445308                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115566.445308                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          2036864                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.774783                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           37707013                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          2037376                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            18.507636                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6575306000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.774783                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999560                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999560                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          258                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           98                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         81526207                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        81526207                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst     37707013                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       37707013                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     37707013                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        37707013                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     37707013                       # number of overall hits
system.cpu0.icache.overall_hits::total       37707013                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      2037394                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2037394                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      2037394                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2037394                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      2037394                       # number of overall misses
system.cpu0.icache.overall_misses::total      2037394                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  20429568000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  20429568000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  20429568000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  20429568000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  20429568000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  20429568000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     39744407                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     39744407                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     39744407                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     39744407                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     39744407                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     39744407                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.051262                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.051262                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.051262                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.051262                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.051262                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.051262                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10027.303506                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10027.303506                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10027.303506                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10027.303506                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10027.303506                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10027.303506                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      2036864                       # number of writebacks
system.cpu0.icache.writebacks::total          2036864                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      2037394                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      2037394                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      2037394                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      2037394                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      2037394                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      2037394                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3277                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         3277                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3277                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         3277                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  19410871500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  19410871500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  19410871500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  19410871500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  19410871500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  19410871500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    323882000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    323882000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    323882000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    323882000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.051262                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.051262                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.051262                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.051262                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.051262                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.051262                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9527.303752                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9527.303752                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9527.303752                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  9527.303752                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9527.303752                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  9527.303752                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98834.909979                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98834.909979                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1927829                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1927948                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit          103                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       243748                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements          297127                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       15638.814401                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           2702273                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          312734                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            8.640803                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14568.839087                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    61.655947                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.055478                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1008.263889                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.889211                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003763                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000003                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.061540                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.954517                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022          252                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           10                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15345                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            6                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           32                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          142                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           72                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          251                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1191                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         7256                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5870                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          777                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.015381                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000610                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.936584                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        95152070                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       95152070                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        82993                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         5634                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         88627                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks       506169                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total       506169                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      2242578                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      2242578                       # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       235126                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       235126                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1941946                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1941946                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       414577                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       414577                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        82993                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         5634                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1941946                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       649703                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        2680276                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        82993                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         5634                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1941946                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       649703                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       2680276                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          792                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker           89                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          881                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        56686                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        56686                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        20512                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        20512                       # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        45703                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        45703                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        95448                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        95448                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       115192                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       115192                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          792                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker           89                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        95448                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       160895                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       257224                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          792                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker           89                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        95448                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       160895                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       257224                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     39518000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2258000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total     41776000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data     46480500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total     46480500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     11233000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     11233000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       499500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       499500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2934504499                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2934504499                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   4610090000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   4610090000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3801275499                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3801275499                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     39518000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2258000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4610090000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   6735779998                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  11387645998                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     39518000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2258000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4610090000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   6735779998                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  11387645998                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        83785                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         5723                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        89508                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks       506169                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total       506169                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      2242578                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      2242578                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56686                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        56686                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20512                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        20512                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       280829                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       280829                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      2037394                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      2037394                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       529769                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       529769                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        83785                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         5723                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      2037394                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       810598                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2937500                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        83785                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         5723                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      2037394                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       810598                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2937500                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.009453                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.015551                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.009843                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.162743                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.162743                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.046848                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.046848                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.217438                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.217438                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.009453                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.015551                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.046848                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.198489                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.087566                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.009453                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.015551                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.046848                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.198489                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.087566                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 49896.464646                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 25370.786517                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 47418.842225                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data   819.964365                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total   819.964365                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data   547.630655                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total   547.630655                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64208.137300                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64208.137300                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 48299.492918                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 48299.492918                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32999.474781                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32999.474781                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 49896.464646                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 25370.786517                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 48299.492918                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41864.445744                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 44271.319931                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 49896.464646                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 25370.786517                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 48299.492918                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41864.445744                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 44271.319931                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs           32                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           32                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           10950                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks       237127                       # number of writebacks
system.cpu0.l2cache.writebacks::total          237127                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         3260                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         3260                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           60                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           60                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          437                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          437                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           60                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3697                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         3758                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            1                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           60                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         3697                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         3758                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          791                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker           89                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          880                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       267610                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       267610                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        56686                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        56686                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20512                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20512                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        42443                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        42443                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        95388                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        95388                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       114755                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       114755                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          791                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker           89                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        95388                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       157198                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       253466                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          791                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker           89                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        95388                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       157198                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       267610                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       521076                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3277                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20603                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        23880                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        19302                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        19302                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3277                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        39905                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        43182                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     34749000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1724000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     36473000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  17027732697                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  17027732697                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    983576499                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    983576499                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    310242000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    310242000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       403500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       403500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2182275999                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2182275999                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   4035832000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   4035832000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   3088712499                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   3088712499                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     34749000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1724000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   4035832000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5270988498                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   9343293498                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     34749000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1724000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   4035832000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5270988498                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  17027732697                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  26371026195                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    297666000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4446739000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4744405000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    297666000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4446739000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   4744405000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009441                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.015551                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.009832                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.151135                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.151135                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.046819                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.046819                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.216613                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.216613                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009441                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.015551                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.046819                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.193928                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.086286                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009441                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.015551                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.046819                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.193928                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.177388                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 41446.590909                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63628.910343                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63628.910343                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17351.312476                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17351.312476                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15124.902496                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15124.902496                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 51416.629338                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 51416.629338                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42309.640626                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42309.640626                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26915.711725                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26915.711725                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42309.640626                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33530.887785                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36862.117594                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42309.640626                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33530.887785                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63628.910343                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50608.790647                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215829.684997                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198676.926298                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111433.128681                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109869.968969                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests      5741859                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2893899                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        44137                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       221175                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       217002                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4173                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq        125397                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      2741625                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        19302                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        19302                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty       743607                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      2286693                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict       110010                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       316910                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        86864                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42906                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       113874                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           15                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           31                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       299874                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       296474                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      2037394                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       616815                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3112                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp           13                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      6118205                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2712873                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        14034                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       176949                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          9022061                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    260962176                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    104517534                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        22892                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       335140                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         365837742                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     939630                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic             19388808                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples      3896038                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.075284                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.267877                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           3606903     92.58%     92.58% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            284962      7.31%     99.89% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2              4173      0.11%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       3896038                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    5733869996                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    115563972                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   3061282943                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1285797933                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      8314992                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     93182962                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups               18647514                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          5782822                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           870887                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             9511803                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                3428026                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            36.039708                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                8548256                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            712976                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        3551521                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           3498978                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses           52543                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted        17984                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                    22971                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               22971                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19558                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         3413                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples        22971                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0          22971    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        22971                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         1848                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 12803.300866                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11525.814953                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 15800.491207                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535         1844     99.78%     99.78% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071            3      0.16%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.05%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         1848                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -1978443032                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1978443032    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -1978443032                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1308     70.78%     70.78% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          540     29.22%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         1848                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        22971                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        22971                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1848                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1848                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        24819                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    10530339                       # DTB read hits
system.cpu1.dtb.read_misses                     20830                       # DTB read misses
system.cpu1.dtb.write_hits                    6472980                       # DTB write hits
system.cpu1.dtb.write_misses                     2141                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1623                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      116                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   297                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      184                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                10551169                       # DTB read accesses
system.cpu1.dtb.write_accesses                6475121                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         17003319                       # DTB hits
system.cpu1.dtb.misses                          22971                       # DTB misses
system.cpu1.dtb.accesses                     17026290                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                     2051                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                2051                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          145                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1906                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         2051                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           2051    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         2051                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples          830                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12046.987952                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11480.071390                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  4509.628818                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          126     15.18%     15.18% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          555     66.87%     82.05% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383           85     10.24%     92.29% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479           14      1.69%     93.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575           22      2.65%     96.63% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           18      2.17%     98.80% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767            6      0.72%     99.52% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863            1      0.12%     99.64% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            3      0.36%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total          830                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1979056532                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1979056532    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1979056532                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          695     83.73%     83.73% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          135     16.27%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total          830                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2051                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2051                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          830                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total          830                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         2881                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    38623354                       # ITB inst hits
system.cpu1.itb.inst_misses                      2051                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                     830                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1040                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                38625405                       # ITB inst accesses
system.cpu1.itb.hits                         38623354                       # DTB hits
system.cpu1.itb.misses                           2051                       # DTB misses
system.cpu1.itb.accesses                     38625405                       # DTB accesses
system.cpu1.numPwrStateTransitions               5477                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         2739                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    1019571073.706097                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   25827442882.959442                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         1941     70.87%     70.87% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10          794     28.99%     99.85% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            1      0.04%     99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.04%     99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11            1      0.04%     99.96% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11            1      0.04%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 949980394548                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           2739                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON    55993511619                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 2792605170881                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                       111990488                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   45059059                       # Number of instructions committed
system.cpu1.committedOps                     55122963                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                      4849343                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     2739                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                  5584538446                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.485416                       # CPI: cycles per instruction
system.cpu1.ipc                              0.402347                       # IPC: instructions per cycle
system.cpu1.op_class_0::No_OpClass                 24      0.00%      0.00% # Class of committed instruction
system.cpu1.op_class_0::IntAlu               38107074     69.13%     69.13% # Class of committed instruction
system.cpu1.op_class_0::IntMult                 43629      0.08%     69.21% # Class of committed instruction
system.cpu1.op_class_0::IntDiv                      0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::FloatAdd                    0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::FloatCmp                    0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::FloatCvt                    0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::FloatMult                   0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::FloatMultAcc                0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::FloatDiv                    0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::FloatMisc                   0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::FloatSqrt                   0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdAdd                     0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdAddAcc                  0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdAlu                     0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdCmp                     0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdCvt                     0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdMisc                    0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdMult                    0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdMultAcc                 0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdShift                   0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdShiftAcc                0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdSqrt                    0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAdd                0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAlu                0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCmp                0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCvt                0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatDiv                0      0.00%     69.21% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMisc            3226      0.01%     69.22% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMult               0      0.00%     69.22% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMultAcc            0      0.00%     69.22% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatSqrt               0      0.00%     69.22% # Class of committed instruction
system.cpu1.op_class_0::MemRead              10387367     18.84%     88.06% # Class of committed instruction
system.cpu1.op_class_0::MemWrite              6581643     11.94%    100.00% # Class of committed instruction
system.cpu1.op_class_0::FloatMemRead                0      0.00%    100.00% # Class of committed instruction
system.cpu1.op_class_0::FloatMemWrite               0      0.00%    100.00% # Class of committed instruction
system.cpu1.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
system.cpu1.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
system.cpu1.op_class_0::total                55122963                       # Class of committed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2739                       # number of quiesce instructions executed
system.cpu1.tickCycles                       90184958                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                       21805530                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements           157661                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          475.726390                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           16648746                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           158020                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs           105.358474                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      91198641000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   475.726390                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.929153                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.929153                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          359                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          284                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           75                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.701172                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         34039754                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        34039754                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data     10204486                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       10204486                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      6223411                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       6223411                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        43300                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        43300                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        71256                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        71256                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        62645                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        62645                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     16427897                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        16427897                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     16471197                       # number of overall hits
system.cpu1.dcache.overall_hits::total       16471197                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       127390                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       127390                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       122263                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       122263                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        24165                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        24165                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16525                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        16525                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23356                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23356                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       249653                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        249653                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       273818                       # number of overall misses
system.cpu1.dcache.overall_misses::total       273818                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2191208500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2191208500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   3801376500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   3801376500                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    322530000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    322530000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    548226000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    548226000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       650000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total       650000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   5992585000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   5992585000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   5992585000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   5992585000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     10331876                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     10331876                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      6345674                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      6345674                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        67465                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        67465                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        87781                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        87781                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        86001                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        86001                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     16677550                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     16677550                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     16745015                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     16745015                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.012330                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.012330                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.019267                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.019267                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.358186                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.358186                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.188253                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.188253                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.271578                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.271578                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.014969                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.014969                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.016352                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.016352                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17200.788916                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 17200.788916                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31091.798009                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 31091.798009                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19517.700454                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19517.700454                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23472.598048                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23472.598048                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24003.657076                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 24003.657076                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21885.285116                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 21885.285116                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks       157661                       # number of writebacks
system.cpu1.dcache.writebacks::total           157661                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data         4447                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total         4447                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        42267                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total        42267                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11747                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11747                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        46714                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        46714                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        46714                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        46714                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       122943                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       122943                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        79996                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        79996                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23657                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        23657                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4778                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4778                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23356                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23356                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       202939                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       202939                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       226596                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       226596                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        14406                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        14406                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11728                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11728                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        26134                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        26134                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1987288500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1987288500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2305734500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2305734500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    418963500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    418963500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     86008500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     86008500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    524885000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    524885000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       635000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       635000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4293023000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4293023000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4711986500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4711986500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2490253500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2490253500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2490253500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2490253500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.011899                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.011899                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.012606                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.012606                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.350656                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.350656                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.054431                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.054431                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.271578                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.271578                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.012168                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.012168                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.013532                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.013532                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16164.307850                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16164.307850                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28823.122406                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28823.122406                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17709.916727                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17709.916727                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18000.941817                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18000.941817                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22473.240281                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22473.240281                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21154.253249                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21154.253249                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20794.658776                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20794.658776                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172862.244898                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172862.244898                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95287.881687                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95287.881687                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements           872875                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.208474                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           37748872                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           873387                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            43.221243                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      72896771000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.208474                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975017                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975017                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          463                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           48                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         78117905                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        78117905                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst     37748872                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       37748872                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     37748872                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        37748872                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     37748872                       # number of overall hits
system.cpu1.icache.overall_hits::total       37748872                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       873387                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       873387                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       873387                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        873387                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       873387                       # number of overall misses
system.cpu1.icache.overall_misses::total       873387                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8011666500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   8011666500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   8011666500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   8011666500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   8011666500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   8011666500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     38622259                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     38622259                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     38622259                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     38622259                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     38622259                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     38622259                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.022614                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.022614                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.022614                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.022614                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.022614                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.022614                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9173.100241                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  9173.100241                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9173.100241                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  9173.100241                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9173.100241                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  9173.100241                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks       872875                       # number of writebacks
system.cpu1.icache.writebacks::total           872875                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       873387                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       873387                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       873387                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       873387                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       873387                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       873387                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7574973000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7574973000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7574973000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7574973000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7574973000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7574973000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     11042500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     11042500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     11042500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     11042500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.022614                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.022614                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.022614                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.022614                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.022614                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.022614                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8673.100241                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8673.100241                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8673.100241                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8673.100241                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8673.100241                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8673.100241                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98593.750000                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 98593.750000                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98593.750000                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 98593.750000                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued       118852                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       118852                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        49172                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements           37377                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       14753.834184                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs            946442                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           52088                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           18.170058                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14422.597482                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    42.225036                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     1.137350                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   287.874316                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.880285                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002577                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000069                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.017570                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.900503                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          261                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           78                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14372                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            3                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           24                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          234                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            9                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           53                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         1285                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2929                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        10158                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.015930                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004761                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.877197                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        35693220                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       35693220                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        23446                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2580                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total         26026                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks        95283                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total        95283                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks       916386                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total       916386                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        18220                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        18220                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       844850                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       844850                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        81639                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total        81639                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        23446                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2580                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       844850                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data        99859                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         970735                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        23446                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2580                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       844850                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data        99859                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        970735                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          823                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          297                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total         1120                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29230                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        29230                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23356                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        23356                       # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32546                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        32546                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        28537                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        28537                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        69739                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        69739                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          823                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          297                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        28537                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       102285                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       131942                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          823                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          297                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        28537                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       102285                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       131942                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     21253500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5882500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     27136000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data      7496000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total      7496000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     16835000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     16835000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       611000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       611000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1439672500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1439672500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst   1146878000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total   1146878000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1720708495                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1720708495                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     21253500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5882500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst   1146878000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3160380995                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   4334394995                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     21253500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5882500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst   1146878000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3160380995                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   4334394995                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        24269                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2877                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total        27146                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks        95283                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total        95283                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks       916386                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total       916386                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29230                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29230                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23356                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23356                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        50766                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        50766                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       873387                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       873387                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       151378                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       151378                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        24269                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2877                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       873387                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       202144                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      1102677                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        24269                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2877                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       873387                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       202144                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      1102677                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.033912                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.103233                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.041258                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.641098                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.641098                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.032674                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.032674                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.460694                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.460694                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.033912                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.103233                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.032674                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.506001                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.119656                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.033912                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.103233                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.032674                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.506001                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.119656                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25824.422843                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19806.397306                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24228.571429                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data   256.448854                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total   256.448854                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data   720.799794                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total   720.799794                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44235.005838                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44235.005838                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40189.157935                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40189.157935                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 24673.547011                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 24673.547011                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25824.422843                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19806.397306                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40189.157935                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30897.795327                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 32850.760145                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25824.422843                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19806.397306                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40189.157935                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30897.795327                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 32850.760145                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches             596                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks        29159                       # number of writebacks
system.cpu1.l2cache.writebacks::total           29159                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            3                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            3                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          174                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          174                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            5                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           44                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           44                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            3                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            3                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            5                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          218                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          229                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            3                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            3                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            5                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          218                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          229                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          820                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          294                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total         1114                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        19637                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        19637                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29230                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29230                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23356                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23356                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        32372                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        32372                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        28532                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        28532                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        69695                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        69695                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          820                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          294                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        28532                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       102067                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       131713                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          820                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          294                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        28532                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       102067                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        19637                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       151350                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        14406                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        14518                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11728                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11728                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        26134                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        26246                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     16302000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4074000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     20376000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    732946008                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    732946008                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    445433500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    445433500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    348598000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    348598000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       521000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       521000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1224744500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1224744500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    975419000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    975419000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1300674995                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1300674995                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     16302000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4074000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    975419000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2525419495                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   3521214495                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     16302000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4074000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    975419000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2525419495                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    732946008                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   4254160503                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10146500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2374983500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2385130000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     10146500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2374983500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2385130000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.033788                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.102190                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.041037                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.637671                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.637671                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.032668                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.032668                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.460404                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.460404                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.033788                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.102190                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.032668                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.504922                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.119448                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.033788                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.102190                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.032668                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.504922                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.137257                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18290.843806                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37324.744513                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37324.744513                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15238.915498                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15238.915498                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14925.415311                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14925.415311                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37833.451748                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37833.451748                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34186.842843                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34186.842843                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18662.386039                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18662.386039                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34186.842843                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24742.762058                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26733.993569                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34186.842843                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24742.762058                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37324.744513                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28108.097146                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90593.750000                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164860.717756                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164287.780686                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90593.750000                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90877.152369                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90875.943001                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests      2165902                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1090398                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        18866                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       115909                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       108045                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         7864                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq         44859                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      1106447                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        11728                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        11728                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty       126621                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean       935252                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict        26571                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        23763                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        71775                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41777                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        84685                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           16                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           31                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        58060                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        55427                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       873387                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       263309                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq           71                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      2619873                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       793002                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6834                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        50653                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          3470362                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    111767936                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25786238                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        11508                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        97076                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         137662758                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     338759                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic              4674348                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples      1446654                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.103615                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.322104                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0           1304623     90.18%     90.18% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            134167      9.27%     99.46% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2              7864      0.54%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1446654                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    2144021494                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     78336814                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   1310300396                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    351676729                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      3959994                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     26397473                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                31009                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31009                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59424                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59424                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56618                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107932                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180866                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71562                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162812                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2483988                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             48425501                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               110500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               324500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                28500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                12500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                88500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               621000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               19500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               47500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6370500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            39055001                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187730317                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84732000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36758000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36449                       # number of replacements
system.iocache.tags.tagsinuse               14.472713                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36465                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         271902155000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.472713                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.904545                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.904545                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328203                       # Number of tag accesses
system.iocache.tags.data_accesses              328203                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide          243                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36467                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36467                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36467                       # number of overall misses
system.iocache.overall_misses::total            36467                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     32482877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     32482877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4347292440                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4347292440                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4379775317                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4379775317                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4379775317                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4379775317                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36467                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36467                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36467                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36467                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 133674.390947                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 133674.390947                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120011.385822                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120011.385822                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 120102.430060                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 120102.430060                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 120102.430060                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 120102.430060                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             7                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     3.500000                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36206                       # number of writebacks
system.iocache.writebacks::total                36206                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36467                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36467                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36467                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36467                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     20332877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     20332877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2534226880                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2534226880                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2554559757                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2554559757                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2554559757                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2554559757                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 83674.390947                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 83674.390947                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69959.885159                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69959.885159                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 70051.272575                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70051.272575                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70051.272575                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70051.272575                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                   143599                       # number of replacements
system.l2c.tags.tagsinuse                65154.346859                       # Cycle average of tags in use
system.l2c.tags.total_refs                     605481                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   209069                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.896082                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              94462980000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks    6720.710891                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    87.363500                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.029896                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     8711.779777                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     6725.180439                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34970.113845                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    14.660518                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2224.966255                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     3446.409233                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2253.132505                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.102550                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001333                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.132931                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.102618                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.533602                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000224                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.033950                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.052588                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.034380                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.994176                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        32778                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           59                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        32633                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          137                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         5072                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        27569                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           59                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          123                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         1691                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        30817                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.500153                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000900                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.497940                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6803015                       # Number of tag accesses
system.l2c.tags.data_accesses                 6803015                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks       266286                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          266286                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           43645                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            4461                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               48106                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          3017                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          2129                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              5146                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4448                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1231                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5679                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          477                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           86                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        72650                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        65777                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        48761                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           80                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker            9                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst        24965                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data         8445                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         3652                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           224902                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker           477                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            86                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               72650                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               70225                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        48761                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            80                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker             9                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               24965                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                9676                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         3652                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  230581                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          477                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           86                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              72650                       # number of overall hits
system.l2c.overall_hits::cpu0.data              70225                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        48761                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           80                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker            9                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              24965                       # number of overall hits
system.l2c.overall_hits::cpu1.data               9676                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         3652                       # number of overall hits
system.l2c.overall_hits::total                 230581                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data           459                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           178                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total               637                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           57                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           62                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             119                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11423                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8564                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19987                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          145                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        22738                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         9967                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       134498                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker           20                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         3567                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         1751                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         5084                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         177771                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker          145                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             22738                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             21390                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       134498                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           20                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              3567                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             10315                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         5084                       # number of demand (read+write) misses
system.l2c.demand_misses::total                197758                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker          145                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            22738                       # number of overall misses
system.l2c.overall_misses::cpu0.data            21390                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       134498                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           20                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             3567                       # number of overall misses
system.l2c.overall_misses::cpu1.data            10315                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         5084                       # number of overall misses
system.l2c.overall_misses::total               197758                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data      8555500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       760000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      9315500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       567000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       122000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       689000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1593574000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    815318500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2408892500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     22107500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker        90000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   2317227000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1217018500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  16177990963                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker      4552500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    377306500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    262293500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    655902831                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  21034489294                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker     22107500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        90000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   2317227000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   2810592500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  16177990963                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      4552500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    377306500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1077612000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    655902831                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     23443381794                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker     22107500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        90000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   2317227000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   2810592500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  16177990963                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      4552500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    377306500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1077612000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    655902831                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    23443381794                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       266286                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       266286                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        44104                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4639                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           48743                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         3074                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         2191                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          5265                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15871                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         9795                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            25666                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          622                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           87                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        95388                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        75744                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       183259                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker          100                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker            9                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        28532                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        10196                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher         8736                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       402673                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          622                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           87                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           95388                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           91615                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       183259                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker          100                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker            9                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           28532                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           19991                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher         8736                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              428339                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          622                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           87                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          95388                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          91615                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       183259                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker          100                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker            9                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          28532                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          19991                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher         8736                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             428339                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.010407                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.038370                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.013069                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.018543                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.028298                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.022602                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.719740                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.874324                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.778735                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.233119                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.011494                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.238374                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.131588                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.733923                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.200000                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.125018                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.171734                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.581960                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.441477                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.233119                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.011494                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.238374                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.233477                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.733923                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.200000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.125018                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.515982                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.581960                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.461686                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.233119                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.011494                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.238374                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.233477                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.733923                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.200000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.125018                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.515982                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.581960                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.461686                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 18639.433551                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4269.662921                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 14624.018838                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  9947.368421                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1967.741935                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  5789.915966                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139505.734045                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 95203.000934                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 120522.964927                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 152465.517241                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        90000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 101909.886534                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 122104.795826                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 120284.249305                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker       227625                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 105776.983459                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 149796.402056                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 129013.145358                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 118323.513363                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 152465.517241                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        90000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 101909.886534                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 131397.498831                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 120284.249305                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       227625                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 105776.983459                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 104470.382937                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 129013.145358                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 118545.807472                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 152465.517241                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        90000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 101909.886534                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 131397.498831                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 120284.249305                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       227625                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 105776.983459                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 104470.382937                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 129013.145358                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 118545.807472                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks              104081                       # number of writebacks
system.l2c.writebacks::total                   104081                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            5                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            1                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total            6                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  6                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 6                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         4309                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         4309                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data          459                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          178                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total          637                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           57                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           62                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          119                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11423                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8564                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19987                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          145                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        22733                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9967                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       134498                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker           20                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         3566                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         1751                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         5084                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       177765                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker          145                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        22733                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        21390                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       134498                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           20                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         3566                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        10315                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         5084                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           197752                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker          145                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        22733                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        21390                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       134498                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           20                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         3566                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        10315                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         5084                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          197752                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3277                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        20603                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        14403                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        38395                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        19302                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11728                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        31030                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3277                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        39905                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26131                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        69425                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     10236500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      3909500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     14146000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      1509500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      1453000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      2962500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1479344000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    729678500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2209022500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker     20657500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker        80000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   2089156001                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1117348500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14833007471                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker      4352500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    341582500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    244783001                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    605061833                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  19256029306                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     20657500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        80000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   2089156001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2596692500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  14833007471                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      4352500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    341582500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    974461501                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    605061833                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  21465051806                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     20657500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        80000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   2089156001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2596692500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  14833007471                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      4352500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    341582500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    974461501                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    605061833                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  21465051806                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    228848500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4075847000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7794500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2115657500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6428147500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    228848500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4075847000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7794500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2115657500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   6428147500                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.010407                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.038370                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.013069                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.018543                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.028298                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.022602                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.719740                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.874324                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.778735                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.233119                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.011494                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.238321                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.131588                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.733923                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.200000                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.124982                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.171734                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.581960                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.441462                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.233119                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011494                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.238321                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.233477                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.733923                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.200000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.124982                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.515982                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.581960                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.461672                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.233119                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011494                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.238321                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.233477                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.733923                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.200000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.124982                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.515982                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.581960                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.461672                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22301.742919                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21963.483146                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22207.221350                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26482.456140                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23435.483871                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24894.957983                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129505.734045                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 85203.000934                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 110522.964927                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker        80000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 91899.705318                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 112104.795826                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker       217625                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 95788.698822                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 139796.117076                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108322.950558                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        80000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 91899.705318                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121397.498831                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker       217625                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 95788.698822                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94470.334561                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 108545.308295                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        80000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 91899.705318                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121397.498831                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker       217625                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 95788.698822                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94470.334561                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 108545.308295                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197827.840606                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69593.750000                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146890.057627                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167421.474150                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102138.754542                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69593.750000                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80963.510773                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 92591.249550                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        513996                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       285885                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          629                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               38395                       # Transaction distribution
system.membus.trans_dist::ReadResp             216403                       # Transaction distribution
system.membus.trans_dist::WriteReq              31030                       # Transaction distribution
system.membus.trans_dist::WriteResp             31030                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       140287                       # Transaction distribution
system.membus.trans_dist::CleanEvict            19048                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            61128                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          38691                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq             40497                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19965                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        178008                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp         4238                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107932                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           42                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14192                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       655043                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       777209                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72931                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72931                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 850140                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162812                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1344                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28384                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19529832                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     19722372                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                22040516                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           124379                       # Total snoops (count)
system.membus.snoopTraffic                      36224                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            423974                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.011487                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.106558                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  419104     98.85%     98.85% # Request fanout histogram
system.membus.snoop_fanout::1                    4870      1.15%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              423974                       # Request fanout histogram
system.membus.reqLayer0.occupancy            95170998                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               23328                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            12519499                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1006886251                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1152568025                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            6725047                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests      1101165                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       567136                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       209084                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          30878                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        29463                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops         1415                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              38398                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            558656                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             31030                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            31030                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       370367                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          149733                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          109212                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         43837                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         153049                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           31                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           31                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            51538                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           51538                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       520262                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq         4298                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp         3081                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1372035                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       353597                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1725632                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     39251474                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5647218                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               44898692                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          393768                       # Total snoops (count)
system.toL2Bus.snoopTraffic                  15844428                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples           942231                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.393753                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.491645                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 572640     60.77%     60.77% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 368176     39.07%     99.85% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                   1415      0.15%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             942231                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          939495440                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1962409                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         733983819                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         257943151                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------