path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.848979                       # Number of seconds simulated
sim_ticks                                2848979128500                       # Number of ticks simulated
final_tick                               2848979128500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 154282                       # Simulator instruction rate (inst/s)
host_op_rate                                   186830                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3456392917                       # Simulator tick rate (ticks/s)
host_mem_usage                                 618280                       # Number of bytes of host memory used
host_seconds                                   824.26                       # Real time elapsed on the host
sim_insts                                   127169330                       # Number of instructions simulated
sim_ops                                     153997543                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         8448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1698560                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1348800                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8516160                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          640                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           208256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           632788                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       357568                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12772244                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1698560                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       208256                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1906816                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8849024                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8866588                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker          132                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             26540                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             21601                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       133065                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           10                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              3254                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              9908                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         5587                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                200113                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          138266                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               142657                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2965                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              596200                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              473433                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2989197                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           225                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               73098                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              222110                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       125507                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4483095                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         596200                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          73098                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             669298                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3106033                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6151                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3112198                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3106033                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2965                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             596200                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             479584                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2989197                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          225                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              73098                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             222124                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       125507                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7595293                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        200113                       # Number of read requests accepted
system.physmem.writeReqs                       142657                       # Number of write requests accepted
system.physmem.readBursts                      200113                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     142657                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12798592                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8640                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8879168                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12772244                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8866588                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      135                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3895                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          69084                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12287                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12592                       # Per bank write bursts
system.physmem.perBankRdBursts::2               13485                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12796                       # Per bank write bursts
system.physmem.perBankRdBursts::4               15663                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12764                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12615                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12815                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11998                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12140                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11596                       # Per bank write bursts
system.physmem.perBankRdBursts::11              10685                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11914                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12844                       # Per bank write bursts
system.physmem.perBankRdBursts::14              12075                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11709                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8805                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9189                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9797                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9112                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8303                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8892                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8866                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8915                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8401                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8590                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8283                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7752                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8566                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8822                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8545                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7899                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          18                       # Number of times write queue was full causing retry
system.physmem.totGap                    2848978583000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     557                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  199528                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 138266                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     88817                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     60985                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     11790                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9494                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7806                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      6286                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5183                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4625                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3738                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       641                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      202                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      157                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      136                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      113                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2866                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4614                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4983                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5998                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6540                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7779                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7940                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8957                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     9084                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9291                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10972                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9095                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9017                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8688                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7869                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7517                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      557                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      414                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      154                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       74                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       39                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       61                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        92122                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      235.314387                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     133.718922                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     297.822907                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          49981     54.26%     54.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17852     19.38%     73.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6274      6.81%     80.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3559      3.86%     84.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2993      3.25%     87.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1358      1.47%     89.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          900      0.98%     90.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          994      1.08%     91.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8211      8.91%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          92122                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6829                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        29.283204                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      564.566486                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6828     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6829                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6829                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.315859                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.777431                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.379766                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5626     82.38%     82.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             466      6.82%     89.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              97      1.42%     90.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             149      2.18%     92.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              29      0.42%     93.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             128      1.87%     95.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              35      0.51%     95.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              17      0.25%     95.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              25      0.37%     96.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              23      0.34%     96.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               7      0.10%     96.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               8      0.12%     96.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             138      2.02%     98.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               8      0.12%     98.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.06%     98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              26      0.38%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               6      0.09%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               4      0.06%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.01%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.01%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             2      0.03%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.01%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.01%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             2      0.03%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.03%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            14      0.21%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.01%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             3      0.04%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.03%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6829                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5270639949                       # Total ticks spent queuing
system.physmem.totMemAccLat                9020227449                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    999890000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       26356.10                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  45106.10                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.49                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.12                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.48                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.11                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.71                       # Average write queue length when enqueuing
system.physmem.readRowHits                     166028                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     80563                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.02                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  58.06                       # Row buffer hit rate for writes
system.physmem.avgGap                      8311633.41                       # Average gap between requests
system.physmem.pageHitRate                      72.80                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  367945200                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  200763750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 819124800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                465775920                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           186081086880                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            85063480605                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1634767041000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1907765218155                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.632478                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2719452348147                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95133480000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     34391644853                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  328497120                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  179239500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 740688000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                433239840                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           186081086880                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            83753939520                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1635915761250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1907432452110                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.515676                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2721369982715                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95133480000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     32475502785                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          832                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1344                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          832                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1344                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           13                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             21                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          180                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          292                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              472                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          180                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          292                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          472                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          180                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          292                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             472                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               36411615                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         17748077                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          1698439                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            20740706                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               15063288                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            72.626689                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               11337600                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            822333                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    73296                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               73296                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        47393                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        25903                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples        73296                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0          73296    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        73296                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         7538                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12243.300610                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11373.544979                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  7165.218707                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767         7499     99.48%     99.48% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535           33      0.44%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839            4      0.05%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::163840-196607            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-425983            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         7538                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    581987000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      581987000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    581987000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5846     77.55%     77.55% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1692     22.45%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         7538                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        73296                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        73296                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7538                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7538                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        80834                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    24914388                       # DTB read hits
system.cpu0.dtb.read_misses                     66763                       # DTB read misses
system.cpu0.dtb.write_hits                   18539888                       # DTB write hits
system.cpu0.dtb.write_misses                     6533                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3822                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1461                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  2016                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      633                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                24981151                       # DTB read accesses
system.cpu0.dtb.write_accesses               18546421                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         43454276                       # DTB hits
system.cpu0.dtb.misses                          73296                       # DTB misses
system.cpu0.dtb.accesses                     43527572                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     4166                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                4166                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          324                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3842                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         4166                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           4166    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         4166                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2675                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12725.794393                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 12032.430474                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  5005.050560                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-16383         2427     90.73%     90.73% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-32767          233      8.71%     99.44% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-49151           14      0.52%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2675                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    581277500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      581277500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    581277500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2356     88.07%     88.07% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          319     11.93%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2675                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         4166                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         4166                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2675                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2675                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         6841                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    71495102                       # ITB inst hits
system.cpu0.itb.inst_misses                      4166                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2450                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     8197                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                71499268                       # ITB inst accesses
system.cpu0.itb.hits                         71495102                       # DTB hits
system.cpu0.itb.misses                           4166                       # DTB misses
system.cpu0.itb.accesses                     71499268                       # DTB accesses
system.cpu0.numCycles                       248928104                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  113059938                       # Number of instructions committed
system.cpu0.committedOps                    136701894                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                      8937139                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     1889                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                  5449058014                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.201736                       # CPI: cycles per instruction
system.cpu0.ipc                              0.454187                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1892                       # number of quiesce instructions executed
system.cpu0.tickCycles                      199965513                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                       48962591                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements           758556                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          498.399366                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           41853464                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           759068                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            55.137964                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        600550000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   498.399366                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.973436                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.973436                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          141                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         86857605                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        86857605                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     23301250                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       23301250                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     17363998                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      17363998                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       329371                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       329371                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       374920                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       374920                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       370784                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       370784                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     40665248                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        40665248                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     40994619                       # number of overall hits
system.cpu0.dcache.overall_hits::total       40994619                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       492930                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       492930                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       604783                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       604783                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       142057                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       142057                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21393                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21393                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20582                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        20582                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1097713                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1097713                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1239770                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1239770                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6978123000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   6978123000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  12569253000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  12569253000                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    330022000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    330022000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    544680500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    544680500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       637500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       637500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  19547376000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  19547376000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  19547376000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  19547376000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     23794180                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     23794180                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     17968781                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     17968781                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       471428                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       471428                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       396313                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       396313                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       391366                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       391366                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     41762961                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     41762961                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     42234389                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     42234389                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.020716                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.020716                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.033657                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.033657                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.301333                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.301333                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.053980                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.053980                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052590                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052590                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026284                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.026284                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029355                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.029355                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14156.417747                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14156.417747                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20783.079220                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20783.079220                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15426.634881                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15426.634881                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26463.924789                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26463.924789                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17807.364949                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 17807.364949                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15766.937416                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 15766.937416                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       758556                       # number of writebacks
system.cpu0.dcache.writebacks::total           758556                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        75954                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        75954                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       266286                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       266286                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14845                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14845                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data       342240                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       342240                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data       342240                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       342240                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       416976                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       416976                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       338497                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       338497                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       108439                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       108439                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6548                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6548                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20582                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        20582                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       755473                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       755473                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       863912                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       863912                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32047                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32047                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28724                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28724                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60771                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60771                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5288189500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5288189500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7115551000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7115551000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1805226500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1805226500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    104756500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    104756500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    524110500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    524110500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       625500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       625500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12403740500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  12403740500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  14208967000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  14208967000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6702515500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6702515500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5452693000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5452693000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12155208500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12155208500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017524                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017524                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018838                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018838                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.230022                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.230022                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016522                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016522                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052590                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052590                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018090                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.018090                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020455                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.020455                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12682.239505                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12682.239505                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21021.016434                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21021.016434                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16647.391621                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16647.391621                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15998.243739                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15998.243739                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25464.507822                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25464.507822                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16418.509331                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16418.509331                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16447.238839                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16447.238839                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209146.425562                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209146.425562                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189830.559811                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189830.559811                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 200016.595086                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 200016.595086                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          2041160                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.728196                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           69444830                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          2041672                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            34.013705                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6975539000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.728196                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999469                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999469                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          172                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          246                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           94                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        145014717                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       145014717                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     69444830                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       69444830                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     69444830                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        69444830                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     69444830                       # number of overall hits
system.cpu0.icache.overall_hits::total       69444830                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      2041686                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2041686                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      2041686                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2041686                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      2041686                       # number of overall misses
system.cpu0.icache.overall_misses::total      2041686                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  20560339500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  20560339500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  20560339500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  20560339500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  20560339500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  20560339500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     71486516                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     71486516                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     71486516                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     71486516                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     71486516                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     71486516                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028560                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.028560                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028560                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.028560                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028560                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.028560                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10070.275008                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10070.275008                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10070.275008                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10070.275008                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10070.275008                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10070.275008                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks      2041160                       # number of writebacks
system.cpu0.icache.writebacks::total          2041160                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      2041686                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      2041686                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      2041686                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      2041686                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      2041686                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      2041686                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3917                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         3917                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3917                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         3917                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  19539497000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  19539497000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  19539497000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  19539497000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  19539497000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  19539497000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    557356500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    557356500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    557356500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    557356500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028560                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028560                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028560                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.028560                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028560                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.028560                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9570.275253                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9570.275253                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9570.275253                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  9570.275253                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9570.275253                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  9570.275253                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1926179                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1926371                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit          166                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       244645                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          305884                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16117.392846                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           4898605                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          322066                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs           15.209941                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14778.459491                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    60.434424                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.065090                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1278.433841                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.902006                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003689                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.078029                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.983728                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022          978                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           12                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15192                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           14                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          328                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          421                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          213                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            6                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           98                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          403                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4034                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         8338                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2319                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.059692                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000732                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.927246                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        93368748                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       93368748                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        90396                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         5742                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         96138                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks       507659                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total       507659                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      2247535                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      2247535                       # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       233006                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       233006                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1971438                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1971438                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       430811                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       430811                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        90396                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         5742                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1971438                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       663817                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        2731393                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        90396                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         5742                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1971438                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       663817                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       2731393                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          708                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker           94                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          802                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        57006                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        57006                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        20580                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        20580                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        48494                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        48494                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        70248                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        70248                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101145                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       101145                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          708                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker           94                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        70248                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       149639                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       220689                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          708                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker           94                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        70248                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       149639                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       220689                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     33565000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2328500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total     35893500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    209633000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    209633000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     49175500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     49175500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       605000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       605000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   3197349498                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   3197349498                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   4517158000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   4517158000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3550453498                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3550453498                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     33565000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2328500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4517158000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   6747802996                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  11300854496                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     33565000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2328500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4517158000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   6747802996                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  11300854496                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        91104                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         5836                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        96940                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks       507659                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total       507659                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      2247535                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      2247535                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        57006                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        57006                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20580                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        20580                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       281500                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       281500                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      2041686                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      2041686                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       531956                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       531956                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        91104                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         5836                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      2041686                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       813456                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2952082                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        91104                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         5836                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      2041686                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       813456                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2952082                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.007771                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.016107                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.008273                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.172270                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.172270                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.034407                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.034407                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.190138                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.190138                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.007771                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.016107                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.034407                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.183955                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.074757                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.007771                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.016107                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.034407                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.183955                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.074757                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47408.192090                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24771.276596                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44754.987531                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3677.384837                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3677.384837                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2389.480078                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2389.480078                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       302500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       302500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 65932.888564                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 65932.888564                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 64303.012185                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 64303.012185                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35102.610094                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35102.610094                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47408.192090                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24771.276596                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 64303.012185                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45093.879243                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 51207.148956                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47408.192090                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24771.276596                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 64303.012185                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45093.879243                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 51207.148956                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs          136                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               4                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       237808                       # number of writebacks
system.cpu0.l2cache.writebacks::total          237808                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5210                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         5210                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           69                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           69                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          569                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          569                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           69                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         5779                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         5848                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           69                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         5779                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         5848                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          708                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker           94                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          802                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       264185                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       264185                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        57006                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        57006                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20580                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20580                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        43284                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        43284                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        70179                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        70179                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       100576                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       100576                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          708                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker           94                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        70179                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       143860                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       214841                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          708                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker           94                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        70179                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       143860                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       264185                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       479026                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3917                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        32047                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        35964                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28724                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28724                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3917                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60771                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        64688                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     29317000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1764500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     31081500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  20868982731                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  20868982731                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1541137000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1541137000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    368989000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    368989000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       533000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       533000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2455445500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2455445500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   4093922000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   4093922000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2912555498                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2912555498                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     29317000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1764500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   4093922000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5368000998                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   9493004498                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     29317000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1764500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   4093922000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5368000998                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  20868982731                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  30361987229                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    526020000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6445976000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6971996000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5236748000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5236748000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    526020000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11682724000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12208744000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.007771                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.016107                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.008273                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.153762                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.153762                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.034373                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.034373                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.189068                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.189068                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.007771                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.016107                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.034373                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.176850                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.072776                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.007771                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.016107                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.034373                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.176850                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.162267                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41408.192090                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18771.276596                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38754.987531                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78993.821493                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 78993.821493                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 27034.645476                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 27034.645476                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17929.494655                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17929.494655                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       266500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       266500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56728.710378                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56728.710378                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58335.427977                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58335.427977                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28958.752565                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28958.752565                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41408.192090                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18771.276596                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58335.427977                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37314.062269                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44186.186519                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41408.192090                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18771.276596                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58335.427977                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37314.062269                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78993.821493                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63382.754233                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201141.323681                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193860.415972                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182312.630553                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182312.630553                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192241.760050                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188732.747959                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests      5755750                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2900650                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        44518                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       351752                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       347037                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4715                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq        143210                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      2766468                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28724                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28724                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty       746011                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      2247535                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict       246533                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       331594                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        87502                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43040                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       114569                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       300476                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       297107                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      2041686                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       606504                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3118                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      6096444                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2755852                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13844                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       190303                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          9056443                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    259253824                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    104429286                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        23344                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       364416                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         364070870                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    1078661                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      4070756                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.104237                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.309335                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           3651149     89.69%     89.69% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            414892     10.19%     99.88% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2              4715      0.12%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       4070756                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    5766247494                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    116466956                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   3069095112                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1306223847                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      8018479                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     99225447                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups                3641195                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          2056746                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           213596                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             2171070                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                1462919                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            67.382397                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 753966                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             56559                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    23130                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               23130                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        18836                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4294                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples        23130                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0          23130    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        23130                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         1830                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11932.513661                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11127.774947                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  7404.648675                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-16383         1668     91.15%     91.15% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-32767          148      8.09%     99.23% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-49151            8      0.44%     99.67% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-65535            3      0.16%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::147456-163839            3      0.16%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         1830                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -1558893032                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1558893032    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -1558893032                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1322     72.24%     72.24% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          508     27.76%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         1830                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        23130                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        23130                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1830                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1830                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        24960                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     3607725                       # DTB read hits
system.cpu1.dtb.read_misses                     21408                       # DTB read misses
system.cpu1.dtb.write_hits                    2997772                       # DTB write hits
system.cpu1.dtb.write_misses                     1722                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1725                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      120                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   261                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      213                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 3629133                       # DTB read accesses
system.cpu1.dtb.write_accesses                2999494                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          6605497                       # DTB hits
system.cpu1.dtb.misses                          23130                       # DTB misses
system.cpu1.dtb.accesses                      6628627                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     1936                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                1936                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          152                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1784                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         1936                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           1936    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         1936                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples          845                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 11855.029586                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11358.377652                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  4391.934541                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          130     15.38%     15.38% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          557     65.92%     81.30% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          112     13.25%     94.56% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479           22      2.60%     97.16% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575            3      0.36%     97.51% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           10      1.18%     98.70% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767            2      0.24%     98.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863            1      0.12%     99.05% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959            6      0.71%     99.76% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.12%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::61440-65535            1      0.12%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total          845                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1559948532                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1559948532    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1559948532                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          705     83.43%     83.43% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          140     16.57%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total          845                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1936                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1936                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          845                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total          845                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         2781                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                     6961088                       # ITB inst hits
system.cpu1.itb.inst_misses                      1936                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                     909                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1058                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 6963024                       # ITB inst accesses
system.cpu1.itb.hits                          6961088                       # DTB hits
system.cpu1.itb.misses                           1936                       # DTB misses
system.cpu1.itb.accesses                      6963024                       # DTB accesses
system.cpu1.numCycles                        40816703                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   14109392                       # Number of instructions committed
system.cpu1.committedOps                     17295649                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                      1386756                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     2772                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                  5656506173                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.892875                       # CPI: cycles per instruction
system.cpu1.ipc                              0.345677                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2772                       # number of quiesce instructions executed
system.cpu1.tickCycles                       27557255                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                       13259448                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements           157096                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          475.586306                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            6254726                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           157444                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            39.726671                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      91652045000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   475.586306                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.928880                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.928880                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          348                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          283                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           65                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.679688                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         13266107                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        13266107                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      3282974                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3282974                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      2751908                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       2751908                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        42647                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        42647                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        70687                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        70687                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        62029                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        62029                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      6034882                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         6034882                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      6077529                       # number of overall hits
system.cpu1.dcache.overall_hits::total        6077529                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       135266                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       135266                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       122118                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       122118                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        24580                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        24580                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16502                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        16502                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23395                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23395                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       257384                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        257384                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       281964                       # number of overall misses
system.cpu1.dcache.overall_misses::total       281964                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2192537500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2192537500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4529521000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   4529521000                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    318889500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    318889500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    637518000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    637518000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1095000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1095000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   6722058500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   6722058500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   6722058500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   6722058500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      3418240                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      3418240                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      2874026                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      2874026                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        67227                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        67227                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        87189                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        87189                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        85424                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        85424                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      6292266                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      6292266                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      6359493                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      6359493                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.039572                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.039572                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.042490                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.042490                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.365627                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.365627                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.189267                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.189267                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.273869                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.273869                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.040905                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.040905                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044337                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.044337                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16209.080626                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16209.080626                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37091.346075                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 37091.346075                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19324.294025                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19324.294025                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27250.181663                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27250.181663                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26116.846813                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 26116.846813                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23840.130300                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 23840.130300                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       157097                       # number of writebacks
system.cpu1.dcache.writebacks::total           157097                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        12921                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        12921                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        42016                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total        42016                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11695                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11695                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        54937                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        54937                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        54937                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        54937                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       122345                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       122345                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        80102                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        80102                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        24073                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        24073                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4807                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4807                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23395                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23395                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       202447                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       202447                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       226520                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       226520                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         2973                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         2973                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2311                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2311                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5284                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5284                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1862537500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1862537500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2760870000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2760870000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    453287500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    453287500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     86939500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     86939500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    614134000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    614134000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1084000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1084000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4623407500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4623407500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5076695000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   5076695000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    389226500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    389226500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    251720500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    251720500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    640947000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    640947000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035792                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035792                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027871                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027871                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.358085                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.358085                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.055133                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.055133                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.273869                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.273869                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.032174                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.032174                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035619                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035619                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15223.650333                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15223.650333                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34466.929665                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34466.929665                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18829.705479                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18829.705479                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18086.020387                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18086.020387                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26250.651849                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26250.651849                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22837.619229                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22837.619229                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22411.685502                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22411.685502                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130920.450723                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 130920.450723                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108922.760710                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108922.760710                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121299.583649                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121299.583649                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           864194                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.135415                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs            6095160                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           864706                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs             7.048824                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      73316283000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.135415                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974874                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.974874                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          460                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           51                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         14784438                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        14784438                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst      6095160                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        6095160                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      6095160                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         6095160                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      6095160                       # number of overall hits
system.cpu1.icache.overall_hits::total        6095160                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       864706                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       864706                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       864706                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        864706                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       864706                       # number of overall misses
system.cpu1.icache.overall_misses::total       864706                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7648423000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   7648423000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   7648423000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   7648423000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   7648423000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   7648423000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      6959866                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      6959866                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      6959866                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      6959866                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      6959866                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      6959866                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.124242                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.124242                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.124242                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.124242                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.124242                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.124242                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8845.113831                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8845.113831                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8845.113831                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8845.113831                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8845.113831                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8845.113831                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks       864194                       # number of writebacks
system.cpu1.icache.writebacks::total           864194                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       864706                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       864706                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       864706                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       864706                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       864706                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       864706                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7216070000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7216070000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7216070000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7216070000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7216070000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7216070000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15350500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     15350500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     15350500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     15350500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.124242                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.124242                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.124242                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.124242                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.124242                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.124242                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8345.113831                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8345.113831                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8345.113831                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8345.113831                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8345.113831                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8345.113831                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137058.035714                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137058.035714                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued       119025                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       119084                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           52                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        48684                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           38075                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15173.951540                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1858742                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           53288                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           34.881061                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14749.353983                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    37.286789                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.078849                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   387.231918                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.900229                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002276                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000005                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.023635                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.926145                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          919                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           92                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14202                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           50                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          864                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           18                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           18                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           56                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          337                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1786                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        12079                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.056091                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005615                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.866821                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        34538889                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       34538889                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        24515                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2453                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total         26968                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks        95201                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total        95201                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks       907759                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total       907759                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        18142                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        18142                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       851797                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       851797                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        83849                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total        83849                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        24515                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2453                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       851797                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       101991                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         980756                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        24515                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2453                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       851797                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       101991                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        980756                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          708                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          242                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          950                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29444                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        29444                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23394                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        23394                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32519                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        32519                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        12909                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        12909                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        67373                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        67373                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          708                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          242                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        12909                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data        99892                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       113751                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          708                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          242                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        12909                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data        99892                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       113751                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     15804500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4851500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     20656000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     65469500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total     65469500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     59113000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     59113000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1066999                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1066999                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1736092499                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1736092499                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    738228000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total    738228000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1614591996                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1614591996                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     15804500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4851500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    738228000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3350684495                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   4109568495                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     15804500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4851500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    738228000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3350684495                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   4109568495                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        25223                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2695                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total        27918                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks        95201                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total        95201                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks       907759                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total       907759                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29444                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29444                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23394                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23394                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        50661                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        50661                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       864706                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       864706                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       151222                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       151222                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        25223                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2695                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       864706                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       201883                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      1094507                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        25223                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2695                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       864706                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       201883                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      1094507                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.028070                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.089796                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.034028                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.641894                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.641894                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.014929                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.014929                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.445524                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.445524                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.028070                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.089796                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.014929                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.494801                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.103929                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.028070                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.089796                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.014929                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.494801                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.103929                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22322.740113                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20047.520661                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21743.157895                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2223.526015                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2223.526015                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2526.844490                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2526.844490                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1066999                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1066999                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53387.019865                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53387.019865                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 57187.078782                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 57187.078782                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23964.971071                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23964.971071                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22322.740113                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20047.520661                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 57187.078782                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33543.071467                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 36127.757075                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22322.740113                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20047.520661                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 57187.078782                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33543.071467                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 36127.757075                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs           84                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           28                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        29108                       # number of writebacks
system.cpu1.l2cache.writebacks::total           29108                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          236                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          236                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            9                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           35                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           35                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            9                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          271                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          280                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            9                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          271                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          280                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          708                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          242                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          950                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        20082                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        20082                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29444                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29444                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23394                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23394                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        32283                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        32283                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        12900                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        12900                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        67338                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        67338                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          708                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          242                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        12900                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data        99621                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       113471                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          708                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          242                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        12900                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data        99621                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        20082                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       133553                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         2973                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3085                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2311                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2311                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5284                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5396                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     11556500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3399500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     14956000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1023264430                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1023264430                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    603797000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    603797000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    437130500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    437130500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1000999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1000999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1515754000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1515754000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    660362000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    660362000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1209005996                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1209005996                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     11556500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3399500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    660362000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2724759996                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   3400077996                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     11556500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3399500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    660362000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2724759996                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1023264430                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   4423342426                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14454500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    365375500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    379830000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    234264000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    234264000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     14454500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    599639500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    614094000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.028070                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.089796                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.034028                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.637236                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.637236                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.014918                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014918                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.445292                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.445292                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.028070                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.089796                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.014918                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.493459                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.103673                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.028070                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.089796                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.014918                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.493459                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.122021                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16322.740113                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14047.520661                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15743.157895                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50954.308834                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50954.308834                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20506.622741                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20506.622741                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18685.581773                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18685.581773                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      1000999                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1000999                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46952.080042                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46952.080042                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51190.852713                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51190.852713                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17954.290237                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17954.290237                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16322.740113                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14047.520661                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51190.852713                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27351.261240                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29964.290400                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16322.740113                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14047.520661                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51190.852713                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27351.261240                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50954.308834                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33120.502168                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122897.914564                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123121.555916                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101369.104284                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101369.104284                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113482.115821                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113805.411416                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests      2148021                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1081444                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        18331                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       178235                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       177001                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1234                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq         34229                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      1087159                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         2311                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2311                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty       125656                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean       907759                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict        98212                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        24432                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        72484                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41782                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        85083                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        57811                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        55294                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       864706                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       235840                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq           36                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      2577500                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       749010                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6415                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        52647                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          3385572                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    109611648                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25531190                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        10780                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       100892                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         135254510                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     383471                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      1462314                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.140260                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.349678                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0           1258444     86.06%     86.06% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            202636     13.86%     99.92% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2              1234      0.08%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1462314                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    2111082490                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     78627228                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   1297343267                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    334901961                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      3720499                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     27451445                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31009                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31009                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59424                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59424                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56618                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107932                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180866                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71562                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162812                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2483988                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             51120500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               109500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               320500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                28500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                12500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                84500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               571500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               20500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               45500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6117000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            32846500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           186337026                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84732000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36758000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36449                       # number of replacements
system.iocache.tags.tagsinuse               14.469949                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36465                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         272430408000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.469949                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.904372                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.904372                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328203                       # Number of tag accesses
system.iocache.tags.data_accesses              328203                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          243                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          243                       # number of demand (read+write) misses
system.iocache.demand_misses::total               243                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          243                       # number of overall misses
system.iocache.overall_misses::total              243                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     32247375                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     32247375                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4733187651                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4733187651                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     32247375                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     32247375                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     32247375                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     32247375                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          243                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             243                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          243                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            243                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 132705.246914                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 132705.246914                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130664.411744                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130664.411744                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 132705.246914                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 132705.246914                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 132705.246914                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 132705.246914                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           621                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   79                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.860759                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36206                       # number of writebacks
system.iocache.writebacks::total                36206                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          243                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          243                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          243                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          243                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     20097375                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     20097375                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2921987651                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2921987651                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     20097375                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     20097375                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     20097375                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     20097375                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 82705.246914                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 82705.246914                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80664.411744                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80664.411744                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 82705.246914                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 82705.246914                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 82705.246914                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 82705.246914                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   131701                       # number of replacements
system.l2c.tags.tagsinuse                63232.493895                       # Cycle average of tags in use
system.l2c.tags.total_refs                     477114                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   195835                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.436306                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   13499.183462                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    81.189305                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.030804                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     9276.099032                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2886.907500                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33207.909394                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     5.955383                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1918.551839                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      583.845643                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1772.821532                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.205981                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001239                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.141542                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.044051                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.506712                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000091                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.029275                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.008909                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.027051                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.964851                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        28913                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           59                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        35162                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          119                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         4903                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        23890                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           59                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            5                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          486                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         3361                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        31288                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.441177                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000900                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.536530                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6403013                       # Number of tag accesses
system.l2c.tags.data_accesses                 6403013                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks       266916                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          266916                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           34147                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            2219                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               36366                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          2260                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           929                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              3189                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4341                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1335                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5676                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          425                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           89                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        47541                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        51775                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        49659                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           78                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           12                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst         9744                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data         5530                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         3532                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           168385                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker           425                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            89                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               47541                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               56116                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        49659                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            78                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            12                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                9744                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                6865                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         3532                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  174061                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          425                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           89                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              47541                       # number of overall hits
system.l2c.overall_hits::cpu0.data              56116                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        49659                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           78                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           12                       # number of overall hits
system.l2c.overall_hits::cpu1.inst               9744                       # number of overall hits
system.l2c.overall_hits::cpu1.data               6865                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         3532                       # number of overall hits
system.l2c.overall_hits::total                 174061                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         10466                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          2461                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             12927                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          842                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1269                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            2111                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11510                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8279                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19789                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          132                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        22638                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         9815                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       133222                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker           10                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         3156                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         1620                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         5587                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         176181                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker          132                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             22638                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             21325                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       133222                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           10                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              3156                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              9899                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         5587                       # number of demand (read+write) misses
system.l2c.demand_misses::total                195970                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker          132                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            22638                       # number of overall misses
system.l2c.overall_misses::cpu0.data            21325                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       133222                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           10                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             3156                       # number of overall misses
system.l2c.overall_misses::cpu1.data             9899                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         5587                       # number of overall misses
system.l2c.overall_misses::total               195970                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data     30632500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      6192500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     36825000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      4484000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2324500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      6808500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1686851000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1090555500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2777406500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     18272000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       133000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   2964447500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1349172500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  19981710279                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker      1426000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    417581000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    225572000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    946990899                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  25905305178                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker     18272000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       133000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   2964447500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   3036023500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  19981710279                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1426000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    417581000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1316127500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    946990899                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     28682711678                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker     18272000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       133000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   2964447500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   3036023500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  19981710279                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1426000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    417581000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1316127500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    946990899                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    28682711678                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       266916                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       266916                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        44613                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4680                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           49293                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         3102                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         2198                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          5300                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15851                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         9614                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            25465                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          557                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           90                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        70179                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        61590                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       182881                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           88                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           12                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        12900                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data         7150                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher         9119                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       344566                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          557                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           90                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           70179                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           77441                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       182881                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           88                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           12                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           12900                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           16764                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher         9119                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              370031                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          557                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           90                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          70179                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          77441                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       182881                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           88                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           12                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          12900                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          16764                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher         9119                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             370031                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.234595                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.525855                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.262248                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.271438                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.577343                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.398302                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.726137                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.861140                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.777106                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.236984                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.011111                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.322575                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.159360                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.728463                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.113636                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.244651                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.226573                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.612677                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.511313                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.236984                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.011111                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.322575                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.275371                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.728463                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.113636                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.244651                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.590492                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.612677                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.529604                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.236984                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.011111                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.322575                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.275371                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.728463                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.113636                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.244651                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.590492                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.612677                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.529604                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2926.858399                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2516.253555                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2848.688791                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5325.415677                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1831.757289                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3225.248697                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 146555.256299                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131725.510327                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 140351.028349                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 138424.242424                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       133000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 130950.061843                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137460.264901                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 149988.067129                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker       142600                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 132313.371356                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139241.975309                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 169498.997494                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 147038.018731                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138424.242424                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       133000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 130950.061843                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 142369.214537                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 149988.067129                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       142600                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 132313.371356                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 132955.601576                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 169498.997494                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 146362.768169                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 138424.242424                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       133000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 130950.061843                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 142369.214537                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 149988.067129                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       142600                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 132313.371356                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 132955.601576                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 169498.997494                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 146362.768169                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              102060                       # number of writebacks
system.l2c.writebacks::total                   102060                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            4                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            1                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  5                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 5                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         3561                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         3561                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        10466                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         2461                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        12927                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          842                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1269                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         2111                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11510                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8279                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19789                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          132                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        22634                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9815                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       133222                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker           10                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         3155                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         1620                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         5587                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       176176                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker          132                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        22634                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        21325                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       133222                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           10                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         3155                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         9899                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         5587                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           195965                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker          132                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        22634                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        21325                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       133222                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           10                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         3155                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         9899                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         5587                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          195965                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3917                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        32047                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         2970                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        39046                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28724                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2311                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        31035                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3917                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60771                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         5281                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        70081                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    791418000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    185319000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    976737000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     65159500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     97313500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    162473000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1571751000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1007765500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2579516500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker     16952000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       123000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   2737736000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1251022500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  18649490279                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker      1326000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    385923000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    209372000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    891120899                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  24143065678                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     16952000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       123000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   2737736000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2822773500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  18649490279                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1326000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    385923000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1217137500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    891120899                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  26722582178                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     16952000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       123000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   2737736000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2822773500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  18649490279                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1326000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    385923000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1217137500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    891120899                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  26722582178                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    443763000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5869112000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     12102000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    311853000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6636830000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4748303000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    194971500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4943274500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    443763000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10617415000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     12102000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    506824500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  11580104500                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.234595                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.525855                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.262248                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.271438                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.577343                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.398302                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.726137                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.861140                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.777106                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.236984                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.011111                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.322518                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.159360                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728463                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.113636                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.244574                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.226573                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.612677                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.511298                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.236984                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011111                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.322518                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.275371                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728463                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.113636                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.244574                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.590492                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.612677                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.529591                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.236984                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011111                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.322518                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.275371                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728463                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.113636                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.244574                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.590492                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.612677                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.529591                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75618.001147                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75302.316132                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75557.902065                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77386.579572                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76685.185185                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76964.945523                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 136555.256299                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121725.510327                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 130351.028349                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 128424.242424                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 120956.790669                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127460.264901                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 139988.067129                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker       132600                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 122321.077655                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129241.975309                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159498.997494                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137039.470064                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128424.242424                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120956.790669                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 132369.214537                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 139988.067129                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker       132600                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122321.077655                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122955.601576                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159498.997494                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 136364.055714                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128424.242424                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120956.790669                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 132369.214537                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 139988.067129                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker       132600                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122321.077655                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122955.601576                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159498.997494                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 136364.055714                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183140.762006                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105001.010101                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169974.645290                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165307.861022                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84366.724362                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159280.634767                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174711.869148                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 95971.312251                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 165238.859320                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               39046                       # Transaction distribution
system.membus.trans_dist::ReadResp             215465                       # Transaction distribution
system.membus.trans_dist::WriteReq              31035                       # Transaction distribution
system.membus.trans_dist::WriteResp             31035                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       138266                       # Transaction distribution
system.membus.trans_dist::CleanEvict            17702                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            74461                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40765                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           15160                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
system.membus.trans_dist::ReadExReq             40157                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19667                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        176419                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107932                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           42                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14220                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       679941                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       802135                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108925                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108925                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 911060                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162812                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1344                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28440                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19320688                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     19513284                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21831428                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           121126                       # Total snoops (count)
system.membus.snoop_fanout::samples            594326                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  594326    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              594326                       # Request fanout histogram
system.membus.reqLayer0.occupancy            91340500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               23828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            12352499                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1009821404                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1176071579                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64144132                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests      1045963                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       564632                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       154673                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          20991                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        19997                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops          994                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              39049                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            502457                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             31035                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            31035                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       405200                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          105572                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          110705                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         43954                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         154659                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           23                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            51324                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           51324                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       463423                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1306764                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       270016                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1576780                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     36870810                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4377514                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               41248324                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          449455                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           943932                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.340597                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.476127                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 623426     66.05%     66.05% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 319512     33.85%     99.89% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    994      0.11%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             943932                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          904213819                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           343121                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         693007025                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         215048953                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------