1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
|
---------- Begin Simulation Statistics ----------
sim_seconds 2.848913 # Number of seconds simulated
sim_ticks 2848912955000 # Number of ticks simulated
final_tick 2848912955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 258856 # Simulator instruction rate (inst/s)
host_op_rate 313468 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5762698171 # Simulator tick rate (ticks/s)
host_mem_usage 627144 # Number of bytes of host memory used
host_seconds 494.37 # Real time elapsed on the host
sim_insts 127970828 # Number of instructions simulated
sim_ops 154969713 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 9408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1675840 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 1349948 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 8501504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 229824 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 661012 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 405952 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 12835728 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1675840 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 229824 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1905664 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9061888 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
system.physmem.bytes_written::total 9079452 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 147 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 26185 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 21618 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 132836 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 3591 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 10349 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 6343 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 201104 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 141592 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
system.physmem.num_writes::total 145983 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 3302 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 588238 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 473847 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 2984122 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 427 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 80671 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 232023 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 142494 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4505483 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 588238 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 80671 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 668909 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3180823 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3186988 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3180823 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 3302 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 588238 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 479998 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 2984122 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 427 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 80671 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 232037 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 142494 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7692471 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 201104 # Number of read requests accepted
system.physmem.writeReqs 145983 # Number of write requests accepted
system.physmem.readBursts 201104 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 145983 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 12861056 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue
system.physmem.bytesWritten 9091968 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 12835728 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 9079452 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 12429 # Per bank write bursts
system.physmem.perBankRdBursts::1 12794 # Per bank write bursts
system.physmem.perBankRdBursts::2 13696 # Per bank write bursts
system.physmem.perBankRdBursts::3 13190 # Per bank write bursts
system.physmem.perBankRdBursts::4 15337 # Per bank write bursts
system.physmem.perBankRdBursts::5 12894 # Per bank write bursts
system.physmem.perBankRdBursts::6 12741 # Per bank write bursts
system.physmem.perBankRdBursts::7 13088 # Per bank write bursts
system.physmem.perBankRdBursts::8 12333 # Per bank write bursts
system.physmem.perBankRdBursts::9 12486 # Per bank write bursts
system.physmem.perBankRdBursts::10 11357 # Per bank write bursts
system.physmem.perBankRdBursts::11 10671 # Per bank write bursts
system.physmem.perBankRdBursts::12 11888 # Per bank write bursts
system.physmem.perBankRdBursts::13 12773 # Per bank write bursts
system.physmem.perBankRdBursts::14 11762 # Per bank write bursts
system.physmem.perBankRdBursts::15 11515 # Per bank write bursts
system.physmem.perBankWrBursts::0 8987 # Per bank write bursts
system.physmem.perBankWrBursts::1 9459 # Per bank write bursts
system.physmem.perBankWrBursts::2 10102 # Per bank write bursts
system.physmem.perBankWrBursts::3 9553 # Per bank write bursts
system.physmem.perBankWrBursts::4 8641 # Per bank write bursts
system.physmem.perBankWrBursts::5 9022 # Per bank write bursts
system.physmem.perBankWrBursts::6 9160 # Per bank write bursts
system.physmem.perBankWrBursts::7 9289 # Per bank write bursts
system.physmem.perBankWrBursts::8 8726 # Per bank write bursts
system.physmem.perBankWrBursts::9 8906 # Per bank write bursts
system.physmem.perBankWrBursts::10 8219 # Per bank write bursts
system.physmem.perBankWrBursts::11 7897 # Per bank write bursts
system.physmem.perBankWrBursts::12 8731 # Per bank write bursts
system.physmem.perBankWrBursts::13 8920 # Per bank write bursts
system.physmem.perBankWrBursts::14 8491 # Per bank write bursts
system.physmem.perBankWrBursts::15 7959 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 98 # Number of times write queue was full causing retry
system.physmem.totGap 2848912399000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 556 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 200520 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4391 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 141592 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 84624 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 63240 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 11856 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 9787 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8153 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 6722 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 5707 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 4943 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 4044 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1053 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 240 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 173 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 127 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2671 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3539 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5027 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6466 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7579 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8612 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8496 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 9787 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 10402 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 9031 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8601 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 9100 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 10035 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 8447 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 8229 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 943 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 593 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 477 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 428 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 296 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 236 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 211 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 194 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 248 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 226 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 220 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 228 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 202 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 262 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 201 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 198 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 156 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 221 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 217 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 179 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 143 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 296 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 89688 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 244.770315 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 140.172635 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 301.083170 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 45750 51.01% 51.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 18787 20.95% 71.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6651 7.42% 79.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3758 4.19% 83.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2958 3.30% 86.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1568 1.75% 88.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1004 1.12% 89.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1009 1.13% 90.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8203 9.15% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 89688 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 7073 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 28.410010 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 554.388606 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 7071 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 7073 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 7073 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.085112 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.515707 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 13.383837 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5944 84.04% 84.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 432 6.11% 90.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 82 1.16% 91.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 52 0.74% 92.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 255 3.61% 95.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 25 0.35% 96.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 15 0.21% 96.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 7 0.10% 96.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 13 0.18% 96.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 9 0.13% 96.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 4 0.06% 96.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 7 0.10% 96.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 148 2.09% 98.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 11 0.16% 99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 6 0.08% 99.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 3 0.04% 99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 9 0.13% 99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 3 0.04% 99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 4 0.06% 99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 6 0.08% 99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.03% 99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 3 0.04% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.01% 99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.01% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 6 0.08% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 3 0.04% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 4 0.06% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.03% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 1 0.01% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 3 0.04% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 4 0.06% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 1 0.01% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 1 0.01% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 1 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187 1 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 7073 # Writes before turning the bus around for reads
system.physmem.totQLat 9366475580 # Total ticks spent queuing
system.physmem.totMemAccLat 13134363080 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1004770000 # Total ticks spent in databus transfers
system.physmem.avgQLat 46610.05 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 65360.05 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.51 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.19 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.51 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.19 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
system.physmem.avgWrQLen 22.20 # Average write queue length when enqueuing
system.physmem.readRowHits 166422 # Number of row buffer hits during reads
system.physmem.writeRowHits 86905 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 61.16 # Row buffer hit rate for writes
system.physmem.avgGap 8208064.26 # Average gap between requests
system.physmem.pageHitRate 73.85 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 341813220 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 181678035 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 758046660 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 387391860 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 5805889440.000001 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 5444775090 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 308095680 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 11642068740 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 8562690720 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 670190772435 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 703626055650 # Total energy per rank (pJ)
system.physmem_0.averagePower 246.980538 # Core power per rank (mW)
system.physmem_0.totalIdleTime 2836051939093 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 546109733 # Time in different power states
system.physmem_0.memoryStateTime::REF 2466940000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 2788334468750 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 22298648785 # Time in different power states
system.physmem_0.memoryStateTime::ACT 9735828674 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 25530959058 # Time in different power states
system.physmem_1.actEnergy 298566240 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 158687925 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 676764900 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 354171780 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 5707547040.000001 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 5348415450 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 325299360 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 10595992200 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 8817735360 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 670663868775 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 702949735620 # Total energy per rank (pJ)
system.physmem_1.averagePower 246.743143 # Core power per rank (mW)
system.physmem_1.totalIdleTime 2836330915238 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 596946927 # Time in different power states
system.physmem_1.memoryStateTime::REF 2425844000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 2790131179750 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 22962884806 # Time in different power states
system.physmem_1.memoryStateTime::ACT 9559167335 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 23236932182 # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 20830846 # Number of BP lookups
system.cpu0.branchPred.condPredicted 13649526 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 1014386 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 13197369 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 8753451 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 66.327243 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 3414506 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 211257 # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups 762629 # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits 580306 # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses 182323 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 100148 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 66699 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 66699 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45954 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20745 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples 66699 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 66699 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 66699 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 6786 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12503.831418 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11414.396725 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 6634.903581 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383 6272 92.43% 92.43% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767 416 6.13% 98.56% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151 85 1.25% 99.81% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535 5 0.07% 99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687 5 0.07% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::114688-131071 2 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 6786 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 338892000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 338892000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 338892000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 5256 77.45% 77.45% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1530 22.55% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 6786 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66699 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66699 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6786 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6786 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 73485 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 17337178 # DTB read hits
system.cpu0.dtb.read_misses 60105 # DTB read misses
system.cpu0.dtb.write_hits 14536732 # DTB write hits
system.cpu0.dtb.write_misses 6594 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3451 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1375 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 1930 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 524 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 17397283 # DTB read accesses
system.cpu0.dtb.write_accesses 14543326 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 31873910 # DTB hits
system.cpu0.dtb.misses 66699 # DTB misses
system.cpu0.dtb.accesses 31940609 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 4013 # Table walker walks requested
system.cpu0.itb.walker.walksShort 4013 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 305 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3708 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples 4013 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 4013 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 4013 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 2436 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12745.689655 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11895.862443 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 5321.422543 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191 433 17.78% 17.78% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383 1791 73.52% 91.30% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575 138 5.67% 96.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767 37 1.52% 98.48% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959 36 1.48% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 2436 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 338263500 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 338263500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 338263500 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 2136 87.68% 87.68% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 300 12.32% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2436 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4013 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4013 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2436 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2436 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 6449 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 38740955 # ITB inst hits
system.cpu0.itb.inst_misses 4013 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2172 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 7050 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 38744968 # ITB inst accesses
system.cpu0.itb.hits 38740955 # DTB hits
system.cpu0.itb.misses 4013 # DTB misses
system.cpu0.itb.accesses 38744968 # DTB accesses
system.cpu0.numPwrStateTransitions 3702 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 1851 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 1492467740.212318 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 23926618307.518574 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 1069 57.75% 57.75% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 775 41.87% 99.62% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 499963002708 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total 1851 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 86355167867 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 2762557787133 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 172712897 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 79713377 # Number of instructions committed
system.cpu0.committedOps 95922535 # Number of ops (including micro ops) committed
system.cpu0.discardedOps 5281292 # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends 1851 # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles 5525141996 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi 2.166674 # CPI: cycles per instruction
system.cpu0.ipc 0.461537 # IPC: instructions per cycle
system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction
system.cpu0.op_class_0::IntAlu 63731011 66.44% 66.44% # Class of committed instruction
system.cpu0.op_class_0::IntMult 92142 0.10% 66.54% # Class of committed instruction
system.cpu0.op_class_0::IntDiv 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::FloatAdd 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::FloatCmp 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::FloatCvt 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::FloatMult 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::FloatDiv 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::FloatMisc 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdAdd 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdAlu 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdCmp 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdCvt 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdMisc 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdMult 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdShift 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.54% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMisc 8073 0.01% 66.55% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.55% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.55% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.55% # Class of committed instruction
system.cpu0.op_class_0::MemRead 16805807 17.52% 84.07% # Class of committed instruction
system.cpu0.op_class_0::MemWrite 15273589 15.92% 99.99% # Class of committed instruction
system.cpu0.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction
system.cpu0.op_class_0::FloatMemWrite 7384 0.01% 100.00% # Class of committed instruction
system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.op_class_0::total 95922535 # Class of committed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 1851 # number of quiesce instructions executed
system.cpu0.tickCycles 120871852 # Number of cycles that the object actually ticked
system.cpu0.idleCycles 51841045 # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 716918 # number of replacements
system.cpu0.dcache.tags.tagsinuse 495.671066 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 30432435 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 717430 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 42.418682 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 356904000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.671066 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968108 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.968108 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 63807329 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 63807329 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 15850504 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 15850504 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 13422208 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 13422208 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320804 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 320804 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365505 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 365505 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361161 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 361161 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 29272712 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 29272712 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 29593516 # number of overall hits
system.cpu0.dcache.overall_hits::total 29593516 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 439135 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 439135 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 581157 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 581157 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 135756 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 135756 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20923 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 20923 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20396 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 20396 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1020292 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1020292 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1156048 # number of overall misses
system.cpu0.dcache.overall_misses::total 1156048 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6443435000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 6443435000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11283390500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 11283390500 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 333090000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 333090000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 482408000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 482408000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 637500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 637500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 17726825500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 17726825500 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 17726825500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 17726825500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 16289639 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 16289639 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 14003365 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 14003365 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456560 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 456560 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386428 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 386428 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381557 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 381557 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 30293004 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 30293004 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 30749564 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 30749564 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026958 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.026958 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041501 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.041501 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.297345 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.297345 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054145 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054145 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053455 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053455 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033681 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.033681 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037596 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.037596 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14673.016271 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14673.016271 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19415.391194 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19415.391194 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15919.801176 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15919.801176 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23652.088645 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23652.088645 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17374.266877 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 17374.266877 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15333.987430 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 15333.987430 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 716918 # number of writebacks
system.cpu0.dcache.writebacks::total 716918 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44597 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 44597 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255598 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 255598 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14548 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14548 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 300195 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 300195 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 300195 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 300195 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 394538 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 394538 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325559 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 325559 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102257 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 102257 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6375 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6375 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20396 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 20396 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 720097 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 720097 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 822354 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 822354 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20581 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20581 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19270 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39851 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39851 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5273598500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5273598500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6168960000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6168960000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1704833000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1704833000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102845500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102845500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 462030000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 462030000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 619500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 619500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11442558500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 11442558500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13147391500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 13147391500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4607502500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4607502500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4607502500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4607502500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024220 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024220 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023249 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023249 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223973 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223973 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016497 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016497 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053455 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053455 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023771 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.023771 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026744 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.026744 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13366.516026 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13366.516026 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18948.823408 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18948.823408 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16672.042012 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16672.042012 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16132.627451 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16132.627451 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22652.971171 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22652.971171 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15890.301584 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15890.301584 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15987.508421 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15987.508421 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223871.653467 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223871.653467 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115618.240446 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115618.240446 # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 1966568 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.773009 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 36766553 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1967080 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 18.690929 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6697446000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.773009 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999557 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999557 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 79434387 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 79434387 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 36766553 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 36766553 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 36766553 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 36766553 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 36766553 # number of overall hits
system.cpu0.icache.overall_hits::total 36766553 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1967094 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1967094 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1967094 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1967094 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1967094 # number of overall misses
system.cpu0.icache.overall_misses::total 1967094 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 19796906000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 19796906000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 19796906000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 19796906000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 19796906000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 19796906000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 38733647 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 38733647 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 38733647 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 38733647 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 38733647 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 38733647 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050785 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.050785 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050785 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.050785 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050785 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.050785 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10064.036594 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10064.036594 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10064.036594 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10064.036594 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10064.036594 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10064.036594 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 1966568 # number of writebacks
system.cpu0.icache.writebacks::total 1966568 # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1967094 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1967094 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 1967094 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1967094 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 1967094 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1967094 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 3277 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 3277 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 18813359500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 18813359500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 18813359500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 18813359500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 18813359500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 18813359500 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 323882000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 323882000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 323882000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 323882000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050785 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050785 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050785 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.050785 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050785 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.050785 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9564.036848 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9564.036848 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9564.036848 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 9564.036848 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9564.036848 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 9564.036848 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98834.909979 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98834.909979 # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1845428 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 1845508 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 70 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 235148 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 289262 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 15626.234267 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 2591525 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 304855 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 8.500845 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14514.282419 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 66.020594 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.070348 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1045.860906 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.885881 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004030 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063834 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.953750 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 230 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15349 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 21 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 83 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1192 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7258 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5558 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1085 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.014038 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936829 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 91498325 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 91498325 # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 78219 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5306 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 83525 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 481785 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 481785 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 2159151 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 2159151 # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 222970 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 222970 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1875280 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 1875280 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 389002 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 389002 # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 78219 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5306 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1875280 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 611972 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 2570777 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 78219 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5306 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1875280 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 611972 # number of overall hits
system.cpu0.l2cache.overall_hits::total 2570777 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 1055 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 176 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 1231 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56519 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 56519 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20396 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 20396 # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 46078 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 46078 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 91814 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 91814 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 114162 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 114162 # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 1055 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 176 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 91814 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 160240 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 253285 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 1055 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 176 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 91814 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 160240 # number of overall misses
system.cpu0.l2cache.overall_misses::total 253285 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 45088000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4105500 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 49193500 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 43638000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 43638000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 10254000 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 10254000 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 591500 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 591500 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2907293999 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 2907293999 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4520777000 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4520777000 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3763870996 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3763870996 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 45088000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4105500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4520777000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 6671164995 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 11241135495 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 45088000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4105500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4520777000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 6671164995 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 11241135495 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 79274 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5482 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 84756 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481785 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total 481785 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks 2159151 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total 2159151 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56519 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 56519 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20396 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 20396 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269048 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 269048 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1967094 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 1967094 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 503164 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 503164 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 79274 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5482 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1967094 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 772212 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 2824062 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 79274 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5482 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1967094 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 772212 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 2824062 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.013308 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.032105 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.171263 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.171263 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.046675 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.046675 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.226888 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.226888 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.013308 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.032105 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.046675 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.207508 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.089688 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.013308 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.032105 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.046675 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.207508 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.089688 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42737.440758 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23326.704545 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39962.225833 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 772.094340 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 772.094340 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 502.745636 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 502.745636 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63095.056187 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63095.056187 # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49238.427691 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49238.427691 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32969.560765 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32969.560765 # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42737.440758 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23326.704545 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49238.427691 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41632.332720 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 44381.370768 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42737.440758 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23326.704545 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49238.427691 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41632.332720 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 44381.370768 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches 10931 # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks 232720 # number of writebacks
system.cpu0.l2cache.writebacks::total 232720 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 4 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 4 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3236 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 3236 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 62 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 62 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 399 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 399 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 4 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 4 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 62 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3635 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 3705 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 4 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 4 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 62 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3635 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 3705 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 1051 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 172 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 1223 # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 265014 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 265014 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 56519 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 56519 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20396 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20396 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42842 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 42842 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 91752 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 91752 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 113763 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 113763 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 1051 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 172 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 91752 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 156605 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 249580 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 1051 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 172 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 91752 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 156605 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 265014 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 514594 # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20581 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23858 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19270 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39851 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 43128 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 38674000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3003500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 41677500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16721781964 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16721781964 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 978283000 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 978283000 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 308154500 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 308154500 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 483500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 483500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2153848999 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2153848999 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3967827500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3967827500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 3058327496 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 3058327496 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 38674000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3003500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3967827500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5212176495 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 9221681495 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 38674000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3003500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3967827500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5212176495 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16721781964 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 25943463459 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 297666000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4442744500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4740410500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 297666000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4442744500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4740410500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013258 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031375 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.014430 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159236 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159236 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046643 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046643 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.226095 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.226095 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013258 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031375 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046643 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.202801 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088376 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013258 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031375 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046643 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.202801 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.182218 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34078.086672 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63097.730550 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63097.730550 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17308.922663 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17308.922663 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15108.575211 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15108.575211 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50274.240208 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50274.240208 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43245.133621 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26883.323189 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26883.323189 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33282.312155 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36948.799964 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33282.312155 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63097.730550 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50415.402160 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215866.308731 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198692.702657 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111483.889990 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109914.916064 # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests 5521359 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2782090 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 221607 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 217384 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4223 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 119065 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 2638335 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 19270 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 19270 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 714834 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 2201699 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 105895 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 314040 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 88690 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43009 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 113952 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 288266 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 284716 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1967094 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603225 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 3100 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 13 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5907309 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2596679 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13203 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166718 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 8683909 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251964032 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99557768 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21928 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 317096 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 351860824 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 942421 # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic 19099824 # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples 3784720 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.076642 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.270185 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 3498873 92.45% 92.45% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 281624 7.44% 99.89% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 4223 0.11% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 3784720 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 5512121494 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 115701354 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 2955829450 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 1228012492 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 7726489 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 87463960 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 19376501 # Number of BP lookups
system.cpu1.branchPred.condPredicted 6203106 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 800498 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 9925818 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 3621861 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 36.489295 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 8664248 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 596452 # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups 3651980 # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits 3587973 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 64007 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 23614 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 26236 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 26236 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19848 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6388 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples 26236 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 26236 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 26236 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 2697 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 12386.911383 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11389.033391 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 6251.379906 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191 628 23.29% 23.29% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1805 66.93% 90.21% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575 172 6.38% 96.59% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.08% 98.67% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959 26 0.96% 99.63% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151 2 0.07% 99.70% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343 3 0.11% 99.81% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.07% 99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-106495 3 0.11% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 2697 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples -1855739032 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -1855739032 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -1855739032 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 2013 74.64% 74.64% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 684 25.36% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 2697 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26236 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26236 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2697 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2697 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 28933 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 11335471 # DTB read hits
system.cpu1.dtb.read_misses 23997 # DTB read misses
system.cpu1.dtb.write_hits 7067505 # DTB write hits
system.cpu1.dtb.write_misses 2239 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1990 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 147 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 359 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 265 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 11359468 # DTB read accesses
system.cpu1.dtb.write_accesses 7069744 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 18402976 # DTB hits
system.cpu1.dtb.misses 26236 # DTB misses
system.cpu1.dtb.accesses 18429212 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 2445 # Table walker walks requested
system.cpu1.itb.walker.walksShort 2445 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 180 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2265 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 2445 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 2445 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 2445 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12500.891266 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11818.240424 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 4741.770571 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 15.60% 15.60% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287 626 55.79% 71.39% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383 208 18.54% 89.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.37% 94.30% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575 21 1.87% 96.17% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671 29 2.58% 98.75% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767 9 0.80% 99.55% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.18% 99.73% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples -1856356532 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -1856356532 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -1856356532 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 957 85.29% 85.29% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 165 14.71% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2445 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2445 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 3567 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 39707544 # ITB inst hits
system.cpu1.itb.inst_misses 2445 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 1094 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 1860 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 39709989 # ITB inst accesses
system.cpu1.itb.hits 39707544 # DTB hits
system.cpu1.itb.misses 2445 # DTB misses
system.cpu1.itb.accesses 39709989 # DTB accesses
system.cpu1.numPwrStateTransitions 5531 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 2766 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 1008751457.310195 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 25700289930.408852 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows 1968 71.15% 71.15% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.71% 99.86% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 949980202104 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total 2766 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 58706424080 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 2790206530920 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 117416330 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 48257451 # Number of instructions committed
system.cpu1.committedOps 59047178 # Number of ops (including micro ops) committed
system.cpu1.discardedOps 5145755 # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends 2766 # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles 5579767080 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi 2.433123 # CPI: cycles per instruction
system.cpu1.ipc 0.410994 # IPC: instructions per cycle
system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction
system.cpu1.op_class_0::IntAlu 40655660 68.85% 68.85% # Class of committed instruction
system.cpu1.op_class_0::IntMult 45723 0.08% 68.93% # Class of committed instruction
system.cpu1.op_class_0::IntDiv 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::FloatAdd 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::FloatCmp 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::FloatCvt 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::FloatMult 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::FloatMultAcc 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::FloatDiv 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::FloatMisc 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdAdd 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdAlu 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdCmp 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdCvt 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdMisc 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdMult 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdShift 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.93% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMisc 3341 0.01% 68.94% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.94% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.94% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.94% # Class of committed instruction
system.cpu1.op_class_0::MemRead 11158922 18.90% 87.83% # Class of committed instruction
system.cpu1.op_class_0::MemWrite 7181682 12.16% 100.00% # Class of committed instruction
system.cpu1.op_class_0::FloatMemRead 516 0.00% 100.00% # Class of committed instruction
system.cpu1.op_class_0::FloatMemWrite 1268 0.00% 100.00% # Class of committed instruction
system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.op_class_0::total 59047178 # Class of committed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed
system.cpu1.tickCycles 94212752 # Number of cycles that the object actually ticked
system.cpu1.idleCycles 23203578 # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 197406 # number of replacements
system.cpu1.dcache.tags.tagsinuse 475.838335 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 17978253 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 197762 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 90.908531 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 91321339500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.838335 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.929372 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.929372 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 356 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 284 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.695312 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 36857417 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 36857417 # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 10958654 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 10958654 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 6778912 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 6778912 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50538 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 50538 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80236 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 80236 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71701 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 71701 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 17737566 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 17737566 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 17788104 # number of overall hits
system.cpu1.dcache.overall_hits::total 17788104 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 149954 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 149954 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 146295 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 146295 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30728 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 30728 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16950 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 16950 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23669 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 23669 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 296249 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 296249 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 326977 # number of overall misses
system.cpu1.dcache.overall_misses::total 326977 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2480923500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 2480923500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4141245000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 4141245000 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 326364000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 326364000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557050500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 557050500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 662000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 662000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 6622168500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 6622168500 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 6622168500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 6622168500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 11108608 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 11108608 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 6925207 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 6925207 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81266 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 81266 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97186 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 97186 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95370 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 95370 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 18033815 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 18033815 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 18115081 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 18115081 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013499 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.013499 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021125 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.021125 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378116 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378116 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174408 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174408 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248181 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248181 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016427 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.016427 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018050 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.018050 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16544.563666 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16544.563666 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28307.495130 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 28307.495130 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19254.513274 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19254.513274 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23535.024716 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23535.024716 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22353.386847 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 22353.386847 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20252.704319 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 20252.704319 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 197406 # number of writebacks
system.cpu1.dcache.writebacks::total 197406 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 5638 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 5638 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53221 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 53221 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12059 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12059 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 58859 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 58859 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 58859 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 58859 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 144316 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 144316 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 93074 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 93074 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29900 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 29900 # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4891 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4891 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23669 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 23669 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 237390 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 237390 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 267290 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 267290 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14424 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11757 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11757 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26181 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26181 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2239010000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2239010000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2480218000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2480218000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 521766000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 521766000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86789500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86789500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 533397500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 533397500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 646000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 646000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4719228000 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4719228000 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5240994000 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 5240994000 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2492996500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2492996500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2492996500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2492996500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.012991 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.012991 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013440 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013440 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.367928 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.367928 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050326 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050326 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248181 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248181 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013164 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.013164 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014755 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15514.634552 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15514.634552 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26647.807121 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26647.807121 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17450.367893 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17450.367893 # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17744.735228 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17744.735228 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22535.700706 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22535.700706 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19879.641097 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19879.641097 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19607.894048 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19607.894048 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172836.695785 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172836.695785 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95221.591994 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95221.591994 # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 951563 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.187738 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 38753540 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 952075 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 40.704293 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 73017738000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.187738 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974976 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.974976 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 466 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 80363305 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 80363305 # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 38753540 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 38753540 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 38753540 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 38753540 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 38753540 # number of overall hits
system.cpu1.icache.overall_hits::total 38753540 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 952075 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 952075 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 952075 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 952075 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 952075 # number of overall misses
system.cpu1.icache.overall_misses::total 952075 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8812564500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 8812564500 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 8812564500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 8812564500 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 8812564500 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 8812564500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 39705615 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 39705615 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 39705615 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 39705615 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 39705615 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 39705615 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023978 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.023978 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023978 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.023978 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023978 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.023978 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9256.166268 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 9256.166268 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9256.166268 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 9256.166268 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9256.166268 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 9256.166268 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 951563 # number of writebacks
system.cpu1.icache.writebacks::total 951563 # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 952075 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 952075 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 952075 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 952075 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 952075 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 952075 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8336527000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 8336527000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8336527000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 8336527000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8336527000 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 8336527000 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10996500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10996500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10996500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 10996500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023978 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.023978 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.023978 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8756.166268 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 8756.166268 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 8756.166268 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98183.035714 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 98183.035714 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98183.035714 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 98183.035714 # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 202046 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 202062 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 58314 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 53261 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 14759.472479 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 1060224 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 67460 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 15.716336 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14399.124814 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 38.202581 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.100138 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 322.044945 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.878853 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002332 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.019656 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.900847 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 251 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13906 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 79 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 172 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1287 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7824 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4795 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.015320 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.848755 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 39696628 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 39696628 # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28743 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3180 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 31923 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 117832 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 117832 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 1010940 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 1010940 # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28052 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 28052 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 916446 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 916446 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 103629 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 103629 # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28743 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 3180 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 916446 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 131681 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 1080050 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28743 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 3180 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 916446 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 131681 # number of overall hits
system.cpu1.l2cache.overall_hits::total 1080050 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 682 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 266 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 948 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 30054 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 30054 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23668 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 23668 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34968 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 34968 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 35629 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 35629 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 75478 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 75478 # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 682 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 266 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 35629 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 110446 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 147023 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 682 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 266 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 35629 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 110446 # number of overall misses
system.cpu1.l2cache.overall_misses::total 147023 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 15962500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5289000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 21251500 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 13859000 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 13859000 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17603500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17603500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 622000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 622000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1509066000 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 1509066000 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1359934000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1359934000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1890312995 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1890312995 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 15962500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5289000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1359934000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 3399378995 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 4780564495 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 15962500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5289000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1359934000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 3399378995 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 4780564495 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29425 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 3446 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 32871 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 117832 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 117832 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 1010940 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 1010940 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30054 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 30054 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23668 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 23668 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63020 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 63020 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 952075 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 952075 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 179107 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 179107 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29425 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 3446 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 952075 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 242127 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 1227073 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29425 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 3446 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 952075 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 242127 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 1227073 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023178 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.077191 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.028840 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.554871 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.554871 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.037422 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.037422 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.421413 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.421413 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023178 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.077191 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.037422 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.456149 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.119816 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023178 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.077191 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.037422 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.456149 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.119816 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23405.425220 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19883.458647 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22417.194093 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 461.136621 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 461.136621 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 743.767957 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 743.767957 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 622000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 622000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43155.628003 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43155.628003 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38169.300289 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38169.300289 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 25044.555963 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 25044.555963 # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23405.425220 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19883.458647 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38169.300289 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30778.651966 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 32515.759405 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23405.425220 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19883.458647 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38169.300289 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30778.651966 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 32515.759405 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 24 # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches 862 # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks 36438 # number of writebacks
system.cpu1.l2cache.writebacks::total 36438 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 196 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 196 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 18 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 87 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 87 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 18 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 18 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 302 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 681 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 266 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 947 # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 26287 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 26287 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 30054 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 30054 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23668 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23668 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34772 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 34772 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 35611 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 35611 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 75391 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 75391 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 681 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 266 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 35611 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 110163 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 146721 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 681 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 266 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 35611 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 110163 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 26287 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 173008 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14536 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11757 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11757 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26181 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26293 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 11857500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3693000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 15550500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 965321170 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 965321170 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 461957500 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 461957500 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 354728500 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 354728500 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 526000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 526000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1277222000 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1277222000 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 1145765500 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 1145765500 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1434909495 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1434909495 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 11857500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3693000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1145765500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2712131495 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 3873447495 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 11857500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3693000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1145765500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2712131495 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 965321170 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 4838768665 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10100500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2377583500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2387684000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10100500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2377583500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2387684000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028810 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.551761 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.551761 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037404 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.420927 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.420927 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454980 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119570 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454980 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.140992 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16420.802534 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36722.378742 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36722.378742 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15370.915685 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15370.915685 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14987.683792 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14987.683792 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 526000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 526000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36731.335557 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36731.335557 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32174.482604 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19032.901739 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19032.901739 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24619.259597 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26400.089251 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24619.259597 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36722.378742 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27968.467730 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90183.035714 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164835.239878 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164260.044029 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90183.035714 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90813.318819 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90810.634009 # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests 2407036 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1212847 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20197 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 118681 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 110741 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7940 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 51870 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 1220498 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 11757 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 11757 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 156434 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 1031137 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 35507 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 31472 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 73789 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42123 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 86153 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 70267 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 67627 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 952075 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295896 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 106 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2855937 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 915985 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8156 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62049 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 3842127 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121840000 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30925576 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13784 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 117700 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 152897060 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 370911 # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic 5180924 # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples 1603484 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.097889 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.313386 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 1454460 90.71% 90.71% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 141084 8.80% 99.50% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 7940 0.50% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 1603484 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 2385111494 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 79363429 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 1428355849 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 412276680 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 4711996 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 32634978 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 31015 # Transaction distribution
system.iobus.trans_dist::ReadResp 31015 # Transaction distribution
system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
system.iobus.trans_dist::WriteResp 59422 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 48355001 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 611500 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 6349500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 38550000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 187836280 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36461 # number of replacements
system.iocache.tags.tagsinuse 14.472129 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 272035829000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.472129 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.904508 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.904508 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328311 # Number of tag accesses
system.iocache.tags.data_accesses 328311 # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses
system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses
system.iocache.demand_misses::total 36479 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 36479 # number of overall misses
system.iocache.overall_misses::total 36479 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 33894626 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 33894626 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4361652654 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4361652654 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 4395547280 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4395547280 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 4395547280 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4395547280 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 132920.101961 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 132920.101961 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120407.813991 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120407.813991 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 120495.278928 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 120495.278928 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 120495.278928 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 120495.278928 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 33 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 5 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 6.600000 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 36206 # number of writebacks
system.iocache.writebacks::total 36206 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 21144626 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 21144626 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2548533560 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2548533560 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 2569678186 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 2569678186 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 2569678186 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 2569678186 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 82920.101961 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 82920.101961 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70354.835468 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70354.835468 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 70442.670742 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70442.670742 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70442.670742 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70442.670742 # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 144965 # number of replacements
system.l2c.tags.tagsinuse 65152.937424 # Cycle average of tags in use
system.l2c.tags.total_refs 609190 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 210433 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.894936 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 94596333000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 6623.641464 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 83.873340 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030778 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 8717.297780 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 6753.906827 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34978.887881 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.032858 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2236.963584 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 3439.697056 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2304.605856 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.101069 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001280 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.133015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.103056 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533735 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.034133 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.052486 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.035165 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.994155 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 31624 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 33792 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 150 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 4711 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 26763 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 52 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 93 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 1870 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 31828 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.482544 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.515625 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 6850011 # Number of tag accesses
system.l2c.tags.data_accesses 6850011 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 269158 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 269158 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 42928 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 5622 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 48550 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 2743 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 2305 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 5048 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 4279 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 1522 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 5801 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 596 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 96 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 68829 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 63546 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47286 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 133 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 12 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 32119 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 13663 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5831 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 232111 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 596 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 96 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 68829 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 67825 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 47286 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 133 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 12 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 32119 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 15185 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 5831 # number of demand (read+write) hits
system.l2c.demand_hits::total 237912 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 596 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 96 # number of overall hits
system.l2c.overall_hits::cpu0.inst 68829 # number of overall hits
system.l2c.overall_hits::cpu0.data 67825 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 47286 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 133 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 12 # number of overall hits
system.l2c.overall_hits::cpu1.inst 32119 # number of overall hits
system.l2c.overall_hits::cpu1.data 15185 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 5831 # number of overall hits
system.l2c.overall_hits::total 237912 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 404 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 229 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 633 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 106 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 82 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 188 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 11300 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 8634 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 19934 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 147 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 22922 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 9947 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 132993 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 19 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 3492 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 1704 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6343 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 177568 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 147 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 22922 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 21247 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 132993 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 19 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 3492 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 10338 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 6343 # number of demand (read+write) misses
system.l2c.demand_misses::total 197502 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 147 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.inst 22922 # number of overall misses
system.l2c.overall_misses::cpu0.data 21247 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 132993 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 19 # number of overall misses
system.l2c.overall_misses::cpu1.inst 3492 # number of overall misses
system.l2c.overall_misses::cpu1.data 10338 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 6343 # number of overall misses
system.l2c.overall_misses::total 197502 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 7730000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 962500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 8692500 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 689500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 165500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 855000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 1562017000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 830214000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 2392231000 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 21395500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 90000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2310573000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 1198855000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15885174851 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 1721000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 383378500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 272430000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 845052256 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 20918670107 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 21395500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 90000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 2310573000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 2760872000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15885174851 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 1721000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 383378500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 1102644000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 845052256 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 23310901107 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 21395500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 90000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 2310573000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 2760872000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15885174851 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 1721000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 383378500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 1102644000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 845052256 # number of overall miss cycles
system.l2c.overall_miss_latency::total 23310901107 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 269158 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 269158 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 43332 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 5851 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 49183 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 2849 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 2387 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 5236 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 15579 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 10156 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 25735 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 743 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 97 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 91751 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 73493 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 180279 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 152 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 12 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 35611 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 15367 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 12174 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 409679 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 743 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 97 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 91751 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 89072 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180279 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 152 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 12 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 35611 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 25523 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 12174 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 435414 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 743 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 97 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 91751 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 89072 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180279 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 152 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 12 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 35611 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 25523 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 12174 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 435414 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.009323 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.039139 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.012870 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.037206 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.034353 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.035905 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.725335 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.850138 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.774587 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.197847 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.010309 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.249828 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.135346 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.737707 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.098060 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.110887 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.521028 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.433432 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.197847 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.010309 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.249828 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.238537 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.737707 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.098060 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.405046 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.521028 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.453596 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.197847 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.010309 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.249828 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.238537 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.737707 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.098060 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.405046 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.521028 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.453596 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19133.663366 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4203.056769 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 13732.227488 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6504.716981 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2018.292683 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 4547.872340 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138231.592920 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 96156.358582 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 120007.574997 # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 145547.619048 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90000 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 100801.544368 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 120524.278677 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119443.691405 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90578.947368 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 109787.657503 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 159876.760563 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 133225.958695 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 117806.531059 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 145547.619048 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 100801.544368 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 129941.732951 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119443.691405 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90578.947368 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 109787.657503 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 106659.315148 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 133225.958695 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 118028.683796 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 145547.619048 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 100801.544368 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 129941.732951 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119443.691405 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90578.947368 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 109787.657503 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 106659.315148 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 133225.958695 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 118028.683796 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 151 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 4 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs 37.750000 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.writebacks::writebacks 105386 # number of writebacks
system.l2c.writebacks::total 105386 # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 3 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 3 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks 4794 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 4794 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 404 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 229 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 633 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 106 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 82 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 188 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 11300 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 8634 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 19934 # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 147 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22919 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9947 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 132993 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 19 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3492 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1704 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6343 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 177565 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 147 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 22919 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 21247 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 132993 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 19 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 3492 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 10338 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6343 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 197499 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 147 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 22919 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 21247 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 132993 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 19 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 3492 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 10338 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6343 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 197499 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20581 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14421 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 38391 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11757 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 31027 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39851 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26178 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 69418 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 8946500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5034000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 13980500 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2786000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1998500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 4784500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1449017000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 743874000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 2192891000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 19925500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2081229000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1099385000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14555242855 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 1531000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 348458500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 255390000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 781621757 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 19142863612 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 19925500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 2081229000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 2548402000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14555242855 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1531000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 348458500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 999264000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 781621757 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 21335754612 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 19925500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 2081229000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 2548402000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14555242855 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1531000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 348458500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 999264000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 781621757 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 21335754612 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 228848500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4072237500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7748500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2117933000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 6426767500 # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 228848500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4072237500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7748500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2117933000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 6426767500 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.009323 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.039139 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.012870 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.037206 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.034353 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.035905 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.725335 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.850138 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.774587 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.197847 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.249796 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.135346 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737707 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098060 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.110887 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521028 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.433425 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.197847 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.249796 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.238537 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737707 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098060 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.405046 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521028 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.453589 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.197847 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.249796 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.238537 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737707 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098060 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.405046 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521028 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.453589 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22144.801980 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21982.532751 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22086.097946 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26283.018868 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24371.951220 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25449.468085 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128231.592920 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 86156.358582 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 110007.574997 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 110524.278677 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 149876.760563 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 107807.640087 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 119941.732951 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96659.315148 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 108029.684262 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 119941.732951 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96659.315148 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 108029.684262 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197863.927895 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69183.035714 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146864.503155 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167402.972051 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102186.582520 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69183.035714 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80905.072962 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 92580.706733 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 519148 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 291431 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 639 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 38391 # Transaction distribution
system.membus.trans_dist::ReadResp 216211 # Transaction distribution
system.membus.trans_dist::WriteReq 31027 # Transaction distribution
system.membus.trans_dist::WriteResp 31027 # Transaction distribution
system.membus.trans_dist::WritebackDirty 141592 # Transaction distribution
system.membus.trans_dist::CleanEvict 19995 # Transaction distribution
system.membus.trans_dist::UpgradeReq 63966 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 38983 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
system.membus.trans_dist::ReadExReq 40431 # Transaction distribution
system.membus.trans_dist::ReadExResp 19912 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 177820 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::InvalidateResp 4302 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14192 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659894 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 782044 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 854999 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28384 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19597036 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 19789560 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22107704 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 127509 # Total snoops (count)
system.membus.snoopTraffic 37120 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 426843 # Request fanout histogram
system.membus.snoop_fanout::mean 0.011580 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.106987 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 421900 98.84% 98.84% # Request fanout histogram
system.membus.snoop_fanout::1 4943 1.16% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 426843 # Request fanout histogram
system.membus.reqLayer0.occupancy 94581999 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 12496000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 1014639485 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 1151195264 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 6864902 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 1123711 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 579018 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 224775 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 30515 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 29083 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 1432 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 38394 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 569470 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 31027 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 31027 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 374544 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 155002 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 112494 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 44031 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 156525 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 34 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 51717 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 51717 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 531080 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 4357 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 3099 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1346867 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 408809 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1755676 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 38391932 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7144124 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 45536056 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 402215 # Total snoops (count)
system.toL2Bus.snoopTraffic 16179148 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 958128 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.409221 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.494721 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 567474 59.23% 59.23% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 389222 40.62% 99.85% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 1432 0.15% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 958128 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 954442443 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 1977326 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 723838248 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 286417681 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
|