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|
---------- Begin Simulation Statistics ----------
sim_seconds 2.846097 # Number of seconds simulated
sim_ticks 2846097440000 # Number of ticks simulated
final_tick 2846097440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 101530 # Simulator instruction rate (inst/s)
host_op_rate 122947 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2278332577 # Simulator tick rate (ticks/s)
host_mem_usage 584920 # Number of bytes of host memory used
host_seconds 1249.20 # Real time elapsed on the host
sim_insts 126830911 # Number of instructions simulated
sim_ops 153585651 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 9344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1671232 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 1335292 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 8458880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 217280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 606496 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 432576 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 12733532 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1671232 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 217280 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1888512 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8840256 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
system.physmem.bytes_written::total 8858000 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 146 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 26113 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 21389 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 132170 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 3395 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 9500 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 6759 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 199510 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 138129 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
system.physmem.num_writes::total 142565 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 3283 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 587201 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 469166 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 2972098 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 472 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 76343 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 213097 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 151989 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4474032 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 587201 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 76343 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 663544 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3106097 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6220 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3112332 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3106097 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 3283 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 587201 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 475386 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 2972098 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 472 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 76343 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 213111 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 151989 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7586364 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 199510 # Number of read requests accepted
system.physmem.writeReqs 178789 # Number of write requests accepted
system.physmem.readBursts 199510 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 178789 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 12761024 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue
system.physmem.bytesWritten 9911424 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 12733532 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 11176336 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 23895 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 14191 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 12377 # Per bank write bursts
system.physmem.perBankRdBursts::1 12507 # Per bank write bursts
system.physmem.perBankRdBursts::2 12921 # Per bank write bursts
system.physmem.perBankRdBursts::3 12944 # Per bank write bursts
system.physmem.perBankRdBursts::4 15059 # Per bank write bursts
system.physmem.perBankRdBursts::5 12345 # Per bank write bursts
system.physmem.perBankRdBursts::6 13163 # Per bank write bursts
system.physmem.perBankRdBursts::7 13279 # Per bank write bursts
system.physmem.perBankRdBursts::8 12255 # Per bank write bursts
system.physmem.perBankRdBursts::9 12304 # Per bank write bursts
system.physmem.perBankRdBursts::10 12058 # Per bank write bursts
system.physmem.perBankRdBursts::11 11233 # Per bank write bursts
system.physmem.perBankRdBursts::12 11543 # Per bank write bursts
system.physmem.perBankRdBursts::13 12301 # Per bank write bursts
system.physmem.perBankRdBursts::14 11677 # Per bank write bursts
system.physmem.perBankRdBursts::15 11425 # Per bank write bursts
system.physmem.perBankWrBursts::0 9896 # Per bank write bursts
system.physmem.perBankWrBursts::1 10159 # Per bank write bursts
system.physmem.perBankWrBursts::2 10174 # Per bank write bursts
system.physmem.perBankWrBursts::3 9995 # Per bank write bursts
system.physmem.perBankWrBursts::4 9156 # Per bank write bursts
system.physmem.perBankWrBursts::5 9568 # Per bank write bursts
system.physmem.perBankWrBursts::6 10283 # Per bank write bursts
system.physmem.perBankWrBursts::7 10373 # Per bank write bursts
system.physmem.perBankWrBursts::8 9590 # Per bank write bursts
system.physmem.perBankWrBursts::9 9571 # Per bank write bursts
system.physmem.perBankWrBursts::10 9719 # Per bank write bursts
system.physmem.perBankWrBursts::11 9542 # Per bank write bursts
system.physmem.perBankWrBursts::12 9254 # Per bank write bursts
system.physmem.perBankWrBursts::13 9350 # Per bank write bursts
system.physmem.perBankWrBursts::14 9412 # Per bank write bursts
system.physmem.perBankWrBursts::15 8824 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 38 # Number of times write queue was full causing retry
system.physmem.totGap 2846096933500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 559 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 198923 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4436 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 174353 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 98295 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 47940 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 13231 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 9850 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7837 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 6409 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 5336 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 4702 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 4182 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 765 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 268 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 250 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 168 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 153 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2534 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3771 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4787 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5445 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6062 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6493 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7082 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7379 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7734 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9231 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8142 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8296 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 10951 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 8932 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 8227 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7988 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1408 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1340 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1453 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 2379 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 2537 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1912 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1868 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 2527 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1779 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1855 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1708 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1845 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1734 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1253 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1386 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 999 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 773 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 467 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 316 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 221 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 195 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 211 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 157 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 142 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 115 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 100 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 145 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 90716 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 249.927069 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 140.222601 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 310.362875 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 47359 52.21% 52.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 17889 19.72% 71.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6289 6.93% 78.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3581 3.95% 82.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2839 3.13% 85.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1568 1.73% 87.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 985 1.09% 88.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1019 1.12% 89.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 9187 10.13% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 90716 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6524 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 30.562538 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 556.578248 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6523 99.98% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6524 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6524 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 23.737891 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.670801 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 40.283485 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31 6175 94.65% 94.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47 90 1.38% 96.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63 23 0.35% 96.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79 12 0.18% 96.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95 26 0.40% 96.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111 32 0.49% 97.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127 26 0.40% 97.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143 10 0.15% 98.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159 20 0.31% 98.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175 5 0.08% 98.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191 20 0.31% 98.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207 23 0.35% 99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223 7 0.11% 99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239 7 0.11% 99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255 1 0.02% 99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271 3 0.05% 99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287 2 0.03% 99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303 5 0.08% 99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319 4 0.06% 99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351 4 0.06% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367 14 0.21% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399 2 0.03% 99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::400-415 1 0.02% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::464-479 1 0.02% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511 2 0.03% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527 2 0.03% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543 3 0.05% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::576-591 1 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::720-735 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6524 # Writes before turning the bus around for reads
system.physmem.totQLat 5679096455 # Total ticks spent queuing
system.physmem.totMemAccLat 9417677705 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 996955000 # Total ticks spent in databus transfers
system.physmem.avgQLat 28482.21 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 47232.21 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.48 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.47 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.18 # Average write queue length when enqueuing
system.physmem.readRowHits 166067 # Number of row buffer hits during reads
system.physmem.writeRowHits 97473 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 62.93 # Row buffer hit rate for writes
system.physmem.avgGap 7523405.91 # Average gap between requests
system.physmem.pageHitRate 74.39 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 359115120 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 195945750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 815841000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 515833920 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 185892919680 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 83249453610 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1634629745250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1905658854330 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.570214 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2719227401175 # Time in different power states
system.physmem_0.memoryStateTime::REF 95037280000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 31827968825 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 326697840 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 178257750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 739401000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 487697760 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 185892919680 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 82096607520 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1635641013750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1905362595300 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.466120 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2720918284391 # Time in different power states
system.physmem_1.memoryStateTime::REF 95037280000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 30141762609 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 157 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 427 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 157 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 427 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 157 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 427 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 20630955 # Number of BP lookups
system.cpu0.branchPred.condPredicted 13593557 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 1040069 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 13124579 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 9315197 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 70.975206 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 3367508 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 204886 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 69457 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 69457 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46535 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22922 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples 69457 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 69457 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 69457 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 6849 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 9469.922616 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 8283.824538 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 6457.338241 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383 6642 96.98% 96.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767 191 2.79% 99.77% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.85% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.10% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 6849 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 5259 76.78% 76.78% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1590 23.22% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 6849 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69457 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69457 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6849 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6849 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 76306 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 17312533 # DTB read hits
system.cpu0.dtb.read_misses 63301 # DTB read misses
system.cpu0.dtb.write_hits 14536158 # DTB write hits
system.cpu0.dtb.write_misses 6156 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3522 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1254 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 1942 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 17375834 # DTB read accesses
system.cpu0.dtb.write_accesses 14542314 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 31848691 # DTB hits
system.cpu0.dtb.misses 69457 # DTB misses
system.cpu0.dtb.accesses 31918148 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 3833 # Table walker walks requested
system.cpu0.itb.walker.walksShort 3833 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3526 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples 3833 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 3833 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 3833 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 2419 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 9485.117817 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 8378.584027 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 4911.792845 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191 918 37.95% 37.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383 1466 60.60% 98.55% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575 5 0.21% 98.76% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767 29 1.20% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 2419 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 2119 87.60% 87.60% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 300 12.40% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2419 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3833 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3833 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2419 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2419 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 6252 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 38694088 # ITB inst hits
system.cpu0.itb.inst_misses 3833 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2222 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 7309 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 38697921 # ITB inst accesses
system.cpu0.itb.hits 38694088 # DTB hits
system.cpu0.itb.misses 3833 # DTB misses
system.cpu0.itb.accesses 38697921 # DTB accesses
system.cpu0.numCycles 164664294 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 79545676 # Number of instructions committed
system.cpu0.committedOps 95726645 # Number of ops (including micro ops) committed
system.cpu0.discardedOps 5037895 # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends 1845 # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles 5527555817 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi 2.070060 # CPI: cycles per instruction
system.cpu0.ipc 0.483078 # IPC: instructions per cycle
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 1847 # number of quiesce instructions executed
system.cpu0.tickCycles 127989646 # Number of cycles that the object actually ticked
system.cpu0.idleCycles 36674648 # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements 713904 # number of replacements
system.cpu0.dcache.tags.tagsinuse 500.482804 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 30358451 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 714416 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 42.494080 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 348749500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.482804 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977505 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.977505 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 63703980 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 63703980 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 15781686 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 15781686 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 13418199 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 13418199 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321521 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 321521 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365596 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 365596 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361488 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 361488 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 29199885 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 29199885 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 29521406 # number of overall hits
system.cpu0.dcache.overall_hits::total 29521406 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 463568 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 463568 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 577310 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 577310 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136519 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 136519 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21073 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 21073 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20283 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 20283 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1040878 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1040878 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1177397 # number of overall misses
system.cpu0.dcache.overall_misses::total 1177397 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6134841542 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 6134841542 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9140419725 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 9140419725 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 317623227 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 317623227 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453858268 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 453858268 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 454500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 454500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 15275261267 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 15275261267 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 15275261267 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 15275261267 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 16245254 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 16245254 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 13995509 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 13995509 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 458040 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 458040 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386669 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 386669 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381771 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 381771 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 30240763 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 30240763 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 30698803 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 30698803 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028536 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.028536 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041250 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.041250 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298050 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298050 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054499 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054499 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053129 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053129 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034420 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.034420 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038353 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.038353 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13233.962530 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13233.962530 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15832.775675 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15832.775675 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15072.520619 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15072.520619 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22376.288912 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22376.288912 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14675.361826 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14675.361826 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12973.755893 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12973.755893 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 513522 # number of writebacks
system.cpu0.dcache.writebacks::total 513522 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 72271 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 72271 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 253439 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 253439 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14656 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14656 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 325710 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 325710 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 325710 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 325710 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391297 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 391297 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323871 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 323871 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103394 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 103394 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6417 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6417 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20283 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 20283 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 715168 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 715168 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 818562 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 818562 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4428376943 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4428376943 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4906976685 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4906976685 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1616801678 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1616801678 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 95832009 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95832009 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 422721232 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 422721232 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 436500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 436500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9335353628 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 9335353628 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10952155306 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 10952155306 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276481750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276481750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3261665000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3261665000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7538146750 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7538146750 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024087 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024087 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023141 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023141 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225731 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225731 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016596 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016596 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053129 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053129 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023649 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.023649 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026664 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.026664 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11317.175810 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11317.175810 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15151.022120 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15151.022120 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15637.287251 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15637.287251 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14934.082749 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14934.082749 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20841.159197 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20841.159197 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13053.371555 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13053.371555 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13379.750472 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13379.750472 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 1969157 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.783924 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 36716761 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1969669 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 18.641082 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6455779250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.783924 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999578 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 79342579 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 79342579 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 36716761 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 36716761 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 36716761 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 36716761 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 36716761 # number of overall hits
system.cpu0.icache.overall_hits::total 36716761 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1969686 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1969686 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1969686 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1969686 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1969686 # number of overall misses
system.cpu0.icache.overall_misses::total 1969686 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18594001543 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 18594001543 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 18594001543 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 18594001543 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 18594001543 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 18594001543 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 38686447 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 38686447 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 38686447 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 38686447 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 38686447 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 38686447 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050914 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.050914 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050914 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.050914 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050914 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.050914 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9440.084127 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 9440.084127 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9440.084127 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 9440.084127 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9440.084127 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 9440.084127 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1969686 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1969686 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 1969686 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1969686 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 1969686 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1969686 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16614994457 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 16614994457 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16614994457 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 16614994457 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16614994457 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 16614994457 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 312159000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 312159000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 312159000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 312159000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050914 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050914 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050914 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.050914 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050914 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.050914 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8435.351857 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8435.351857 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8435.351857 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 8435.351857 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8435.351857 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 8435.351857 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1838342 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 1838481 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 119 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 233119 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 300411 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16152.844833 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 2914098 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 316661 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 9.202579 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 2826281697500 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 6746.773874 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 56.784036 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.060323 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5767.067703 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1954.184068 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1627.974828 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.411790 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003466 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.351994 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119274 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.099364 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.985891 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1019 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15218 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 323 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 417 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 268 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4291 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7836 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2805 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062195 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.928833 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 55319704 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 55319704 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 80908 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4161 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1898400 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data 400606 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 2384075 # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks 513519 # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total 513519 # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28702 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 28702 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1838 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 1838 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 223052 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 223052 # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 80908 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4161 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1898400 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 623658 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 2607127 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 80908 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4161 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1898400 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 623658 # number of overall hits
system.cpu0.l2cache.overall_hits::total 2607127 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 892 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 113 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst 71286 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data 100496 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 172787 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26801 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 26801 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45324 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 45324 # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 892 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 113 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 71286 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 145820 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 218111 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 892 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 113 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 71286 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 145820 # number of overall misses
system.cpu0.l2cache.overall_misses::total 218111 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 31644248 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2618496 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 3281889931 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 3018329920 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 6334482595 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 498950782 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 498950782 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 372929796 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 372929796 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 423999 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 423999 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2226350926 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 2226350926 # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 31644248 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2618496 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3281889931 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 5244680846 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 8560833521 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 31644248 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2618496 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3281889931 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 5244680846 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 8560833521 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 81800 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4274 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1969686 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data 501102 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 2556862 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks 513519 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total 513519 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55503 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 55503 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20282 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 20282 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 268376 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 268376 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 81800 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4274 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1969686 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 769478 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 2825238 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 81800 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4274 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1969686 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 769478 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 2825238 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010905 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.026439 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.036192 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.200550 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.067578 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.482875 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.482875 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.909378 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.909378 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.168882 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.168882 # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010905 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.026439 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.036192 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.189505 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.077201 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010905 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.026439 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.036192 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.189505 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.077201 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35475.614350 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23172.530973 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46038.351584 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 30034.328929 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36660.643422 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18616.871833 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18616.871833 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20219.572544 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20219.572544 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 423999 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 423999 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49120.795296 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49120.795296 # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35475.614350 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23172.530973 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46038.351584 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35966.814196 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 39249.893499 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35475.614350 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23172.530973 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46038.351584 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35966.814196 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 39249.893499 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 13 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks 200740 # number of writebacks
system.cpu0.l2cache.writebacks::total 200740 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 77 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 418 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 495 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3009 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 3009 # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 77 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3427 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 3504 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 77 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3427 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 3504 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 892 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 113 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 71209 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 100078 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 172292 # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 246246 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 246246 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26801 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26801 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18444 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18444 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42315 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 42315 # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 892 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 113 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 71209 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142393 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 214607 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 892 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 113 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 71209 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142393 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 246246 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 460853 # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25830750 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1882000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2808366569 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2341826150 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5177905469 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14395344158 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14395344158 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 540640009 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 540640009 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 270568831 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 270568831 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 345999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 345999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1615514460 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1615514460 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25830750 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1882000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2808366569 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3957340610 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 6793419929 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25830750 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1882000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2808366569 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3957340610 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14395344158 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 21188764087 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 283536500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4113067750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4396604250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3117904500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3117904500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 283536500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7230972250 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7514508750 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010905 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.026439 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.036152 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.199716 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.067384 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.482875 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.482875 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.909378 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.909378 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157671 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157671 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010905 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.026439 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036152 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.185051 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075961 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010905 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.026439 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036152 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.185051 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163120 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23400.009493 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30053.081217 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58459.199979 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58459.199979 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20172.381963 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20172.381963 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14669.747940 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14669.747940 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 345999 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 345999 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38178.292804 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38178.292804 # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27791.679436 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31655.164692 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27791.679436 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58459.199979 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45977.272768 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq 2703667 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 2643606 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 19130 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 19130 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback 513519 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 304285 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 88848 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42983 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 113085 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 297594 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 284124 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3946133 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2385460 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11633 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174179 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 6517405 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126276224 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86385120 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17096 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 327200 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 213005640 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 651207 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 3963380 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 3.135029 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.341755 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 3428208 86.50% 86.50% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 535172 13.50% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 3963380 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 2258643996 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 116241999 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 2965047043 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 1230256203 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 7364491 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 92392742 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 18842889 # Number of BP lookups
system.cpu1.branchPred.condPredicted 6205402 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 629106 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 9920552 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 7177439 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 72.349190 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 8245946 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 413041 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 26188 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 26188 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19132 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7056 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples 26188 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 26188 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 26188 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 2719 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 9780.159618 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 8826.212048 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 5631.617808 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191 919 33.80% 33.80% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1662 61.13% 94.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575 68 2.50% 97.43% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767 62 2.28% 99.71% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.78% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.11% 99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.07% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 2719 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 1631340764 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1631340764 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 1631340764 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 2011 73.96% 73.96% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 708 26.04% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 2719 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26188 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26188 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2719 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2719 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 28907 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 11112548 # DTB read hits
system.cpu1.dtb.read_misses 24192 # DTB read misses
system.cpu1.dtb.write_hits 6961122 # DTB write hits
system.cpu1.dtb.write_misses 1996 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 2061 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 278 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 11136740 # DTB read accesses
system.cpu1.dtb.write_accesses 6963118 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 18073670 # DTB hits
system.cpu1.dtb.misses 26188 # DTB misses
system.cpu1.dtb.accesses 18099858 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 2252 # Table walker walks requested
system.cpu1.itb.walker.walksShort 2252 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2071 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 2252 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 2252 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 2252 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 1119 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 9763.181412 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 8935.720507 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 4528.605471 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-4095 139 12.42% 12.42% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191 170 15.19% 27.61% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287 525 46.92% 74.53% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383 253 22.61% 97.14% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479 2 0.18% 97.32% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.88% 99.20% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.63% 99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 1119 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 1630766264 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1630766264 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1630766264 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 951 84.99% 84.99% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 168 15.01% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 1119 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2252 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2252 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1119 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1119 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 3371 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 39781680 # ITB inst hits
system.cpu1.itb.inst_misses 2252 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 1157 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 1899 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 39783932 # ITB inst accesses
system.cpu1.itb.hits 39781680 # DTB hits
system.cpu1.itb.misses 2252 # DTB misses
system.cpu1.itb.accesses 39783932 # DTB accesses
system.cpu1.numCycles 114623988 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 47285235 # Number of instructions committed
system.cpu1.committedOps 57859006 # Number of ops (including micro ops) committed
system.cpu1.discardedOps 5005620 # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends 2776 # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles 5576963738 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi 2.424097 # CPI: cycles per instruction
system.cpu1.ipc 0.412525 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2776 # number of quiesce instructions executed
system.cpu1.tickCycles 97884766 # Number of cycles that the object actually ticked
system.cpu1.idleCycles 16739222 # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements 194739 # number of replacements
system.cpu1.dcache.tags.tagsinuse 472.948438 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 17633406 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 195100 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 90.381374 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 90504077500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.948438 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923727 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.923727 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 55 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.705078 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 36178407 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 36178407 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 10725883 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 10725883 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 6668052 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 6668052 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49984 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 49984 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80051 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 80051 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71499 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 71499 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 17393935 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 17393935 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 17443919 # number of overall hits
system.cpu1.dcache.overall_hits::total 17443919 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 157968 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 157968 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 144726 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 144726 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30816 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 30816 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16919 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 16919 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23678 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 23678 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 302694 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 302694 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 333510 # number of overall misses
system.cpu1.dcache.overall_misses::total 333510 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2315952429 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 2315952429 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3861386324 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 3861386324 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316030492 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 316030492 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557062155 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 557062155 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 124000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 124000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 6177338753 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 6177338753 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 6177338753 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 6177338753 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 10883851 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 10883851 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 6812778 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 6812778 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80800 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 80800 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96970 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 96970 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95177 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 95177 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 17696629 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 17696629 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 17777429 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 17777429 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014514 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.014514 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021243 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.021243 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381386 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381386 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174477 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174477 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248779 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248779 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.017105 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.017105 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018760 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.018760 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14660.896061 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14660.896061 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26680.667772 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 26680.667772 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18679.029021 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18679.029021 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23526.571290 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23526.571290 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20407.866535 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20407.866535 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18522.199493 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18522.199493 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 119475 # number of writebacks
system.cpu1.dcache.writebacks::total 119475 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16075 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 16075 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52265 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 52265 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12035 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12035 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 68340 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 68340 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 68340 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 68340 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 141893 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 141893 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92461 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 92461 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29935 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 29935 # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4884 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4884 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23678 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 23678 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 234354 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 234354 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 264289 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 264289 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1871458583 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1871458583 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2300176813 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2300176813 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 487265761 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 487265761 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79878753 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79878753 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 520207345 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 520207345 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 119500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 119500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4171635396 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4171635396 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4658901157 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 4658901157 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2322015751 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322015751 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1843986000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1843986000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4166001751 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166001751 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013037 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013037 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013572 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013572 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.370483 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.370483 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050366 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050366 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248779 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248779 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013243 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.013243 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014867 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.014867 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13189.224155 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13189.224155 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24877.265150 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24877.265150 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16277.459863 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16277.459863 # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16355.191032 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16355.191032 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21970.071163 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21970.071163 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17800.572621 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17800.572621 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17628.055488 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17628.055488 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 947666 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.322678 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 38831450 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 948178 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 40.953756 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 72138919500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.322678 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975240 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.975240 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 80507434 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 80507434 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 38831450 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 38831450 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 38831450 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 38831450 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 38831450 # number of overall hits
system.cpu1.icache.overall_hits::total 38831450 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 948178 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 948178 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 948178 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 948178 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 948178 # number of overall misses
system.cpu1.icache.overall_misses::total 948178 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8186316171 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 8186316171 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 8186316171 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 8186316171 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 8186316171 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 8186316171 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 39779628 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 39779628 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 39779628 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 39779628 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 39779628 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 39779628 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023836 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.023836 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023836 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.023836 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023836 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.023836 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8633.733509 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 8633.733509 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8633.733509 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 8633.733509 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8633.733509 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 8633.733509 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 948178 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 948178 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 948178 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 948178 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 948178 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 948178 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7236829829 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 7236829829 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7236829829 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 7236829829 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7236829829 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 7236829829 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10429000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10429000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10429000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 10429000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023836 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023836 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023836 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.023836 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023836 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.023836 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7632.353660 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 7632.353660 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 7632.353660 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued 198185 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 198250 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 56 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 58438 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 54866 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 15346.205956 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 1177923 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 69767 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 16.883670 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 7899.614060 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 43.616627 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.093163 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4379.239024 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2180.842140 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 842.800943 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.482154 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002662 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.267288 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.133108 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051440 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.936658 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1047 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13803 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 662 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 384 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6041 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7452 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.063904 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.842468 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 22495354 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 22495354 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28402 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2611 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst 927201 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data 105616 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 1063830 # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks 119475 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 119475 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1556 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 1556 # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 974 # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total 974 # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28114 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 28114 # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28402 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2611 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 927201 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 133730 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 1091944 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28402 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2611 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 927201 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 133730 # number of overall hits
system.cpu1.l2cache.overall_hits::total 1091944 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 655 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 221 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst 20977 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data 71094 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 92947 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28365 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 28365 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22703 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 22703 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34428 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 34428 # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 655 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 221 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 20977 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 105522 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 127375 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 655 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 221 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 20977 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 105522 # number of overall misses
system.cpu1.l2cache.overall_misses::total 127375 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 15088235 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4439998 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 733507240 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1569643994 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 2322679467 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536973358 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 536973358 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 458518574 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 458518574 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 116500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 116500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1375727201 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 1375727201 # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 15088235 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4439998 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 733507240 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 2945371195 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 3698406668 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 15088235 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4439998 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 733507240 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 2945371195 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 3698406668 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29057 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2832 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 948178 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data 176710 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 1156777 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 119475 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 119475 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29921 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 29921 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23677 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 23677 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62542 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 62542 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29057 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2832 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 948178 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 239252 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 1219319 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29057 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2832 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 948178 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 239252 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 1219319 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022542 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.078037 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.022123 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.402320 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.080350 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.947996 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.947996 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.958863 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.958863 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.550478 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.550478 # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022542 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.078037 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.022123 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.441050 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.104464 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022542 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.078037 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.022123 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.441050 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.104464 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23035.473282 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20090.488688 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34967.213615 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22078.431288 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24989.289240 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18930.842870 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18930.842870 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20196.386997 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20196.386997 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 116500 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 116500 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39959.544586 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39959.544586 # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23035.473282 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20090.488688 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34967.213615 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27912.389786 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 29035.577374 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23035.473282 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20090.488688 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34967.213615 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27912.389786 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 29035.577374 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 66 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 33 # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks 32095 # number of writebacks
system.cpu1.l2cache.writebacks::total 32095 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 29 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 84 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 230 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 230 # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 29 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 314 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 343 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 29 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 314 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 343 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 655 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 221 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 20948 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 71010 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 92834 # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 23894 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 23894 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28365 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28365 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22703 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22703 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34198 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 34198 # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 655 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 221 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 20948 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 105208 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 127032 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 655 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 221 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 20948 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 105208 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 23894 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 150926 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 10825243 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3002500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 595509510 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1105908750 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1715246003 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1009576164 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1009576164 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 452138519 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 452138519 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 342402748 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 342402748 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 97000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 97000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1121062806 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1121062806 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 10825243 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3002500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 595509510 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2226971556 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 2836308809 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 10825243 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3002500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 595509510 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2226971556 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1009576164 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 3845884973 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9469000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2205184749 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2214653749 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1754353500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1754353500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9469000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3959538249 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3969007249 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.401845 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.080252 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.947996 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947996 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.958863 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.958863 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.546801 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.546801 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439737 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.104183 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439737 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.123779 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15573.986058 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18476.484941 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42252.287771 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 42252.287771 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15940.014772 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15940.014772 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15081.828305 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15081.828305 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 97000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 97000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32781.531259 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32781.531259 # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21167.321458 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22327.514398 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21167.321458 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42252.287771 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25481.924738 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq 1546268 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 1215347 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 11936 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 11936 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback 119475 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 29668 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 76508 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42110 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 86467 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 85086 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 67037 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1896584 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 833808 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7155 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62301 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 2799848 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60690688 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25792980 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11328 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 116228 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 86611224 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 603822 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 1920664 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 3.272089 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.445035 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 1398073 72.79% 72.79% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 522591 27.21% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 1920664 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 837814982 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 80458500 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 1423116171 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 410915491 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 4323500 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 33252737 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 31003 # Transaction distribution
system.iobus.trans_dist::ReadResp 31003 # Transaction distribution
system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
system.iobus.trans_dist::WriteResp 23198 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 198973953 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36786758 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36449 # number of replacements
system.iocache.tags.tagsinuse 14.479940 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 270378265000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.479940 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.904996 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.904996 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328203 # Number of tag accesses
system.iocache.tags.data_accesses 328203 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses
system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses
system.iocache.demand_misses::total 243 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 243 # number of overall misses
system.iocache.overall_misses::total 243 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 31380127 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 31380127 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6638963068 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 6638963068 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide 31380127 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 31380127 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 31380127 # number of overall miss cycles
system.iocache.overall_miss_latency::total 31380127 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 129136.325103 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 129136.325103 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183275.261374 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 183275.261374 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 129136.325103 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 129136.325103 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 129136.325103 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 129136.325103 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 22458 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 3415 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 6.576281 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 36206 # number of writebacks
system.iocache.writebacks::total 36206 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 18685627 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 18685627 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4755299084 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4755299084 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 18685627 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 18685627 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 18685627 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 18685627 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76895.584362 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76895.584362 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131274.820119 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131274.820119 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76895.584362 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76895.584362 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76895.584362 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76895.584362 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 135638 # number of replacements
system.l2c.tags.tagsinuse 64035.864385 # Cycle average of tags in use
system.l2c.tags.total_refs 380564 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 200114 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 1.901736 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 12087.017372 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 77.160254 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.033685 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 8509.496822 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2877.165248 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35676.414678 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 13.500349 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2186.391247 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 567.991773 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2040.692959 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.184433 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001177 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.129845 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.043902 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544379 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000206 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.033362 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.008667 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.031139 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.977110 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 30037 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 34391 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 135 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 4776 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 25126 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 3317 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 30762 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.458328 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.524765 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 5287806 # Number of tag accesses
system.l2c.tags.data_accesses 5287806 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 444 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 48461 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 49558 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 47653 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 127 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 25 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 17654 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 9320 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5533 # number of ReadReq hits
system.l2c.ReadReq_hits::total 178838 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 232835 # number of Writeback hits
system.l2c.Writeback_hits::total 232835 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3130 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 650 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 3780 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 173 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 165 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 338 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 4192 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 1733 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 5925 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 444 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 48461 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 53750 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 47653 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 127 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 25 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 17654 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 11053 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 5533 # number of demand (read+write) hits
system.l2c.demand_hits::total 184763 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 444 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits
system.l2c.overall_hits::cpu0.inst 48461 # number of overall hits
system.l2c.overall_hits::cpu0.data 53750 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 47653 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 127 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 25 # number of overall hits
system.l2c.overall_hits::cpu1.inst 17654 # number of overall hits
system.l2c.overall_hits::cpu1.data 11053 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 5533 # number of overall hits
system.l2c.overall_hits::total 184763 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 146 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 22747 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 9845 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 132327 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 21 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 3294 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 1096 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 6759 # number of ReadReq misses
system.l2c.ReadReq_misses::total 176237 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 9250 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 2916 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 12166 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 671 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 1253 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1924 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 11244 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 8399 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 19643 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 146 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 22747 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 21089 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 132327 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 21 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 3294 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 9495 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 6759 # number of demand (read+write) misses
system.l2c.demand_misses::total 195880 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 146 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
system.l2c.overall_misses::cpu0.inst 22747 # number of overall misses
system.l2c.overall_misses::cpu0.data 21089 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 132327 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 21 # number of overall misses
system.l2c.overall_misses::cpu1.inst 3294 # number of overall misses
system.l2c.overall_misses::cpu1.data 9495 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 6759 # number of overall misses
system.l2c.overall_misses::total 195880 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 13322250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 165000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 1836389560 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 869862901 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13647658866 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1878250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 273761254 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 100369500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 908948741 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 17652356322 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 7104776 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 3030406 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 10135182 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1032472 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1498952 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 2531424 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 1028146684 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 690374730 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 1718521414 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 13322250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 165000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 1836389560 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 1898009585 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13647658866 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 1878250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 273761254 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 790744230 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 908948741 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 19370877736 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 13322250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 165000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 1836389560 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 1898009585 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13647658866 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 1878250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 273761254 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 790744230 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 908948741 # number of overall miss cycles
system.l2c.overall_miss_latency::total 19370877736 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 590 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 71208 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 59403 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 179980 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 148 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 25 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 20948 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 10416 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 12292 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 355075 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 232835 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 232835 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 12380 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 3566 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 15946 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 844 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 1418 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 2262 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 15436 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 10132 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 25568 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 590 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 71208 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 74839 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179980 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 148 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 25 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 20948 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 20548 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 12292 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 380643 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 590 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 71208 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 74839 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179980 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 148 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 25 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 20948 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 20548 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 12292 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 380643 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.247458 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.319444 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.165732 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.735232 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.141892 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.157247 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.105223 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.549870 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.496337 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.747173 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.817723 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.762950 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.795024 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.883639 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.850575 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.728427 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.828958 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.768265 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.247458 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.319444 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.281792 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.735232 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.141892 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.157247 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.462089 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.549870 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.514603 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.247458 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.319444 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.281792 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.735232 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.141892 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.157247 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.462089 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.549870 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.514603 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 91248.287671 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82500 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80731.066075 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 88355.805079 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 103135.859394 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89440.476190 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83109.063145 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 91578.010949 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 134479.766386 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 100162.601054 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 768.083892 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1039.233882 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 833.074305 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1538.706408 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1196.290503 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 1315.708940 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91439.584134 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82197.253244 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 87487.726620 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 91248.287671 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 80731.066075 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 89999.980321 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 103135.859394 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89440.476190 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 83109.063145 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 83280.066351 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134479.766386 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 98891.554707 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 91248.287671 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 80731.066075 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 89999.980321 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 103135.859394 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89440.476190 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 83109.063145 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 83280.066351 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134479.766386 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 98891.554707 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 101923 # number of writebacks
system.l2c.writebacks::total 101923 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 146 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst 22742 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 9845 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 132327 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 21 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 3293 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 1095 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 6759 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 176230 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 9250 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 2916 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 12166 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 671 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1253 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1924 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 11244 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 8399 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 19643 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 146 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 22742 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 21089 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 132327 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 21 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 3293 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 9494 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6759 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 195873 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 146 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 22742 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 21089 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 132327 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 21 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 3293 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 9494 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6759 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 195873 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 11489750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 140000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1551174190 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 746786599 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12016886672 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1614750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 232356996 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 86604500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 826146057 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 15473199514 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 164200724 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 51784907 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 215985631 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12008669 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22268252 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 34276921 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 889143316 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 585339270 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1474482586 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 11489750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 140000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 1551174190 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 1635929915 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12016886672 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1614750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 232356996 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 671943770 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 826146057 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 16947682100 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 11489750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 140000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 1551174190 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 1635929915 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12016886672 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1614750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 232356996 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 671943770 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 826146057 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 16947682100 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 205778000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3714619750 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6850000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919856251 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 5847104001 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2763444000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1533087000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 4296531000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 205778000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6478063750 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6850000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3452943251 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 10143635001 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.247458 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.319374 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.165732 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735232 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.141892 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.157199 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.105127 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.549870 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.496318 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.747173 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.817723 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.762950 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.795024 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.883639 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850575 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.728427 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.828958 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.768265 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.247458 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.319374 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.281792 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735232 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.141892 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.157199 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.462040 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.549870 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.514585 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.247458 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319374 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.281792 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735232 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.141892 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.157199 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.462040 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.549870 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.514585 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75854.403149 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79090.867580 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 87801.166169 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17751.429622 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17758.884431 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17753.216423 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17896.675112 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17771.948923 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.447505 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79077.135895 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69691.543041 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 75064.022094 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77572.664185 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70775.623552 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 86523.829726 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77572.664185 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70775.623552 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 86523.829726 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 214962 # Transaction distribution
system.membus.trans_dist::ReadResp 214962 # Transaction distribution
system.membus.trans_dist::WriteReq 31066 # Transaction distribution
system.membus.trans_dist::WriteResp 31066 # Transaction distribution
system.membus.trans_dist::Writeback 138129 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.membus.trans_dist::UpgradeReq 76255 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 40796 # Transaction distribution
system.membus.trans_dist::UpgradeResp 14193 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution
system.membus.trans_dist::ReadExReq 40018 # Transaction distribution
system.membus.trans_dist::ReadExResp 19540 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14158 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661851 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 783963 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108912 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108912 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 892875 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28316 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19273388 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 19465716 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 24102196 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 123912 # Total snoops (count)
system.membus.snoop_fanout::samples 507941 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 507941 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 507941 # Request fanout histogram
system.membus.reqLayer0.occupancy 88612000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 12528499 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 1167691410 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 1172073016 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 37476242 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.trans_dist::ReadReq 516720 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 516705 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 31066 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 31066 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 232835 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 79932 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 41134 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 121066 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 51762 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 51762 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1083099 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 338756 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1421855 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34093856 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5618324 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 39712180 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 288702 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 920160 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.039660 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.195160 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 883666 96.03% 96.03% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 36494 3.97% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 920160 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 787000770 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 342000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 681574777 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 259216519 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
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