path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.846107                       # Number of seconds simulated
sim_ticks                                2846106511000                       # Number of ticks simulated
final_tick                               2846106511000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 154405                       # Simulator instruction rate (inst/s)
host_op_rate                                   186958                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3504377822                       # Simulator tick rate (ticks/s)
host_mem_usage                                 600496                       # Number of bytes of host memory used
host_seconds                                   812.16                       # Real time elapsed on the host
sim_insts                                   125401163                       # Number of instructions simulated
sim_ops                                     151839522                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         8832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1669760                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1336112                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8514432                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         1408                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           219648                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           604112                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       400768                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12756096                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1669760                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       219648                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1889408                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8854144                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8871708                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker          138                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             26090                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             21399                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       133038                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           22                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              3432                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              9459                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         6262                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                199856                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          138346                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               142737                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3103                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              586682                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              469453                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2991607                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           495                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               77175                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              212259                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       140813                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4481946                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         586682                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          77175                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             663857                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3110967                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6157                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3117138                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3110967                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3103                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             586682                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             475610                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2991607                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          495                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              77175                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             212273                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       140813                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7599085                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        199856                       # Number of read requests accepted
system.physmem.writeReqs                       178961                       # Number of write requests accepted
system.physmem.readBursts                      199856                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     178961                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12785664                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      5120                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9927488                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12756096                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               11190044                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       80                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   23813                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          14250                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12367                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12533                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12905                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12918                       # Per bank write bursts
system.physmem.perBankRdBursts::4               15006                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12397                       # Per bank write bursts
system.physmem.perBankRdBursts::6               13141                       # Per bank write bursts
system.physmem.perBankRdBursts::7               13266                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12256                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12318                       # Per bank write bursts
system.physmem.perBankRdBursts::10              12174                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11385                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11522                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12342                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11687                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11559                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9829                       # Per bank write bursts
system.physmem.perBankWrBursts::1               10209                       # Per bank write bursts
system.physmem.perBankWrBursts::2               10296                       # Per bank write bursts
system.physmem.perBankWrBursts::3               10100                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9093                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9584                       # Per bank write bursts
system.physmem.perBankWrBursts::6               10130                       # Per bank write bursts
system.physmem.perBankWrBursts::7               10398                       # Per bank write bursts
system.physmem.perBankWrBursts::8                9607                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9596                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9832                       # Per bank write bursts
system.physmem.perBankWrBursts::11               9707                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9196                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9428                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9291                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8821                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          44                       # Number of times write queue was full causing retry
system.physmem.totGap                    2846106004500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     552                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  199276                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 174570                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     98276                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     48017                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     13343                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9981                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7920                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      6441                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5383                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4706                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      4161                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       742                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      273                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      252                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      151                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      128                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2212                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2498                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3704                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4717                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5610                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6075                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6457                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6849                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8256                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7351                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7669                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9425                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8094                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8319                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    11216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     9077                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8599                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     8116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1362                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2301                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     2267                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1793                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     2060                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     2701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1815                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1987                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1779                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1788                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1635                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1409                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      787                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      414                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      356                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      234                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       49                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        90865                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      249.965201                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     140.421700                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     309.995255                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          47261     52.01%     52.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18080     19.90%     71.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6274      6.90%     78.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3625      3.99%     82.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2837      3.12%     85.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1606      1.77%     87.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          998      1.10%     88.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1046      1.15%     89.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         9138     10.06%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          90865                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6548                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        30.509316                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      555.919891                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6546     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6548                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6548                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        23.689218                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.640113                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       40.676171                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31            6193     94.58%     94.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47              92      1.41%     95.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63              24      0.37%     96.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79              16      0.24%     96.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95              27      0.41%     97.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111             36      0.55%     97.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127            25      0.38%     97.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143            12      0.18%     98.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159            17      0.26%     98.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175             3      0.05%     98.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191            21      0.32%     98.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207            18      0.27%     99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223            11      0.17%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239             3      0.05%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255             2      0.03%     99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271             3      0.05%     99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287             5      0.08%     99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303             1      0.02%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319             4      0.06%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335             1      0.02%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351             8      0.12%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367             9      0.14%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383             3      0.05%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::400-415             2      0.03%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495             1      0.02%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527             3      0.05%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543             3      0.05%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::608-623             1      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::688-703             3      0.05%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::912-927             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6548                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5702655246                       # Total ticks spent queuing
system.physmem.totMemAccLat                9448455246                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    998880000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       28545.25                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  47295.25                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.49                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.49                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.48                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.93                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.22                       # Average write queue length when enqueuing
system.physmem.readRowHits                     166460                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     97567                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.32                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  62.89                       # Row buffer hit rate for writes
system.physmem.avgGap                      7513142.24                       # Average gap between requests
system.physmem.pageHitRate                      74.39                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  359425080                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  196114875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 815357400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                516060720                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           185893428240                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            83232319410                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1634649447000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1905662152725                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.569541                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2719260667390                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95037540000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     31802228860                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  327514320                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  178703250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 742887600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                489097440                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           185893428240                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            82208245725                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1635547757250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1905387633825                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.473086                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2720763679724                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95037540000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     30305178276                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          448                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1216                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          448                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1216                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            7                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             19                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          157                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst          270                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              427                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          157                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst          270                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          427                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          157                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst          270                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             427                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               20636360                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         13610949                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          1051916                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            13187821                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                9315921                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            70.640336                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                3367590                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            213586                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    69356                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort               69356                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        46232                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        23124                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples        69356                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0          69356    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        69356                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         6817                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean  9525.708083                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  8414.892081                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  6090.769517                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         6639     97.39%     97.39% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767          162      2.38%     99.77% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151            6      0.09%     99.85% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303            5      0.07%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687            4      0.06%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         6817                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    328505000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      328505000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    328505000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5248     76.98%     76.98% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1569     23.02%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6817                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        69356                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        69356                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6817                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6817                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        76173                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    17307432                       # DTB read hits
system.cpu0.dtb.read_misses                     63365                       # DTB read misses
system.cpu0.dtb.write_hits                   14534577                       # DTB write hits
system.cpu0.dtb.write_misses                     5991                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3513                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1432                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1922                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      561                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                17370797                       # DTB read accesses
system.cpu0.dtb.write_accesses               14540568                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         31842009                       # DTB hits
system.cpu0.dtb.misses                          69356                       # DTB misses
system.cpu0.dtb.accesses                     31911365                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3833                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3833                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          307                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3526                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3833                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3833    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3833                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2411                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean  9827.457901                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean  8615.260983                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  5288.530479                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          893     37.04%     37.04% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1467     60.85%     97.88% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575            9      0.37%     98.26% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           39      1.62%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            2      0.08%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2411                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    328041000                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      328041000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    328041000                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2111     87.56%     87.56% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          300     12.44%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2411                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3833                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3833                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2411                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2411                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         6244                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    38721907                       # ITB inst hits
system.cpu0.itb.inst_misses                      3833                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2217                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     7269                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                38725740                       # ITB inst accesses
system.cpu0.itb.hits                         38721907                       # DTB hits
system.cpu0.itb.misses                           3833                       # DTB misses
system.cpu0.itb.accesses                     38725740                       # DTB accesses
system.cpu0.numCycles                       164661578                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   79519346                       # Number of instructions committed
system.cpu0.committedOps                     95696233                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                      5042389                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     1874                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                  5527576937                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.070711                       # CPI: cycles per instruction
system.cpu0.ipc                              0.482926                       # IPC: instructions per cycle
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1879                       # number of quiesce instructions executed
system.cpu0.tickCycles                      128007340                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                       36654238                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.replacements           714687                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          500.798460                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           30351139                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           715199                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            42.437334                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        346166500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   500.798460                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.978122                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.978122                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          293                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           98                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         63691793                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        63691793                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     15776398                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       15776398                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     13416114                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      13416114                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       321622                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       321622                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       365571                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       365571                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       361457                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       361457                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     29192512                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        29192512                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     29514134                       # number of overall hits
system.cpu0.dcache.overall_hits::total       29514134                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       464236                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       464236                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       577383                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       577383                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       136671                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       136671                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21082                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21082                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20299                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        20299                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1041619                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1041619                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1178290                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1178290                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6143546304                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   6143546304                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9155597212                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   9155597212                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    318010226                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    318010226                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    454779772                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    454779772                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       214000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       214000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  15299143516                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  15299143516                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  15299143516                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  15299143516                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     16240634                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     16240634                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     13993497                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     13993497                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       458293                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       458293                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386653                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       386653                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381756                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       381756                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     30234131                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     30234131                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     30692424                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     30692424                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.028585                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.028585                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.041261                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.041261                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.298218                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.298218                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054524                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054524                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053173                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053173                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.034452                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.034452                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.038390                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.038390                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13233.670599                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13233.670599                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15857.060585                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15857.060585                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15084.442937                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15084.442937                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22404.048081                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22404.048081                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14687.849891                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14687.849891                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12984.191936                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12984.191936                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       514395                       # number of writebacks
system.cpu0.dcache.writebacks::total           514395                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        72393                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        72393                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       253509                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       253509                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14653                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14653                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data       325902                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       325902                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data       325902                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       325902                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       391843                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       391843                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       323874                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       323874                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       103461                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       103461                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6429                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6429                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20299                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        20299                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       715717                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       715717                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       819178                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       819178                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20386                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20386                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19085                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19085                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        39471                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        39471                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4433666662                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4433666662                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4919386398                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4919386398                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1621821456                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1621821456                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     96313514                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     96313514                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    423613728                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    423613728                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       205000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       205000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9353053060                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   9353053060                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10974874516                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  10974874516                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4276413999                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4276413999                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3259254500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3259254500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7535668499                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7535668499                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024127                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024127                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023145                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023145                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.225753                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.225753                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016627                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016627                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.053173                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053173                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023672                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.023672                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026690                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.026690                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11314.905873                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11314.905873                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15189.198262                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15189.198262                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15675.679299                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15675.679299                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14981.103438                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14981.103438                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20868.699345                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20868.699345                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13068.088448                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13068.088448                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13397.423412                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13397.423412                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209772.098450                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209772.098450                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170775.713911                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170775.713911                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190916.584302                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190916.584302                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1966290                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.784569                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           36747505                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1966802                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            18.683886                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6453364250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.784569                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999579                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999579                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          229                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          106                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         79395451                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        79395451                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     36747505                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       36747505                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     36747505                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        36747505                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     36747505                       # number of overall hits
system.cpu0.icache.overall_hits::total       36747505                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1966814                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1966814                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1966814                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1966814                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1966814                       # number of overall misses
system.cpu0.icache.overall_misses::total      1966814                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  18563219293                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  18563219293                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  18563219293                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  18563219293                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  18563219293                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  18563219293                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     38714319                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     38714319                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     38714319                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     38714319                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     38714319                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     38714319                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050803                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.050803                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050803                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.050803                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050803                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.050803                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9438.217998                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9438.217998                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9438.217998                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9438.217998                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9438.217998                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9438.217998                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1966814                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1966814                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1966814                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1966814                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1966814                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1966814                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3367                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         3367                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3367                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         3367                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  16587142707                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  16587142707                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  16587142707                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  16587142707                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  16587142707                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  16587142707                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    310652000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    310652000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    310652000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    310652000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.050803                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.050803                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.050803                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.050803                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.050803                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.050803                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8433.508561                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8433.508561                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8433.508561                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  8433.508561                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8433.508561                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  8433.508561                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92263.736264                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92263.736264                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1838523                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1838641                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit          103                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       232831                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          300437                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16148.129146                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           2913009                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          316676                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            9.198705                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle    2826267479000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  6686.637120                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    47.827012                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.093258                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  5824.484196                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1950.328123                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1638.759437                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.408120                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002919                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000006                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.355498                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.119039                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.100022                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.985604                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1008                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           17                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15214                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           12                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          310                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          388                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          298                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            8                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4157                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7950                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2796                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.061523                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.001038                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.928589                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        55309423                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       55309423                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        81547                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4240                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1895666                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data       400950                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       2382403                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       514393                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       514393                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28717                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        28717                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1850                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         1850                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       223495                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       223495                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        81547                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4240                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1895666                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       624445                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        2605898                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        81547                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4240                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1895666                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       624445                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       2605898                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          820                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          137                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst        71148                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data       100778                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total       172883                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26770                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        26770                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18449                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        18449                       # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        44897                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        44897                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          820                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          137                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        71148                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       145675                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       217780                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          820                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          137                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        71148                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       145675                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       217780                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     28707498                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3099498                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   3273175214                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data   3026145651                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   6331127861                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    497876262                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    497876262                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    373490824                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    373490824                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       199000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       199000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2237004716                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2237004716                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     28707498                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3099498                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3273175214                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   5263150367                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   8568132577                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     28707498                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3099498                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3273175214                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   5263150367                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   8568132577                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        82367                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4377                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1966814                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data       501728                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total      2555286                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       514393                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       514393                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55487                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        55487                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20299                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        20299                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       268392                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       268392                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        82367                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4377                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1966814                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       770120                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2823678                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        82367                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4377                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1966814                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       770120                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2823678                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.009955                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.031300                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.036174                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.200862                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.067657                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.482455                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.482455                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.908863                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.908863                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.167281                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.167281                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.009955                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.031300                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.036174                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.189159                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.077126                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.009955                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.031300                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.036174                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.189159                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.077126                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35009.143902                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22624.072993                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46005.161269                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 30027.839915                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36620.881527                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18598.291446                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18598.291446                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20244.502358                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20244.502358                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49825.260396                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49825.260396                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35009.143902                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22624.072993                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46005.161269                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36129.400151                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 39343.064455                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35009.143902                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22624.072993                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46005.161269                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36129.400151                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 39343.064455                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs           91                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    30.333333                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       200924                       # number of writebacks
system.cpu0.l2cache.writebacks::total          200924                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst           68                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data          431                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total          499                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         3081                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         3081                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           68                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3512                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         3580                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           68                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         3512                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         3580                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          820                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          137                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        71080                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data       100347                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total       172384                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       246966                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       246966                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        26770                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        26770                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        18449                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18449                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41816                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        41816                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          820                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          137                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        71080                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       142163                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       214200                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          820                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          137                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        71080                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       142163                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       246966                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       461166                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3367                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20386                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        23753                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        19085                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        19085                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3367                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        39471                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        42838                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     23361000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2208000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   2800542786                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data   2349073394                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   5175185180                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14549193181                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  14549193181                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    539459030                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    539459030                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    271290805                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    271290805                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       160000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       160000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1612964489                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1612964489                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     23361000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2208000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2800542786                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3962037883                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   6788149669                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     23361000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2208000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2800542786                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3962037883                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  14549193181                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  21337342850                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    282144500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4113041750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4395186250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3115835500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3115835500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    282144500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7228877250                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7511021750                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009955                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.031300                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.036140                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.200003                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.067462                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.482455                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.482455                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.908863                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.908863                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.155802                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.155802                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009955                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.031300                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.036140                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.184599                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.075859                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009955                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.031300                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.036140                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.184599                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.163321                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28489.024390                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16116.788321                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39399.870371                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23409.502965                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30021.261718                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58911.725424                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58911.725424                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20151.626074                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20151.626074                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14704.905686                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14704.905686                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38572.902454                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38572.902454                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28489.024390                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16116.788321                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39399.870371                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27869.683975                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31690.708072                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28489.024390                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16116.788321                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39399.870371                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27869.683975                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58911.725424                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46268.247984                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201758.155106                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185037.100577                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163260.964108                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163260.964108                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183144.010793                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 175335.490686                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq       2715743                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      2641226                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        31021                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        19085                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       514393                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       305303                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36254                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        89358                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43016                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       112820                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           10                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           16                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       297586                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       284185                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3940361                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2387083                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11736                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       174847                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          6514027                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    126091520                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     86470884                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17508                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       329468                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         212909380                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     677925                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      4032687                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       1.164340                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.370584                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           3369954     83.57%     83.57% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2            662733     16.43%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       4032687                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    2258839735                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    115861999                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   2960687293                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1231161241                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      7364989                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     92493743                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups               18540788                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          6039472                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           931744                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             9588411                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                6940637                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            72.385685                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                8266914                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            716215                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    26399                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort               26399                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19296                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         7103                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples        26399                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0          26399    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        26399                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         2728                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean  9779.693548                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean  8843.591627                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  5628.626467                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191          924     33.87%     33.87% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         1671     61.25%     95.12% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575           66      2.42%     97.54% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767           58      2.13%     99.67% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959            1      0.04%     99.71% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151            5      0.18%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::90112-98303            1      0.04%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-106495            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::106496-114687            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         2728                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1622643264                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1622643264    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1622643264                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         2007     73.57%     73.57% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          721     26.43%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2728                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        26399                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        26399                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2728                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2728                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        29127                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    10801915                       # DTB read hits
system.cpu1.dtb.read_misses                     24746                       # DTB read misses
system.cpu1.dtb.write_hits                    6805241                       # DTB write hits
system.cpu1.dtb.write_misses                     1653                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2067                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      156                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   413                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      271                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                10826661                       # DTB read accesses
system.cpu1.dtb.write_accesses                6806894                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         17607156                       # DTB hits
system.cpu1.dtb.misses                          26399                       # DTB misses
system.cpu1.dtb.accesses                     17633555                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     2259                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                2259                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          181                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2078                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         2259                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           2259    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         2259                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1119                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean  9888.739946                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean  9049.592552                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  4688.260195                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-4095          127     11.35%     11.35% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          167     14.92%     26.27% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          537     47.99%     74.26% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          253     22.61%     96.87% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479            2      0.18%     97.05% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575            3      0.27%     97.32% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           16      1.43%     98.75% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767           11      0.98%     99.73% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            2      0.18%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::45056-49151            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1119                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1622052264                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1622052264    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1622052264                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          951     84.99%     84.99% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          168     15.01%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1119                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2259                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2259                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1119                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1119                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         3378                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    39782626                       # ITB inst hits
system.cpu1.itb.inst_misses                      2259                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1157                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1864                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                39784885                       # ITB inst accesses
system.cpu1.itb.hits                         39782626                       # DTB hits
system.cpu1.itb.misses                           2259                       # DTB misses
system.cpu1.itb.accesses                     39784885                       # DTB accesses
system.cpu1.numCycles                       114626006                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   45881817                       # Number of instructions committed
system.cpu1.committedOps                     56143289                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                      4843481                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     2780                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                  5576973220                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.498288                       # CPI: cycles per instruction
system.cpu1.ipc                              0.400274                       # IPC: instructions per cycle
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2782                       # number of quiesce instructions executed
system.cpu1.tickCycles                       97881179                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                       16744827                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.replacements           194211                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          472.569028                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           17169326                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           194582                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            88.236970                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      90524286500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.569028                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.922986                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.922986                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          371                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          322                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           49                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.724609                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         35245180                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        35245180                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     10415746                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       10415746                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      6512410                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       6512410                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50058                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        50058                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        80074                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        80074                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71526                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        71526                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     16928156                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        16928156                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     16978214                       # number of overall hits
system.cpu1.dcache.overall_hits::total       16978214                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       157191                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       157191                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       144867                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       144867                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30819                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        30819                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16921                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        16921                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23675                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23675                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       302058                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        302058                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       332877                       # number of overall misses
system.cpu1.dcache.overall_misses::total       332877                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2309301217                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2309301217                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   3857781581                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   3857781581                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    316145498                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    316145498                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    557553671                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    557553671                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       527500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total       527500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   6167082798                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   6167082798                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   6167082798                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   6167082798                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     10572937                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     10572937                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      6657277                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      6657277                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        80877                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        80877                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96995                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        96995                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        95201                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        95201                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     17230214                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     17230214                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     17311091                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     17311091                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.014867                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.014867                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.021761                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.021761                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.381060                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.381060                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.174452                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.174452                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.248684                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.248684                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.017531                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.017531                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.019229                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.019229                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14691.052395                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14691.052395                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26629.816183                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 26629.816183                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18683.617871                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18683.617871                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23550.313453                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23550.313453                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20416.882844                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20416.882844                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18526.611325                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18526.611325                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       117850                       # number of writebacks
system.cpu1.dcache.writebacks::total           117850                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        15942                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        15942                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        52278                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total        52278                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12035                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12035                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        68220                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        68220                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        68220                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        68220                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       141249                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       141249                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        92589                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        92589                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29909                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        29909                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4886                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4886                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23675                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23675                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       233838                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       233838                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       263747                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       263747                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        14605                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        14605                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11936                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11936                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        26541                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        26541                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1867063577                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1867063577                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2294961861                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2294961861                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    485499507                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    485499507                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     80204246                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     80204246                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    520729829                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    520729829                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       512500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       512500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4162025438                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4162025438                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4647524945                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4647524945                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2322107500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2322107500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1843997501                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1843997501                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4166105001                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4166105001                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.013359                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.013359                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013908                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.013908                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.369808                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.369808                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050374                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.050374                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.248684                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.248684                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.013571                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.013571                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.015236                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.015236                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13218.242798                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13218.242798                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24786.549817                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24786.549817                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16232.555652                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16232.555652                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16415.113795                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16415.113795                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21994.924139                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21994.924139                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17798.755711                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17798.755711                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17621.148089                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17621.148089                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158994.008901                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 158994.008901                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154490.407255                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154490.407255                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 156968.652312                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 156968.652312                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           947892                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.324313                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           38832195                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           948404                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            40.944782                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      72125006000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.324313                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975243                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975243                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          461                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           51                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         80509602                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        80509602                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     38832195                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       38832195                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     38832195                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        38832195                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     38832195                       # number of overall hits
system.cpu1.icache.overall_hits::total       38832195                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       948404                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       948404                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       948404                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        948404                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       948404                       # number of overall misses
system.cpu1.icache.overall_misses::total       948404                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8190397665                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   8190397665                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   8190397665                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   8190397665                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   8190397665                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   8190397665                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     39780599                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     39780599                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     39780599                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     39780599                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     39780599                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     39780599                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.023841                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.023841                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.023841                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.023841                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.023841                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.023841                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8635.979672                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8635.979672                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8635.979672                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8635.979672                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8635.979672                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8635.979672                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       948404                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       948404                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       948404                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       948404                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       948404                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       948404                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          112                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          112                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7240674335                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   7240674335                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7240674335                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   7240674335                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7240674335                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   7240674335                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10306250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10306250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10306250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     10306250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.023841                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.023841                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.023841                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.023841                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.023841                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.023841                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7634.588567                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7634.588567                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7634.588567                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  7634.588567                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7634.588567                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  7634.588567                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92020.089286                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92020.089286                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92020.089286                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92020.089286                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued       197682                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       197698                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           14                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        58310                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           54781                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15316.530997                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1176536                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           69755                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           16.866691                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  7883.130354                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    45.774786                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.102173                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4372.978904                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2161.890501                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   852.654278                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.481148                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002794                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000006                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.266905                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.131951                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.052042                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.934847                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1060                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           47                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13867                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          654                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          402                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           12                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           17                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           18                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          309                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         6188                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         7370                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.064697                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002869                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.846375                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        22471002                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       22471002                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        28799                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2667                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst       927404                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data       105047                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total       1063917                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       117850                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       117850                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1629                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         1629                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          948                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total          948                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27664                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        27664                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        28799                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2667                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       927404                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       132711                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        1091581                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        28799                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2667                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       927404                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       132711                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       1091581                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          641                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          224                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst        21000                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data        70995                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        92860                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28409                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        28409                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22727                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22727                       # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34889                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        34889                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          641                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          224                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        21000                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       105884                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       127749                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          641                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          224                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        21000                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       105884                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       127749                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     14838480                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4527497                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst    735996245                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data   1568239223                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   2323601445                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    538393885                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    538393885                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    458698584                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    458698584                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       502500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       502500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1371520229                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1371520229                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     14838480                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4527497                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    735996245                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   2939759452                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3695121674                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     14838480                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4527497                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    735996245                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   2939759452                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3695121674                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        29440                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2891                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       948404                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data       176042                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total      1156777                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       117850                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       117850                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        30038                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        30038                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23675                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23675                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        62553                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        62553                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        29440                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2891                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       948404                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       238595                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      1219330                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        29440                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2891                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       948404                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       238595                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      1219330                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021773                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.077482                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.022142                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.403284                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.080275                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.945769                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.945769                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.959958                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.959958                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.557751                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.557751                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021773                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.077482                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.022142                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.443781                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.104770                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021773                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.077482                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.022142                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.443781                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.104770                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23148.954758                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20212.040179                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35047.440238                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22089.431974                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 25022.630250                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18951.525397                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18951.525397                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20182.979892                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20182.979892                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39310.964172                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39310.964172                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23148.954758                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20212.040179                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35047.440238                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27763.962941                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 28924.857917                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23148.954758                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20212.040179                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35047.440238                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27763.962941                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 28924.857917                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs            0                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        31909                       # number of writebacks
system.cpu1.l2cache.writebacks::total           31909                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst           25                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data           89                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total          114                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          233                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          233                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           25                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          322                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          347                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           25                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          322                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          347                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          641                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          224                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst        20975                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        70906                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        92746                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        23372                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        23372                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28409                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28409                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22727                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22727                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34656                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        34656                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          641                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          224                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        20975                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       105562                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       127402                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          641                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          224                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        20975                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       105562                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        23372                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       150774                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        14605                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        14717                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11936                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11936                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        26541                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        26653                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     10662992                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3070499                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    597837255                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1104689269                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1716260015                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    913442152                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    913442152                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    453224001                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    453224001                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    342962233                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    342962233                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       437500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       437500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1116530031                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1116530031                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     10662992                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3070499                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    597837255                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2221219300                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   2832790046                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     10662992                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3070499                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    597837255                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2221219300                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    913442152                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   3746232198                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9363750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2205259000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2214622750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1754356999                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1754356999                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9363750                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3959615999                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3968979749                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021773                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.077482                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.022116                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.402779                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.080176                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.945769                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.945769                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.959958                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.959958                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.554026                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.554026                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021773                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.077482                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.022116                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.442432                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.104485                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021773                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.077482                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.022116                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.442432                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.123653                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28502.372110                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15579.630342                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18504.949162                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39082.755092                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39082.755092                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15953.535887                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15953.535887                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15090.519338                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15090.519338                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32217.510128                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32217.510128                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28502.372110                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21041.845550                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22235.051616                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28502.372110                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21041.845550                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39082.755092                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24846.672490                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83604.910714                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150993.426909                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 150480.583679                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146980.311578                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146980.311578                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83604.910714                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 149188.651483                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 148913.058530                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq       1570481                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      1215284                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        31021                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        11936                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       117850                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        29116                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36254                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        76106                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42118                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        86519                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq            6                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           16                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        85085                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        67041                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1897032                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       831140                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7228                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        62942                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2798342                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     60705024                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25653404                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        11564                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       117760                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          86487752                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     646083                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      1988037                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       1.303225                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.459652                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1           1385215     69.68%     69.68% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2            602822     30.32%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1988037                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy     835355978                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     80571000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   1423456915                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    410007475                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      4338499                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     33513487                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31003                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31003                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
system.iobus.trans_dist::WriteResp              23198                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162796                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2483972                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40091000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           198954212                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84718000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36786767                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36433                       # number of replacements
system.iocache.tags.tagsinuse               14.479130                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36449                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         270363169000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.479130                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.904946                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.904946                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328203                       # Number of tag accesses
system.iocache.tags.data_accesses              328203                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          243                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          243                       # number of demand (read+write) misses
system.iocache.demand_misses::total               243                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          243                       # number of overall misses
system.iocache.overall_misses::total              243                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     31382127                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     31382127                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6655722318                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   6655722318                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide     31382127                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     31382127                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     31382127                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     31382127                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          243                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             243                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          243                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            243                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 129144.555556                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 129144.555556                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183737.917348                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 183737.917348                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 129144.555556                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 129144.555556                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 129144.555556                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 129144.555556                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         22459                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3430                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.547813                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          243                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          243                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          243                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          243                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     18687627                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     18687627                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4772040352                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4772040352                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     18687627                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     18687627                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     18687627                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     18687627                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76903.814815                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76903.814815                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131736.979682                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131736.979682                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76903.814815                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76903.814815                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76903.814815                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76903.814815                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   136145                       # number of replacements
system.l2c.tags.tagsinuse                64036.316369                       # Cycle average of tags in use
system.l2c.tags.total_refs                     380367                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   200629                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     1.895872                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   12112.427093                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    74.878570                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.028766                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     8551.494132                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2840.139732                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35681.498153                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    16.446887                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2203.793190                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      582.329943                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1973.279904                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.184821                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001143                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.130485                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.043337                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.544456                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000251                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.033627                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.008886                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.030110                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.977117                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        30113                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           44                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        34327                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          139                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         5558                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        24416                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           43                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          319                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         3300                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        30690                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.459488                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000671                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.523788                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  5288124                       # Number of tag accesses
system.l2c.tags.data_accesses                 5288124                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker          404                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker           85                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst              48346                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data              49709                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher        47536                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker          123                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker           32                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst              17643                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data               9297                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher         5444                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 178619                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          232833                       # number of Writeback hits
system.l2c.Writeback_hits::total               232833                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            2833                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             761                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                3594                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           161                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           166                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               327                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4206                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1689                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5895                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker           404                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            85                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               48346                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               53915                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        47536                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker           123                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            32                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               17643                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               10986                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         5444                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  184514                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          404                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           85                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              48346                       # number of overall hits
system.l2c.overall_hits::cpu0.data              53915                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        47536                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker          123                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           32                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              17643                       # number of overall hits
system.l2c.overall_hits::cpu1.data              10986                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         5444                       # number of overall hits
system.l2c.overall_hits::total                 184514                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker          138                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            22734                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             9861                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       133208                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           22                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             3332                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1132                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher         6262                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               176690                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          9235                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          2955                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             12190                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          697                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1269                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1966                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11244                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8331                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19575                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker          138                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             22734                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             21105                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       133208                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           22                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              3332                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              9463                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         6262                       # number of demand (read+write) misses
system.l2c.demand_misses::total                196265                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker          138                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            22734                       # number of overall misses
system.l2c.overall_misses::cpu0.data            21105                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       133208                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           22                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             3332                       # number of overall misses
system.l2c.overall_misses::cpu1.data             9463                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         6262                       # number of overall misses
system.l2c.overall_misses::total               196265                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker     11906500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        82500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst   1830615779                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    872554898                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  13804634964                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1919000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    276050505                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    100986272                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher    812337192                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    17711087610                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data     10802199                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      3228400                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     14030599                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1283464                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1219962                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      2503426                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1032599700                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    678696974                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1711296674                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker     11906500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        82500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1830615779                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   1905154598                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  13804634964                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      1919000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    276050505                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    779683246                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    812337192                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     19422384284                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker     11906500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        82500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1830615779                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   1905154598                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13804634964                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      1919000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    276050505                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    779683246                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    812337192                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    19422384284                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker          542                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker           86                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst          71080                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data          59570                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       180744                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker          145                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker           32                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst          20975                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          10429                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher        11706                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             355309                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       232833                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           232833                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        12068                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         3716                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           15784                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          858                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         1435                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2293                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15450                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        10020                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            25470                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          542                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           86                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           71080                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           75020                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       180744                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker          145                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           32                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           20975                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           20449                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11706                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              380779                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          542                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           86                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          71080                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          75020                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       180744                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker          145                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           32                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          20975                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          20449                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11706                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             380779                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.254613                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.011628                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.319837                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.165536                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.736998                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.151724                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.158856                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.108543                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.534939                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.497285                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.765247                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.795210                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.772301                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.812354                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.884321                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.857392                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.727767                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.831437                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.768551                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.254613                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.011628                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.319837                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.281325                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.736998                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.151724                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.158856                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.462761                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.534939                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.515430                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.254613                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.011628                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.319837                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.281325                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.736998                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.151724                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.158856                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.462761                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.534939                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.515430                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 86278.985507                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        82500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80523.259391                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 88485.437380                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 103632.176476                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87227.272727                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82848.290816                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 89210.487633                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 129724.878952                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 100238.200294                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1169.702112                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1092.521151                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1150.992535                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1841.411765                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   961.356974                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1273.360122                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91835.618997                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81466.447485                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 87422.563167                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86278.985507                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        82500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 80523.259391                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 90270.296044                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 103632.176476                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87227.272727                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 82848.290816                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 82392.818979                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 129724.878952                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 98959.999409                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86278.985507                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        82500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 80523.259391                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 90270.296044                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 103632.176476                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87227.272727                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 82848.290816                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 82392.818979                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 129724.878952                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 98959.999409                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              102156                       # number of writebacks
system.l2c.writebacks::total                   102156                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker          138                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        22733                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         9861                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       133208                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           22                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         3332                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1132                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher         6262                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          176689                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         9235                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         2955                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        12190                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          697                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1269                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1966                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11244                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8331                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19575                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker          138                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        22733                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        21105                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       133208                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           22                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         3332                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         9463                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6262                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           196264                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker          138                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        22733                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        21105                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       133208                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           22                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         3332                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         9463                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6262                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          196264                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3367                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        20386                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        14601                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        38466                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        19085                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11936                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        31021                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3367                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        39471                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26537                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        69487                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker     10173000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        70000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   1545823471                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    749260602                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  12163111570                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      1642500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    234290995                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     86797728                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher    735598364                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  15526768230                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    164742191                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     52500445                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    217242636                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     12465195                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     22538766                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     35003961                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    893597800                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    574508526                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1468106326                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     10173000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        70000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1545823471                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   1642858402                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  12163111570                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1642500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    234290995                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    661306254                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    735598364                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16994874556                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     10173000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        70000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1545823471                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   1642858402                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  12163111570                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1642500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    234290995                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    661306254                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    735598364                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16994874556                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    204708000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3714675750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6791250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1919935500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5846110500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2762262500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1533068501                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4295331001                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    204708000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6476938250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6791250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3453004001                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10141441501                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.254613                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.011628                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.319823                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.165536                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.736998                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.151724                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.158856                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.108543                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.534939                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.497283                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.765247                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.795210                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.772301                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.812354                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.884321                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.857392                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.727767                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.831437                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.768551                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.254613                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011628                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.319823                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.281325                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.736998                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.151724                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.158856                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.462761                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.534939                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.515428                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.254613                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011628                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.319823                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.281325                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.736998                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.151724                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.158856                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.462761                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.534939                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.515428                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73717.391304                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67999.096952                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75982.212960                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91309.167392                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74659.090909                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70315.424670                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76676.438163                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117470.195465                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 87876.258454                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17838.894532                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17766.648054                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17821.381132                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17884.067432                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17761.044917                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17804.659715                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79473.301316                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68960.332013                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 74999.046028                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73717.391304                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67999.096952                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77842.141767                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91309.167392                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74659.090909                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70315.424670                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69883.361936                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117470.195465                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 86591.909652                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73717.391304                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67999.096952                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77842.141767                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91309.167392                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74659.090909                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70315.424670                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69883.361936                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117470.195465                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 86591.909652                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182216.999411                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60636.160714                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131493.425108                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151981.243176                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144734.739324                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 128440.725620                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138465.265498                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164093.594031                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60636.160714                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 130120.360289                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 145947.321096                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              215398                       # Transaction distribution
system.membus.trans_dist::ReadResp             215398                       # Transaction distribution
system.membus.trans_dist::WriteReq              31021                       # Transaction distribution
system.membus.trans_dist::WriteResp             31021                       # Transaction distribution
system.membus.trans_dist::Writeback            138346                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            76455                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40833                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           14266                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            6                       # Transaction distribution
system.membus.trans_dist::ReadExReq             39995                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19465                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107916                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           38                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14158                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       663047                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       785159                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108896                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108896                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 894055                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162796                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1216                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28316                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19310684                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     19503012                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                24138468                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           124155                       # Total snoops (count)
system.membus.snoop_fanout::samples            578323                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  578323    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              578323                       # Request fanout histogram
system.membus.reqLayer0.occupancy            88747000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               22828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            12490999                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1169123868                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1173969642                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           37485233                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq             516846                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            516831                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             31021                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            31021                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           232833                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        36254                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           79939                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         41160                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         121099                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           16                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           16                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            51726                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           51726                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1083746                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       338123                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1421869                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34155096                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5564428                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               39719524                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          288847                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           989795                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.036873                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.188451                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 953298     96.31%     96.31% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  36497      3.69%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             989795                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          786931704                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           342000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         682239026                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         258695257                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------